Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 131950

Article: 131950
Subject: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058) RESOLVED
From: "MM" <mbmsv@yahoo.com>
Date: Thu, 8 May 2008 10:01:53 -0400
Links: << >>  << T >>  << A >>
"Bob" <rsg.uClinux@gmail.com> wrote in message 
news:c8e6fe8d-6a36-4cb7-81f3-a665207b9208@b64g2000hsa.googlegroups.com...
>
> Anyway, I was going to say I don't have time to try, but since you've
> been so good to me, I figure I could return the favor.  Yes, the
> second method does indeed work!  Seems to suggest there are two
> separate uses of this function, one which the FPGA requires pulses for
> whatever reason, and the other just time (erasing flash?)...

Thanks Bob. There was no need to return the favor, but I think this was time 
not wasted :) And, yes, Spartan-3 is based on the Virtex-II architecture.

/Mikhail 



Article: 131951
Subject: Re: Quartus 7.2 and PCI Express
From: axalay <axalay@gmail.com>
Date: Thu, 8 May 2008 07:41:47 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 8 =A7=DE=A7=D1=A7=DB, 17:23, G=A8=AErski Adam
<gorskia@.................wp....................pl..................>
wrote:
> axalay pisze:
>
>
>
> > Good day!
> > Have:
> > -Quartus 7.2 SP3
> > -Megacore IP SP2
> > Need:
> > -PCI Express.
>
> > But I have only time_limited.sof
> > In Quartus/tools/license Setup/MegaCore functions I see PCI Express.
>
> > And Quartus give a warinig:
> > using OpenCore Plus Hardvare evalution for a following cores
> > PCI Express Compiler (6A66_00A9) will use OpenCore Plus hardware
> > Evalution
>
> > It is uncorrect license file? Help!!! I need a crack :)
>
> So ,go to dealer :)
>
> Adam- =A7=B3=A7=DC=A7=E2=A7=ED=A7=E4=A7=EE =A7=E8=A7=DA=A7=E4=A7=DA=A7=E2=
=A7=E5=A7=D6=A7=DE=A7=ED=A7=DB =A7=E4=A7=D6=A7=DC=A7=E3=A7=E4 -
>
> - =A7=B1=A7=E0=A7=DC=A7=D1=A7=D9=A7=D1=A7=E4=A7=EE =A7=E8=A7=DA=A7=E4=A7=
=DA=A7=E2=A7=E5=A7=D6=A7=DE=A7=ED=A7=DB =A7=E4=A7=D6=A7=DC=A7=E3=A7=E4 -

We go to dealer when sertified product. Now I need help!! :)
Mail me a lines from license file: 6A66_00A9

Article: 131952
Subject: Re: ANNC: FPGA Design Software Webcast
From: ehsjr <e.h.s.j.r.removethespampunctuation@bellatlantic.net>
Date: Thu, 08 May 2008 15:00:31 GMT
Links: << >>  << T >>  << A >>
CBFalconer wrote:
> John Larkin wrote:
> 
>>bart <bart.borosky@latticesemi.com> wrote:
>>
>>
>>>Lattice is holding a webcast today, Wednesday, May 7th, on our
>>>latest version of our FPGA software design tools "ispLEVER 7.1
>>>FPGA Design Tool Technical Rollout." The presenter will be Troy
>>>Scott, from our software marketing group.
>>>
>>>If you're interested, the event takes place live at 11am Pacific,
>>>18:00 GMT. In addition, you will be able to view this webcast
>>>archive on-demand, at your convenience, starting a few hours
>>>after the live event takes place.
>>>
>>>You can register by clicking:
>>> http://www.latticesemi.com/corporate/webcasts/isplever7.1fpgadesigntool.cfm
>>
>>We dumped Lattice over buggy compilers and dinky performance.
>>Now that you're spamming our group, I'll make the ban permanent.
> 
> 
> You're wrong.  Proper announcements are quite topical.  The quality
> may be questionable, and that is also suitable for discussion.  Of
> course, making the announcement less than one hour before the event
> begins is indicative of poor thinking.  Even 24 hours notice would
> be cutting it close.
> 


It's a question of opinion, not of fact, so it's not a
matter of right or wrong.

Your observation "Proper announcements are quite topical."
supports the "it is not spam" point of view.

As you point out,  Lattice (or at least its representative
Mr. Borosky) has not given a lot of thought to getting the
notice out in a "proper" manner.  By "proper", I mean where
and when it would do Lattice the most good.  That supports
the "it is spam" point of view.

For the record, I agree with JL. Posted here as it was it is
spam, in my opinion.

Ed

Article: 131953
Subject: Re: Quartus 7.2 and PCI Express
From: =?GB2312?B?R6iucnNraSBBZGFt?=
Date: Thu, 08 May 2008 17:00:36 +0200
Links: << >>  << T >>  << A >>
axalay pisze:
> On 8 技忘抄, 17:23, G車rski Adam
> <gorskia@.................wp....................pl..................>
> wrote:
>> axalay pisze:
>>
>>
>>
>>> Good day!
>>> Have:
>>> -Quartus 7.2 SP3
>>> -Megacore IP SP2
>>> Need:
>>> -PCI Express.
>>> But I have only time_limited.sof
>>> In Quartus/tools/license Setup/MegaCore functions I see PCI Express.
>>> And Quartus give a warinig:
>>> using OpenCore Plus Hardvare evalution for a following cores
>>> PCI Express Compiler (6A66_00A9) will use OpenCore Plus hardware
>>> Evalution
>>> It is uncorrect license file? Help!!! I need a crack :)
>> So ,go to dealer :)
>>
>> Adam- 妊抗把抑找抆 扯我找我把批快技抑抄 找快抗扼找 -
>>
>> - 妤抉抗忘戒忘找抆 扯我找我把批快技抑抄 找快抗扼找 -
> 
> We go to dealer when sertified product. Now I need help!! :)
> Mail me a lines from license file: 6A66_00A9

Why you can't work with time limited sof ?

Adam

Article: 131954
Subject: Re: Quartus 7.2 and PCI Express
From: axalay <axalay@gmail.com>
Date: Thu, 8 May 2008 08:07:27 -0700 (PDT)
Links: << >>  << T >>  << A >>
because I need restart system? and windows is not see the devise

Article: 131955
Subject: ML300 evaluation board broken?
From: PG <pg@yahoo.co.uk>
Date: Thu, 08 May 2008 16:35:50 +0100
Links: << >>  << T >>  << A >>
Hi

After two years I am back trying to use the ML300 evaluation platform 
for some FPGA programming. I connected the MultilinX cable to the P114
connector in order to program the board over the JTAG interface. I 
pressed then the button FPGA-prog and since then I have some strange 
effects. The PLB & OPB LEDs are not sure if there is an bus error, they 
toggle between red and green. IN addition, the power monitor outputs a 
red LED for the 2,5V power supply. Strange effects and I think I dont 
have to mention in particular that I wasnt able to connect to the JTAG 
Chain ;). If i disconnect the platform from the power supply and I 
reconnect I have the same trouble. Anyone an idea what went wrong or 
could advise me how to proceed?

Many thanks!

Article: 131956
Subject: Re: Quartus 7.2 and PCI Express
From: ghelbig@lycos.com
Date: Thu, 8 May 2008 08:38:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 8, 7:41 am, axalay <axa...@gmail.com> wrote:
> On 8 =A7=DE=A7=D1=A7=DB, 17:23, G=A8=AErski Adam
> <gorskia@.................wp....................pl..................>
> wrote:
>
>
>
> > axalay pisze:
>
> > > Good day!
> > > Have:
> > > -Quartus 7.2 SP3
> > > -Megacore IP SP2
> > > Need:
> > > -PCI Express.
>
> > > But I have only time_limited.sof
> > > In Quartus/tools/license Setup/MegaCore functions I see PCI Express.
>
> > > And Quartus give a warinig:
> > > using OpenCore Plus Hardvare evalution for a following cores
> > > PCI Express Compiler (6A66_00A9) will use OpenCore Plus hardware
> > > Evalution
>
> > > It is uncorrect license file? Help!!! I need a crack :)
>
> > So ,go to dealer :)
>
> > Adam- =A7=B3=A7=DC=A7=E2=A7=ED=A7=E4=A7=EE =A7=E8=A7=DA=A7=E4=A7=DA=A7=
=E2=A7=E5=A7=D6=A7=DE=A7=ED=A7=DB =A7=E4=A7=D6=A7=DC=A7=E3=A7=E4 -
>
> > - =A7=B1=A7=E0=A7=DC=A7=D1=A7=D9=A7=D1=A7=E4=A7=EE =A7=E8=A7=DA=A7=E4=A7=
=DA=A7=E2=A7=E5=A7=D6=A7=DE=A7=ED=A7=DB =A7=E4=A7=D6=A7=DC=A7=E3=A7=E4 -
>
> We go to dealer when sertified product. Now I need help!! :)
> Mail me a lines from license file: 6A66_00A9

Do you realize that you are asking someone to violate their contract
agreement with Altera, perhaps costing them a lot of money, or their
job?

It is not good to ask someone to do this.

G.


Article: 131957
Subject: Re: EDK for spartan2?
From: ghelbig@lycos.com
Date: Thu, 8 May 2008 08:50:00 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 8, 3:17 am, taco <b...@joepie.org> wrote:
> Hi,
> We have a PC104 board with a spartan2 device. I tried to compile a
> microblaze system for this device but got the error "not supported for
> architecture spartan2". I've seen however that in the past this was
> possible. I'm using EDK9.2. Is the 10.1 supporting this device or is there
> still some old version lying around somewhere?
> Taco

The last EDK that supports the Spartan2 is version 6.3

ISE 6.3 is available at <http://www.xilinx.com/webpack/classics/
wpclassic/index.htm>

I'm guessing that you will need to contact your friendly local FAE to
get EDK-6.3

G.


Article: 131958
Subject: Re: Quartus 7.2 and PCI Express
From: axalay <axalay@gmail.com>
Date: Thu, 8 May 2008 08:51:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
If I dont find it, I do it in Xilinx devise - freedom of shoise

Article: 131959
Subject: Re: ANNC: FPGA Design Software Webcast
From: "Robert Miles" <robertmiles@bellsouthNOSPAM.net>
Date: Thu, 8 May 2008 10:53:36 -0500
Links: << >>  << T >>  << A >>

"David L. Jones" <altzone@gmail.com> wrote in message 
news:4822f3a7$1@dnews.tpgi.com.au...
>
> "BobW" <nimby_NEEDSPAM@roadrunner.com> wrote in message 
> news:q9KdnYE_8uqU2r_VnZ2dnUVZ_hmtnZ2d@giganews.com...
>>
>> "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in 
>> message news:o1e424d2h2uldtu4qm4589v667lu96hip8@4ax.com...
>>> On Wed, 7 May 2008 12:19:40 -0700 (PDT), John_H
>>> <newsgroup@johnhandwork.com> wrote:
>>>
>>>>John Larkin wrote:
>>>>>
>>>>> To Lattice:
>>>>>
>>>>> We dumped Lattice over buggy compilers and dinky performance. Now that
>>>>> you're spamming our group, I'll make the ban permanent.
>>>>>
>>>>>
>>>>> To the group:
>>>>>
>>>>> Whenever anybody spams us, please
>>>>>
>>>>> 1. Blackball them as a vendor
>>>>>
>>>>> 2. Say bad things about their companies and products, preferably with
>>>>> lots of google-searchable keywords.
>>>>>
>>>>> John
>>>>
>>>>Was this really necessary?
>>>>
>>>>If there were technical webcasts from any of the big vendors, I'd like
>>>>to know about them though preferably more than 8 minutes beforehand.
>>>>If the posts of this nature got to be more than a couple a month from
>>>>any one source I'd agree with the spam catagorization but it isn't
>>>>that frequent.
>>>>
>>>>I'm disappointed that you had problems with them in the past and won't
>>>>trust them for future designs because of your history; competition is
>>>>almost always good.  But is it reason to be publicly vocal?
>>>>
>>>>Kill-lists are easy to manage if bart's messages offend you.
>>>>
>>>>- John_H
>>>
>>>
>>> If we don't discourage commercial posts, newsgroups will be flooded
>>> with them. I can't kill-file the tens of thousands of companies who
>>> would spam newsgroups if they thought it would pay off. So let's make
>>> sure it *doesn't* pay off.
>>>
>>> If they want to advertise, let them pay for it somewhere else.
>>>
>>>
>>> John
>>>
>>
>> For what it's worth, I agree with John.
>>
>> It's a real shame that we, now, have to go out of our way to filter 
>> commercial and sexual posts. There are proper places for both of those. 
>> Usenet is not one of them, in my opinion.
>
> Come on guys, get over it, really.
> The heading clearly had "ANNC:" and what it was about clearly stated, so 
> the OP did the right thing.
> It only takes a split second to scan the header to see if you are 
> interested. If you aren't interested then you shouldn't have even opened 
> it.
> I'd consider this ON TOPIC and not spam as it was a one-off announcement 
> to the correct groups with the correct formatting.
> Some people might very well be interested, this is a professional design 
> group with many FPGA designers afer all.
>
> Dave.
The message was crossposted to five newsgroups, not just one.  Are the
people who say accept it in the same newsgroup as the one who say don't?



Article: 131960
Subject: Re: ANNC: FPGA Design Software Webcast
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Thu, 08 May 2008 09:11:13 -0700
Links: << >>  << T >>  << A >>
On Thu, 8 May 2008 10:53:36 -0500, "Robert Miles"
<robertmiles@bellsouthNOSPAM.net> wrote:

>
>"David L. Jones" <altzone@gmail.com> wrote in message 
>news:4822f3a7$1@dnews.tpgi.com.au...
>>
>> "BobW" <nimby_NEEDSPAM@roadrunner.com> wrote in message 
>> news:q9KdnYE_8uqU2r_VnZ2dnUVZ_hmtnZ2d@giganews.com...
>>>
>>> "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in 
>>> message news:o1e424d2h2uldtu4qm4589v667lu96hip8@4ax.com...
>>>> On Wed, 7 May 2008 12:19:40 -0700 (PDT), John_H
>>>> <newsgroup@johnhandwork.com> wrote:
>>>>
>>>>>John Larkin wrote:
>>>>>>
>>>>>> To Lattice:
>>>>>>
>>>>>> We dumped Lattice over buggy compilers and dinky performance. Now that
>>>>>> you're spamming our group, I'll make the ban permanent.
>>>>>>
>>>>>>
>>>>>> To the group:
>>>>>>
>>>>>> Whenever anybody spams us, please
>>>>>>
>>>>>> 1. Blackball them as a vendor
>>>>>>
>>>>>> 2. Say bad things about their companies and products, preferably with
>>>>>> lots of google-searchable keywords.
>>>>>>
>>>>>> John
>>>>>
>>>>>Was this really necessary?
>>>>>
>>>>>If there were technical webcasts from any of the big vendors, I'd like
>>>>>to know about them though preferably more than 8 minutes beforehand.
>>>>>If the posts of this nature got to be more than a couple a month from
>>>>>any one source I'd agree with the spam catagorization but it isn't
>>>>>that frequent.
>>>>>
>>>>>I'm disappointed that you had problems with them in the past and won't
>>>>>trust them for future designs because of your history; competition is
>>>>>almost always good.  But is it reason to be publicly vocal?
>>>>>
>>>>>Kill-lists are easy to manage if bart's messages offend you.
>>>>>
>>>>>- John_H
>>>>
>>>>
>>>> If we don't discourage commercial posts, newsgroups will be flooded
>>>> with them. I can't kill-file the tens of thousands of companies who
>>>> would spam newsgroups if they thought it would pay off. So let's make
>>>> sure it *doesn't* pay off.
>>>>
>>>> If they want to advertise, let them pay for it somewhere else.
>>>>
>>>>
>>>> John
>>>>
>>>
>>> For what it's worth, I agree with John.
>>>
>>> It's a real shame that we, now, have to go out of our way to filter 
>>> commercial and sexual posts. There are proper places for both of those. 
>>> Usenet is not one of them, in my opinion.
>>
>> Come on guys, get over it, really.
>> The heading clearly had "ANNC:" and what it was about clearly stated, so 
>> the OP did the right thing.
>> It only takes a split second to scan the header to see if you are 
>> interested. If you aren't interested then you shouldn't have even opened 
>> it.
>> I'd consider this ON TOPIC and not spam as it was a one-off announcement 
>> to the correct groups with the correct formatting.
>> Some people might very well be interested, this is a professional design 
>> group with many FPGA designers afer all.
>>
>> Dave.
>The message was crossposted to five newsgroups, not just one.  Are the
>people who say accept it in the same newsgroup as the one who say don't?
>

OK, now imagine every seminar, every call for papers, every new
product announcement, every investors conference call, and every new
goofy marketing idea being crossposted to five newsgroups, alongside
the offers for replica watches, sneakers, and discount drugs and porn.

We need to discourage commercial posts.

John


Article: 131961
Subject: Re: ANNC: FPGA Design Software Webcast
From: CBFalconer <cbfalconer@yahoo.com>
Date: Thu, 08 May 2008 13:24:56 -0400
Links: << >>  << T >>  << A >>
Robert Miles wrote:
> "David L. Jones" <altzone@gmail.com> wrote in message
>
... snip ...
>
>> Come on guys, get over it, really.  The heading clearly had
>> "ANNC:" and what it was about clearly stated, so the OP did the
>> right thing. It only takes a split second to scan the header to
>> see if you are interested. If you aren't interested then you
>> shouldn't have even opened it.
>>
>> I'd consider this ON TOPIC and not spam as it was a one-off
>> announcement to the correct groups with the correct formatting.
>>
>> Some people might very well be interested, this is a professional
>> design group with many FPGA designers afer all.
>
> The message was crossposted to five newsgroups, not just one.  Are
> the people who say accept it in the same newsgroup as the one who
> say don't?

I accepted it, and I am posting in comp.arch.embedded.

Please snip your quotes.

-- 
 [mail]: Chuck F (cbfalconer at maineline dot net) 
 [page]: <http://cbfalconer.home.att.net>
            Try the download section.


** Posted from http://www.teranews.com **

Article: 131962
Subject: Virtex XCV1000E-6FG860C
From: jon <jon@pyramidemail.com>
Date: Thu, 8 May 2008 10:26:05 -0700 (PDT)
Links: << >>  << T >>  << A >>
Need help on  a Virtex XCV1000E-6FG860C . I am short 500 pieces and
the only parts I see are coming from China brokers. Please call with
any quantity that you can supply. I need them ASAP.

Jon E. Hansen

(949)864-7745

Article: 131963
Subject: Re: ANNC: FPGA Design Software Webcast
From: CBFalconer <cbfalconer@yahoo.com>
Date: Thu, 08 May 2008 13:29:29 -0400
Links: << >>  << T >>  << A >>
John Larkin wrote:
> "Robert Miles" <robertmiles@bellsouthNOSPAM.net> wrote:
>> "David L. Jones" <altzone@gmail.com> wrote in message
>>
... snip ...
>>
>>> I'd consider this ON TOPIC and not spam as it was a one-off
>>> announcement to the correct groups with the correct formatting.
>>> Some people might very well be interested, this is a
>>> professional design group with many FPGA designers afer all.
>>
>> The message was crossposted to five newsgroups, not just one. 
>> Are the people who say accept it in the same newsgroup as the
>> one who say don't?
> 
> OK, now imagine every seminar, every call for papers, every new
> product announcement, every investors conference call, and every
> new goofy marketing idea being crossposted to five newsgroups,
> alongside the offers for replica watches, sneakers, and discount
> drugs and porn.
> 
> We need to discourage commercial posts.

But this was not a commercial post.  It was an announcement of
something of possible interest to all participants on those
newsgroups.  It should have had a follow-up setting also.

Please snip the quotes on your replies.

-- 
 [mail]: Chuck F (cbfalconer at maineline dot net) 
 [page]: <http://cbfalconer.home.att.net>
            Try the download section.


** Posted from http://www.teranews.com **

Article: 131964
Subject: Re: Virtex XCV1000E-6FG860C
From: austin <austin@xilinx.com>
Date: Thu, 08 May 2008 11:29:49 -0700
Links: << >>  << T >>  << A >>
jon,

Unauthorized distributors are likely to have slower parts re-marked as
faster parts so they can gouge you for more money....

-6 is the slowest, so maybe you won't have that problem.

Or, devices that look like our parts, but are empty inside, or just
remarked garbage (non-functional).

This is the most common results we have seen when we have looked into
these "sources."

I am also concerned that we made a gift of Virtex E to Universities a
long time ago.

These devices were "not suitable for commercial use" ...

Caveat Emptor!

Austin

Article: 131965
Subject: Re: ANNC: FPGA Design Software Webcast
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Fri, 09 May 2008 07:20:41 +1200
Links: << >>  << T >>  << A >>
Robert Miles wrote:
> 
> The message was crossposted to five newsgroups, not just one.  Are the
> people who say accept it in the same newsgroup as the one who say don't?

I'd agree that spanning 5 groups was on the lower end of the IQ scale.
The most relevent group would be comp.arch.fpga

-jg



Article: 131966
Subject: Re: Virtex XCV1000E-6FG860C
From: "BobW" <nimby_NEEDSPAM@roadrunner.com>
Date: Thu, 8 May 2008 13:29:59 -0700
Links: << >>  << T >>  << A >>

"austin" <austin@xilinx.com> wrote in message 
news:fvvgqu$oe22@cnn.xsj.xilinx.com...
> jon,
>
> Unauthorized distributors are likely to have slower parts re-marked as
> faster parts so they can gouge you for more money....
>
> -6 is the slowest, so maybe you won't have that problem.
>
> Or, devices that look like our parts, but are empty inside, or just
> remarked garbage (non-functional).
>
> This is the most common results we have seen when we have looked into
> these "sources."
>
> I am also concerned that we made a gift of Virtex E to Universities a
> long time ago.
>
> These devices were "not suitable for commercial use" ...
>
> Caveat Emptor!
>
> Austin

Ahhh. So you've been to Latin America, Austin?

Bob
-- 
== NOTE: I automatically delete all Google Group posts due to uncontrolled 
SPAM ==



Article: 131967
Subject: Spartan 3 Mapping Problem
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Thu, 08 May 2008 15:22:59 -0700
Links: << >>  << T >>  << A >>
So, I'm busily poking around at a Spartan 3 design, and can't get my 
latest iteration of things to build properly.  I've got all my pin 
locations defined, but make no recommendations to the tools as to which 
clocking resources to use how and where.  Yet when I try to map the 
design, I get:

---
ERROR:Place:1018 - A clock IOB / clock component pair have been found
that are not placed at an optimal clock IOB / clock site pair. The clock
component <INST_PLL/BUF10/BUFGMUX> is placed at site <BUFGMUX2>. The IO
component <EXT_10_MHZ> is placed at site <A11>. This will not allow the
use of the fast path between the IO and the Clock buffer. If this sub
optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message
to a WARNING and allow your design to continue. However, the use of this
override is highly discouraged as it may lead to very poor timing
results. It is recommended that this error condition be corrected in the
design. A list of all the COMP.PINs used in this clock placement rule is
listed below. These examples can be used directly in the .ucf file to
override this clock rule.
< NET "EXT_10_MHZ" CLOCK_DEDICATED_ROUTE = FALSE; >
---

Now it seems to me that, if I'm letting MAP pick which clock buffers 
should do what where, that I'm the last guy in the world it should be 
complaining to about not liking the decisions that get made.

For reference: my clocking situation is as follows:

8MHz  --O----+------BUFGCE>--------------8 MHz clock
              \----------data pins

10MHz --O----+------BUFGCE>--------------10 MHz clock
              \----------data pins

20MHz --O----BUFG>------+----------------20 MHz clock
                         \--DCM>--BUFG>---40 MHz clock

128MHz -O----BUFG>-----------------------128 MHz clock

which all gives me an XST clock report of:
----------------+----------------------------------------+-------+
Clock Signal    | Clock buffer(FF name)                  | Load  |
----------------+----------------------------------------+-------+
CLK128          | IBUFG+BUFG                             | 7854  |
CLK20           | IBUFG+BUFG                             | 2058  |
CLK20           | DCM_INST:CLK2X                         | 59    |
BOARDSYNC_IN    | IBUF+BUFGCE                            | 4     |
EXT_10_MHZ      | IBUF+BUFGCE                            | 5     |
----------------+----------------------------------------+-------+

So, I've got only one DCM used on a chip with 4, only 5 BUFGs used on a 
chip with 8, and yet somehow I can't get everything to fit nicely.  Any 
suggestions on what's going on/how to fix it?

Thanks,
Rob

--
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 131968
Subject: Re: Spartan 3 Mapping Problem
From: John_H <newsgroup@johnhandwork.com>
Date: Thu, 8 May 2008 15:50:54 -0700 (PDT)
Links: << >>  << T >>  << A >>
Rob Gaddi wrote:
<snip>
> For reference: my clocking situation is as follows:
>
> 8MHz  --O----+------BUFGCE>--------------8 MHz clock
>               \----------data pins
>
> 10MHz --O----+------BUFGCE>--------------10 MHz clock
>               \----------data pins
>
> 20MHz --O----BUFG>------+----------------20 MHz clock
>                          \--DCM>--BUFG>---40 MHz clock
>
> 128MHz -O----BUFG>-----------------------128 MHz clock
>
> which all gives me an XST clock report of:
> ----------------+----------------------------------------+-------+
> Clock Signal    | Clock buffer(FF name)                  | Load  |
> ----------------+----------------------------------------+-------+
> CLK128          | IBUFG+BUFG                             | 7854  |
> CLK20           | IBUFG+BUFG                             | 2058  |
> CLK20           | DCM_INST:CLK2X                         | 59    |
> BOARDSYNC_IN    | IBUF+BUFGCE                            | 4     |
> EXT_10_MHZ      | IBUF+BUFGCE                            | 5     |
> ----------------+----------------------------------------+-------+
>
> So, I've got only one DCM used on a chip with 4, only 5 BUFGs used on a
> chip with 8, and yet somehow I can't get everything to fit nicely.  Any
> suggestions on what's going on/how to fix it?
>
> Thanks,
> Rob
<snip>

Are all your clock inputs defined as one edge of the chip?  I'd
suggest using FPGA Editor to delve into your chip to understand where
the signals are easily routed from.  It may be that you *must* go from
one side to the other to use the pins you've chosen.  I recall some
suboptimal choices in the Spartan-2s that made me choose manually
where my clock buffers and DCMs would be so I haven't come across the
error you have lately.

- John_H

Article: 131969
Subject: Re: Spartan 3 Mapping Problem
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Thu, 08 May 2008 16:01:40 -0700
Links: << >>  << T >>  << A >>
John_H wrote:
> 
> Are all your clock inputs defined as one edge of the chip?  I'd
> suggest using FPGA Editor to delve into your chip to understand where
> the signals are easily routed from.  It may be that you *must* go from
> one side to the other to use the pins you've chosen.  I recall some
> suboptimal choices in the Spartan-2s that made me choose manually
> where my clock buffers and DCMs would be so I haven't come across the
> error you have lately.
> 
> - John_H

Three of them (including the one throwing the error and the one with the 
DCM on it) are along the top of the chip (CLK4, CLK6, and CLK7 pins) 
The fourth is down on the bottom on CLK0.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 131970
Subject: Re: Spartan 3 Mapping Problem
From: John_H <newsgroup@johnhandwork.com>
Date: Thu, 8 May 2008 16:44:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
Rob Gaddi wrote:
>
> Three of them (including the one throwing the error and the one with the
> DCM on it) are along the top of the chip (CLK4, CLK6, and CLK7 pins)
> The fourth is down on the bottom on CLK0.
<snip>

So are you going to look into the FPGA Editor view like I suggested?

Another question for you to ponder much more than to answer here: did
you instantiate the BUFGMUX primitives or are those coming from your
synthesizer?  It may be that you need to hook up the I1 channel rather
than the I0 on one or two of your BUFGMUXs to work with the routing
from the clock pins to the buffers... which is why I suggested looking
at the details of the part in FPGA Editor.

- John_H

Article: 131971
Subject: Re: Spartan 3 Mapping Problem
From: Marvin <marvin.tom@gmail.com>
Date: Thu, 8 May 2008 16:57:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
Rob,

Did you LOC your IOs down?  Each BUFG has a dedicated IO that should
be used.  A list of these IO locations are available from the Spartan
3 User Guide.  If you LOC the IO to one of the non-dedicated IOs, this
error message will appear.

Marvin

On May 8, 4:44 pm, John_H <newsgr...@johnhandwork.com> wrote:
> Rob Gaddi wrote:
>
> > Three of them (including the one throwing the error and the one with the
> > DCM on it) are along the top of the chip (CLK4, CLK6, and CLK7 pins)
> > The fourth is down on the bottom on CLK0.
>
> <snip>
>
> So are you going to look into the FPGA Editor view like I suggested?
>
> Another question for you to ponder much more than to answer here: did
> you instantiate the BUFGMUX primitives or are those coming from your
> synthesizer?  It may be that you need to hook up the I1 channel rather
> than the I0 on one or two of your BUFGMUXs to work with the routing
> from the clock pins to the buffers... which is why I suggested looking
> at the details of the part in FPGA Editor.
>
> - John_H


Article: 131972
Subject: Re: ANNC: FPGA Design Software Webcast
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Thu, 08 May 2008 18:09:01 -0700
Links: << >>  << T >>  << A >>
On Thu, 08 May 2008 13:29:29 -0400, CBFalconer <cbfalconer@yahoo.com>
wrote:

>John Larkin wrote:
>> "Robert Miles" <robertmiles@bellsouthNOSPAM.net> wrote:
>>> "David L. Jones" <altzone@gmail.com> wrote in message
>>>
>... snip ...
>>>
>>>> I'd consider this ON TOPIC and not spam as it was a one-off
>>>> announcement to the correct groups with the correct formatting.
>>>> Some people might very well be interested, this is a
>>>> professional design group with many FPGA designers afer all.
>>>
>>> The message was crossposted to five newsgroups, not just one. 
>>> Are the people who say accept it in the same newsgroup as the
>>> one who say don't?
>> 
>> OK, now imagine every seminar, every call for papers, every new
>> product announcement, every investors conference call, and every
>> new goofy marketing idea being crossposted to five newsgroups,
>> alongside the offers for replica watches, sneakers, and discount
>> drugs and porn.
>> 
>> We need to discourage commercial posts.
>
>But this was not a commercial post.  It was an announcement of
>something of possible interest to all participants on those
>newsgroups.


Well, since we all wear shoes, and most of us like sex, all the
sneaker and porn ads are of possible interest to us.

>
>Please snip the quotes on your replies.

Feel free to snip whatever you like.

John


Article: 131973
Subject: Re: ANNC: FPGA Design Software Webcast
From: CBFalconer <cbfalconer@yahoo.com>
Date: Thu, 08 May 2008 21:46:21 -0400
Links: << >>  << T >>  << A >>
John Larkin wrote:
> CBFalconer <cbfalconer@yahoo.com> wrote:
> 
... snip ...
>
>> Please snip the quotes on your replies.
> 
> Feel free to snip whatever you like.

The point of that request is to avoid burdoning all group users
with the burdon of paging down over irrelevant material, and to
reduce the overall load on the Usenet system.

-- 
 [mail]: Chuck F (cbfalconer at maineline dot net) 
 [page]: <http://cbfalconer.home.att.net>
            Try the download section.

** Posted from http://www.teranews.com **

Article: 131974
Subject: Anyway to secure a Xilinx NGC file ?
From: "fpganut" <rats@myhouse.com>
Date: Thu, 8 May 2008 23:26:42 -0700
Links: << >>  << T >>  << A >>
Hi,

Is there anyway to secure a Xilinx NGC file from being reverse engineered ?
Xilinx has a ngc2edif  utility to convert the binary ngc file into a 
readable netlist.
Still work of course but makes it a lot easier to copy a design.

So anyway to secure a NGC file ?

Thanks.

Jim 





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search