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On Sep 1, 6:09=A0am, morphiend <morphi...@gmail.com> wrote: > When you install EDK it will detect if you have Cygwin already > installed. If it finds it, it won't use its own version and just use > the one you have. I think that's a nice feature. I think it is a *terrible* feature. If EDK just uses it's own version of cygwin, it *always* works. By trying to use who-knows-what version that happens to be installed, it might work, it might not, it might work sometimes. This is not a good situation. (and how many times will I have to down rev make?!?) > I'd rather not have 10 different copies of Cygwin running around :P. I think the number of copies would be closer to two. Or perhaps you are using binary? :-) Alan NishiokaArticle: 134801
<randomdude@gmail.com> wrote in message news:61f17dbd-b201-4ea9-b646-49590a772e5a@73g2000hsx.googlegroups.com... On Sep 1, 8:21 am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > <randomd...@gmail.com> wrote in message > > news:b24b1f24-0ecb-4eb1-8193-26bdc61a1ff9@73g2000hsx.googlegroups.com... > On Sep 1, 4:52 am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > > > > > <randomd...@gmail.com> wrote in message > > >news:fdde256c-a1dd-4e7c-bae5-3f7b949f7004@x41g2000hsb.googlegroups.com... > > > > My main idea at the moment is an encrypting DIMM module, intended to > > > protect against 'cold boot' attacks, and the scenario that an attacker > > > is presented with a freshly-turned-off machine with some juicy secret > > > still in a DIMM module, which they can then remove, throw in to some > > > socket, and dump. > > > Perhaps the first order of business is to establish that this is a > > viable > > attack. Can someone really do that? SDRAM refresh cycles are on the > > order > > of <10 usec, otherwise data would be lost. I would think much simpler > > and > > more severe "attacks" would be available once you gained physical > > control > > of > > the machine. Cutting out the living and still beating heart idea tops > > them > > all in complexity. > > Yup, apparently so. Seehttp://citp.princeton.edu/memory/:) > > --------- > Thanks. > > In regards your original question, if viability encompasses usability, the > huge power footprint is a problem. Simpler, less intrusive solutions are > likely possible. For example, drawing down the residual charge in the > memory > cells will also render their old contents inaccessible. Hum, thanks - I hadn't thought of it in terms of power budget (I guess that shows my inexperience!). I'll look in to that in depth. What kind of less-intrusive solutions do you mean, though? How would you lower the residual power in each cell? The obvious way it to overwrite RAM with zeros on power-on, but this would be mitigated by transplanting the DIMM in question to another machine (or a custom board). ------- I don't know if it can be done, whether entirely externally or even with help on the memory chip. Speed and power draw, particularly for portables, are visible and of concern to end users. Just document the possibility, and what you found while researching alternatives.Article: 134802
On Sep 1, 9:42=A0pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > <randomd...@gmail.com> wrote in message > > news:61f17dbd-b201-4ea9-b646-49590a772e5a@73g2000hsx.googlegroups.com... > On Sep 1, 8:21 am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > > > > > <randomd...@gmail.com> wrote in message > > >news:b24b1f24-0ecb-4eb1-8193-26bdc61a1ff9@73g2000hsx.googlegroups.com... > > On Sep 1, 4:52 am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > > > > <randomd...@gmail.com> wrote in message > > > >news:fdde256c-a1dd-4e7c-bae5-3f7b949f7004@x41g2000hsb.googlegroups.com= ... > > > > > My main idea at the moment is an encrypting DIMM module, intended t= o > > > > protect against 'cold boot' attacks, and the scenario that an attac= ker > > > > is presented with a freshly-turned-off machine with some juicy secr= et > > > > still in a DIMM module, which they can then remove, throw in to som= e > > > > socket, and dump. > > > > Perhaps the first order of business is to establish that this is a > > > viable > > > attack. Can someone really do that? SDRAM refresh cycles are on the > > > order > > > of <10 usec, otherwise data would be lost. I would think much simpler > > > and > > > more severe "attacks" would be available once you gained physical > > > control > > > of > > > the machine. Cutting out the living and still beating heart idea tops > > > them > > > all in complexity. > > > Yup, apparently so. Seehttp://citp.princeton.edu/memory/:) > > > --------- > > Thanks. > > > In regards your original question, if viability encompasses usability, = the > > huge power footprint is a problem. Simpler, less intrusive solutions ar= e > > likely possible. For example, drawing down the residual charge in the > > memory > > cells will also render their old contents inaccessible. > > Hum, thanks - I hadn't thought of it in terms of power budget (I guess > that shows my inexperience!). I'll look in to that in depth. What kind > of less-intrusive solutions do you mean, though? How would you lower > the residual power in each cell? The obvious way it to overwrite RAM > with zeros on power-on, but this would be mitigated by transplanting > the DIMM in question to another machine (or a custom board). > > ------- > I don't know if it can be done, whether entirely externally or even with > help on the memory chip. Do you mean from a technical perspective? > Speed I don't suppose you could be any more specific? Is my assertion that I could use the extra spare clock (in a scenario where the system expects CL3 memory and the boar duses CL2) incorrect? If not, surely I could just tell the system that the DIMM is registered and do things that way? I couldn't find any way for the memory modules to 'stall' the host system, so I'm not sure how my approach could slow system speed. Or perhaps you mean that getting my FPGA design to hit timing would be difficult/impossible? > and power draw, particularly for portables, > are visible and of concern to end users. But I think there's a subset of those users that place more worry over the security of their data. What kind of ballpark power demands do you envision? Are my rough 'guestimates' of 'low tens to a couple hundred mW' way out?Article: 134803
On Sep 1, 11:01=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > software is expected to work, not make customers unhappy You're also talking about a company that at the same time a new release is available a service pack is available for download too. Personally, I like the feature since only have to configure one environment. EDK should be smart enough to detect the cygwin DLL version during install and default it self at that time. Here's an Answer Record on how to fix it though: http://www.xilinx.com/support/answers/23716.htm HTH, -- MikeArticle: 134804
On Mon, 1 Sep 2008 16:00:06 -0700 (PDT), morphiend <morphiend@gmail.com> wrote: >On Sep 1, 11:01 am, Antti <Antti.Luk...@googlemail.com> wrote: > >> software is expected to work, not make customers unhappy > >You're also talking about a company that at the same time a new >release is available a service pack is available for download too. > >Personally, I like the feature since only have to configure one >environment. EDK should be smart enough to detect the cygwin DLL >version during install and default it self at that time. > >Here's an Answer Record on how to fix it though: >http://www.xilinx.com/support/answers/23716.htm And another one, which solved my Cygwin problem http://www.xilinx.com/support/answers/24134.htm (changed handling of CRLF in text files) Any more? - BrianArticle: 134805
On 2 sept, 03:03, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Mon, 1 Sep 2008 16:00:06 -0700 (PDT), morphiend <morphi...@gmail.com> > wrote: > > >On Sep 1, 11:01=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > >> software is expected to work, not make customers unhappy > > >You're also talking about a company that at the same time a new > >release is available a service pack is available for download too. > > >Personally, I like the feature since only have to configure one > >environment. EDK should be smart enough to detect the cygwin DLL > >version during install and default it self at that time. > > >Here's an Answer Record on how to fix it though: > >http://www.xilinx.com/support/answers/23716.htm > > And another one, which solved my Cygwin problemhttp://www.xilinx.com/supp= ort/answers/24134.htm > (changed handling of CRLF in text files) > > Any more? > > - Brian well i solved it myself, its really trivial ren E:\Cygwin E:\CygwinIsXilinxBugTheyDontCareToFix that fixes it I was so happy! I did run the project and it PASSED no errors! but too early... I did run clean all and rebuild and now I got Xilinx REANME error damnit i had the reanme error before and i just do not recall i had it fixed i am trying again to fix the reanme error, but this time no luck the project is not building anymore and thats it nor does any other project build! and all those project have been building ok on the same PC with same EDK no updates or service packs installed! wait.. maybe the problem is that Xilinx supports only customers? and they know that i have consumed over 10K of actel silicon lately? hm.. i have disabled Xilinx talkback? so googletoolbarnotifier maybe? Xilinx - I would be real happy to consume xxx Xilinx silicon, but so far Xilinx has NONE to offer for cost sensitive consumer market area where also protection against design theft is a consern and PCB are may also be at premium. (Actel, Lattice and SiliconBlue all have products for that area) And please do not go say SiliconBlue products do not exist their device samples and devkit are currently in transit via express to me Xilinx the reason I once again tried to work with Xilinx tools EDK was to provide support for the accesory board I have designed for Xilinx development boards. This accessory board has been sold to more then 300 Xilinx customers by our distribution partner who also is Xilinx Alliance Partner. I would hope that this is enough reason for Xilinx consider me as someone who deserves to have WORKING xilinx tools not tools that fail because Xilinx software folks can not spell out RENAME and write reanme ??? Antti eh I missed a little its 3 hours past monday (I used to be angry because of xilinx bugs on mondays)Article: 134806
On 2 sept, 03:36, Antti <Antti.Luk...@googlemail.com> wrote: > On 2 sept, 03:03, Brian Drummond <brian_drumm...@btconnect.com> wrote: > > > > > On Mon, 1 Sep 2008 16:00:06 -0700 (PDT), morphiend <morphi...@gmail.com= > > > wrote: > > > >On Sep 1, 11:01=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > > >> software is expected to work, not make customers unhappy > > > >You're also talking about a company that at the same time a new > > >release is available a service pack is available for download too. > > > >Personally, I like the feature since only have to configure one > > >environment. EDK should be smart enough to detect the cygwin DLL > > >version during install and default it self at that time. > > > >Here's an Answer Record on how to fix it though: > > >http://www.xilinx.com/support/answers/23716.htm > > > And another one, which solved my Cygwin problemhttp://www.xilinx.com/su= pport/answers/24134.htm > > (changed handling of CRLF in text files) > > > Any more? > > > - Brian > > well i solved it myself, its really trivial > > ren E:\Cygwin E:\CygwinIsXilinxBugTheyDontCareToFix > > that fixes it > > I was so happy! > I did run the project and it PASSED no errors! > > but too early... > I did run clean all > and rebuild > > and now I got Xilinx REANME error > damnit > i had the reanme error before > and i just do not recall i had it fixed > i am trying again to fix the reanme error, but this time no luck > the project is not building anymore and thats it > nor does any other project build! > and all those project have been building ok on the same PC > with same EDK no updates or service packs installed! > > wait.. maybe the problem is that Xilinx supports only customers? > and they know that i have consumed over 10K of actel silicon lately? > hm.. i have disabled Xilinx talkback? so googletoolbarnotifier maybe? > > Xilinx - I would be real happy to consume xxx Xilinx silicon, but > so far Xilinx has NONE to offer for cost sensitive consumer > market area where also protection against design theft is a consern > and PCB are may also be at premium. > (Actel, Lattice and SiliconBlue all have products for that area) > > And please do not go say SiliconBlue products do not exist > their device samples and devkit are currently in transit via > express to me > > Xilinx the reason I once again tried to work with Xilinx tools EDK > was to provide support for the accesory board I have designed for > Xilinx development boards. > > This accessory board has been sold to more then 300 Xilinx > customers by our distribution partner who also is Xilinx Alliance > Partner. > > I would hope that this is enough reason for Xilinx consider me as > someone who deserves to have WORKING xilinx tools not tools > that fail because Xilinx software folks can not spell out RENAME and > write reanme ??? > > Antti > eh I missed a little its 3 hours past monday > (I used to be angry because of xilinx bugs on mondays) Ah solved! google remembered what I had solved before :) the reanme error does come because anti virus is classifying ISE9.2SP4 as a Virus (my wife says: right so!) ok, all i need todo is disable the antivirus and it will work (as i recall this is only relevant for 9.2SP4!) AnttiArticle: 134807
<randomdude@gmail.com> wrote in message news:9212d27d-bd7c-479e-bacf-72345456c9bb@c58g2000hsc.googlegroups.com... On Sep 1, 9:42 pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > <randomd...@gmail.com> wrote in message > > news:61f17dbd-b201-4ea9-b646-49590a772e5a@73g2000hsx.googlegroups.com... > On Sep 1, 8:21 am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > > > > > <randomd...@gmail.com> wrote in message > > >news:b24b1f24-0ecb-4eb1-8193-26bdc61a1ff9@73g2000hsx.googlegroups.com... > > On Sep 1, 4:52 am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > > > > <randomd...@gmail.com> wrote in message > > > >news:fdde256c-a1dd-4e7c-bae5-3f7b949f7004@x41g2000hsb.googlegroups.com... > > > > > My main idea at the moment is an encrypting DIMM module, intended to > > > > protect against 'cold boot' attacks, and the scenario that an > > > > attacker > > > > is presented with a freshly-turned-off machine with some juicy > > > > secret > > > > still in a DIMM module, which they can then remove, throw in to some > > > > socket, and dump. > > > > Perhaps the first order of business is to establish that this is a > > > viable > > > attack. Can someone really do that? SDRAM refresh cycles are on the > > > order > > > of <10 usec, otherwise data would be lost. I would think much simpler > > > and > > > more severe "attacks" would be available once you gained physical > > > control > > > of > > > the machine. Cutting out the living and still beating heart idea tops > > > them > > > all in complexity. > > > Yup, apparently so. Seehttp://citp.princeton.edu/memory/:) > > > --------- > > Thanks. > > > In regards your original question, if viability encompasses usability, > > the > > huge power footprint is a problem. Simpler, less intrusive solutions are > > likely possible. For example, drawing down the residual charge in the > > memory > > cells will also render their old contents inaccessible. > > Hum, thanks - I hadn't thought of it in terms of power budget (I guess > that shows my inexperience!). I'll look in to that in depth. What kind > of less-intrusive solutions do you mean, though? How would you lower > the residual power in each cell? The obvious way it to overwrite RAM > with zeros on power-on, but this would be mitigated by transplanting > the DIMM in question to another machine (or a custom board). > > ------- > I don't know if it can be done, whether entirely externally or even with > help on the memory chip. Do you mean from a technical perspective? > Speed I don't suppose you could be any more specific? Is my assertion that I could use the extra spare clock (in a scenario where the system expects CL3 memory and the boar duses CL2) incorrect? If not, surely I could just tell the system that the DIMM is registered and do things that way? I couldn't find any way for the memory modules to 'stall' the host system, so I'm not sure how my approach could slow system speed. Or perhaps you mean that getting my FPGA design to hit timing would be difficult/impossible? ---------- The only thing I had in mind was your CL2 to CL3. It's a noticeable throughput hit. > and power draw, particularly for portables, > are visible and of concern to end users. But I think there's a subset of those users that place more worry over the security of their data. What kind of ballpark power demands do you envision? Are my rough 'guestimates' of 'low tens to a couple hundred mW' way out? ------- Don't let me distract you. You're sniffing the right directions, and I haven't spent nearly as much time thinking about this as you.Article: 134808
In article <40ecd9be-0bb5-457c-8614-a0402d627188@73g2000hsx.googlegroups.com>, xenix <lastval@gmail.com> wrote: > Hello all, > I am looking to find information/books in Camera design with CCD and > FPGA. till now i havent find any. Have you something spotted? These guys: http://www3.elphel.com/index.php have an open source camera with an FPGA and daughterboards that have CMOS imagers and CCDs. You will be able to learn a lot by looking at their design and code, and even if you want to write all the FPGA stuff from scratch, you can use it as a hardware platform. -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 134809
On Aug 22, 11:12=A0pm, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > Do you really need to hook up a camera? > > If the primary goal is to demonstrate the processing algorythm in hardwar= e. > Then you can use a staticimageor video and pass the bitstream to the > hardware. > The bit stream could be passed via ethernet, usb or serial connections to > the FPGA and read back the same way. > > Projects to pass data to and from a xilinx chip are scattered all over th= e > internet. =A0Take a look at sites likewww.fpga4fun.com > to just pass data. > > If you do need to have a real time video feed, you could use the suggesti= on > above as a way to prove your alogrythm seperately from the circuit to > control the camera/sensor. > > "Ghazal" <gzl.ja...@gmail.com> wrote in message > > news:2ff87bd6-ffbc-4620-b47e-1ab625856f86@2g2000hsn.googlegroups.com... > > > Hello, > > > =A0 =A0I want to integrate animageprocessing algorithm (half tone pixel > > converter, etc.) in Xilinx Spartan-3 FPGA (for a demo project only), > > and the concern bugging me is how to get a simpleimageinput. > > > =A0* Which camera should I use > > =A0* Will it be directly controlled by the FPGA and if yes then how, if > > no then how will it be controlled > > =A0* How will it physically interface with the FPGA > > =A0* What will be theimageformat and how will it be read by the FPGA > > =A0* Will animagesensor be easier to interface and use or digital > > camera > > =A0* Will a video camera take a snapshotimagewhich can be processed > > =A0* Will any pre-processing or analog-to-digital conversion of the > >image/ captured snapshot be required > > =A0* Is there a Xilinx prototype board forimagecapturing only > > > If anyone has designed / worked on cameras / images with FPGA .... do > > let me know ... it will help me quick start the things here !!! > > Anxiously waiting. > > > Regards, > > Ghazal Javed I guess there are no simple solutions to Engineer's problems .... I got some ideas from the replies above but which camera to use is still undecided. I do not have time/ expertise to employ pre-processing of the image obtained from the sensor. It would be easier if use a camera which has been used with Xilinx FPGA boards/kits and has reference documents and schematics .I have come across CMOS camera's from Aptina (previously Micron) and Photon Focus but I have no idea of their interface with FPGA (data sheets are not available from Aptina/ Micron). I just want to have an RGB or YCbCR format input in to the FPGA with the simplest interface possible (CameraLink might be a difficult option for me). Hope there are more solutions around !!! Regards, Ghazal JavedArticle: 134810
Here it is the list as known today
Package size
1. 3x4 mm 65L04 SiliconBlue
2. 4x4 mm AGL030 Actel
3. 4x5 mm 65L08 SiliconBlue
4. 5x5 mm
=95 AGL030 Actel
=95 EPM240Z Altera
5. 5x6 mm 65L16 SiliconBlue
6. 6x6 mm
=95 AGL060 Actel
=95 EPM240/570 Altera
=95 65L02 SiliconBlue
=95 PolarPro QuickLogic
7. 7x7 mm EPM570Z Altera
8. 8x8 mm
=95 A3P/IGLOO Actel
=95 MachXO all, XP2-5,XP2-8 Lattice
=95 65L02,65L04 SiliconBlue
=95 PolarPro/ArticLink QuickLogic
=95 S3E Xilinx
I have listed Altera MAX2 as FPGA, because they much more like FPGA
than CPLD (array structure not product term based)
There is still little hope that Spartan-4 will fill in the chart and
rank up Xilinx a few places
Antti
Article: 134811On Sep 2, 8:46 am, Antti <Antti.Luk...@googlemail.com> wrote: > Here it is the list as known today .... > I have listed Altera MAX2 as FPGA, because they much more like FPGA > than CPLD (array structure not product term based) > > There is still little hope that Spartan-4 will fill in the chart and > rank up Xilinx a few places > > Antti It might be interesting to look at the size of the FPGA and associated hardware for programming as a whole. Some of the FPGAs listed above do not need a PROM, but some do. And sometimes the PROM (or SPI flash equivalent) is bigger than the FPGA itself. Do you think you actually could get hold of the SiBlue devices -in particular the ones with built-in flash config RAM? BartArticle: 134812
On Sep 2, 8:24=A0am, Ghazal <gzl.ja...@gmail.com> wrote: > On Aug 22, 11:12=A0pm, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > > > > > > > Do you really need to hook up a camera? > > > If the primary goal is to demonstrate the processing algorythm in hardw= are. > > Then you can use a staticimageor video and pass the bitstream to the > > hardware. > > The bit stream could be passed via ethernet, usb or serial connections = to > > the FPGA and read back the same way. > > > Projects to pass data to and from a xilinx chip are scattered all over = the > > internet. =A0Take a look at sites likewww.fpga4fun.com > > to just pass data. > > > If you do need to have a real time video feed, you could use the sugges= tion > > above as a way to prove your alogrythm seperately from the circuit to > > control the camera/sensor. > > > "Ghazal" <gzl.ja...@gmail.com> wrote in message > > >news:2ff87bd6-ffbc-4620-b47e-1ab625856f86@2g2000hsn.googlegroups.com... > > > > Hello, > > > > =A0 =A0I want to integrate animageprocessing algorithm (half tone pix= el > > > converter, etc.) in Xilinx Spartan-3 FPGA (for a demo project only), > > > and the concern bugging me is how to get a simpleimageinput. > > > > =A0* Which camera should I use > > > =A0* Will it be directly controlled by the FPGA and if yes then how, = if > > > no then how will it be controlled > > > =A0* How will it physically interface with the FPGA > > > =A0* What will be theimageformat and how will it be read by the FPGA > > > =A0* Will animagesensor be easier to interface and use or digital > > > camera > > > =A0* Will a video camera take a snapshotimagewhich can be processed > > > =A0* Will any pre-processing or analog-to-digital conversion of the > > >image/ captured snapshot be required > > > =A0* Is there a Xilinx prototype board forimagecapturing only > > > > If anyone has designed / worked on cameras / images with FPGA .... do > > > let me know ... it will help me quick start the things here !!! > > > Anxiously waiting. > > > > Regards, > > > Ghazal Javed > > I guess there are no simple solutions to Engineer's problems .... I > got some ideas from the replies above but which camera to use is still > undecided. I do not have time/ expertise to employ pre-processing of > the image obtained from the sensor. It would be easier if use a camera > which has been used with Xilinx FPGA boards/kits and has reference > documents and schematics .I have come across CMOS camera's from Aptina > (previously Micron) and Photon Focus but I have no idea of their > interface with FPGA (data sheets are not available from Aptina/ > Micron). =A0I just want to have an RGB or YCbCR format input in to the > FPGA with the simplest interface possible (CameraLink might be a > difficult option for me). > Hope there are more solutions around !!! > Regards, > Ghazal Javed- Hide quoted text - > > - Show quoted text - Hi Javed, I have build some FPGA cameras from a scratch using Micron sensors. I have some monochrome sensors MT9V403 capturing 200fps VGA frames. The camera has an USB interface for live image previev (100fps+) and processed data acquisition (3D points). Since Micron stopped producing this sensor I started development of new, low cost camera, based on the new MT9V033 (wide VGA, 60fps, global shutter). The project was started as a stereo camera with detachable extra head. The camera base module measures 40x47mm and incorporates Spartan3E 1200 or 1600, 64MB x16 DDR and Cypress FX2 for USB. If you (or anyone else) are interested I can sell you one of these with full Microblaze reference design when it is finished. You can choose sensor type - monochrome or color. Cheers, AlesArticle: 134813
On Sep 1, 9:04=A0pm, xenix <last...@gmail.com> wrote: > Hello all, > I am looking to find information/books in Camera design with CCD and > FPGA. till now i havent find any. Have you something spotted? > > regards Is CMOS sensor OK? See what I wrote to Javed: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/2ecda3b7= f4bef67c?hl=3DenArticle: 134814
On 2 sept, 11:57, bommels <bart.homm...@gmail.com> wrote: > On Sep 2, 8:46 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > Here it is the list as known today > .... > > I have listed Altera MAX2 as FPGA, because they much more like FPGA > > than CPLD (array structure not product term based) > > > There is still little hope that Spartan-4 will fill in the chart and > > rank up Xilinx a few places > > > Antti > > It might be interesting to look at the size of the FPGA and associated > hardware for programming as a whole. Some of the FPGAs listed above do > not need a PROM, but some do. And sometimes the PROM (or SPI flash > equivalent) is bigger than the FPGA itself. > > Do you think you actually could get hold of the SiBlue devices -in > particular the ones with built-in flash config RAM? > > Bart Hi Bart, the only item that needs configuration memory is at position 8, that is the Xilinx part i forgot that, this would shift Xilinx to position 9 as it is 2 chip solution ALL other devices in the list have nonvolatile configuration ALL SiBlue devices have nonvolatile OTP memory that is accessible as standard SPI for programming, isnt that neat? SiBlue devices can be loaded from standard SPI flash also of course or by MCU, etc.. and as of getting hold on them: 65L04 (8x8 package) samples and SiBlue devkit ARE at THIS moment in transit to me, that is they have sent by my agent to me, fully confirmed. SiBlue DID ship the order within advertized lead time, actually a little ahead. (not all package option are in production and/or available yet) the most interesting (largest in the smaller easyBGA) is, that is the 65L04 the 3x4 are 0.4mm full-grid BGAs not so fun to design in, unless really constrained by space AnttiArticle: 134815
On Sep 2, 11:23 am, Antti <Antti.Luk...@googlemail.com> wrote: > On 2 sept, 11:57, bommels <bart.homm...@gmail.com> wrote: > > > > > On Sep 2, 8:46 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > Here it is the list as known today > > .... > > > I have listed Altera MAX2 as FPGA, because they much more like FPGA > > > than CPLD (array structure not product term based) > > > > There is still little hope that Spartan-4 will fill in the chart and > > > rank up Xilinx a few places > > > > Antti > > > It might be interesting to look at the size of the FPGA and associated > > hardware for programming as a whole. Some of the FPGAs listed above do > > not need a PROM, but some do. And sometimes the PROM (or SPI flash > > equivalent) is bigger than the FPGA itself. > > > Do you think you actually could get hold of the SiBlue devices -in > > particular the ones with built-in flash config RAM? > > > Bart > > Hi Bart, > > the only item that needs configuration memory is at position 8, that > is the Xilinx part > i forgot that, this would shift Xilinx to position 9 as it is 2 chip > solution > > ALL other devices in the list have nonvolatile configuration > > ALL SiBlue devices have nonvolatile OTP memory that is accessible as > standard SPI for programming, isnt that neat? > SiBlue devices can be loaded from standard SPI flash also of course or > by MCU, etc.. > > and as of getting hold on them: > > 65L04 (8x8 package) samples and SiBlue devkit ARE at THIS moment in > transit to me, > that is they have sent by my agent to me, fully confirmed. > SiBlue DID ship the order within advertized lead time, actually a > little ahead. > (not all package option are in production and/or available yet) > > the most interesting (largest in the smaller easyBGA) is, that is the > 65L04 > the 3x4 are 0.4mm full-grid BGAs not so fun to design in, unless > really constrained by space > > Antti OK, thanks a lot for the info. We could get the SiBlue dev. kit, but not the packaged parts wich feature the flash-config RAM. But that was a few months ago, which is an eternity in their business I suppose. As I am not involved in the PCB design, I might reconsider them :-) Cheers, BartArticle: 134816
On 2008-09-01, David Brown <david@westcontrol.removethisbit.com> wrote: > I believe (my own thoughts) that in an FPGA design, generating and > compiling modules is equivalent to compilation in software, and routing > and placing is equivalent to static linking. If there are components > that are isolated and communicate through standard and fixed interfaces, > then it could be argued that these are separate "works" and not part of > a complete "derived work", and the GPL/LGPL will not spread across the > interface. But the opposite could also be argued - the router and > placer software will dig into components on each side of the interface, > and the implementation of these components will depend on each other. > This of course gives you a more efficient bitstream - but it means that > the final bitstream cannot be split into separate parts and is therefore > a single combined "work". First of all: Thanks to Genode Labs for releasing this source code under an open source license! I hope this initiative will bring you lot of goodwill and customers! However, I have a few things to say regarding open source and hardware. The license question for open source hardware is a pretty interesting one. I feel that there are many questions here such as the one you list above. My personal belief is that it is not legally possible to distribute a design which contains both components under GPL and components under a more restrictive license. Regarding your comments about standard interfaces: A GPL program which calls a proprietary library using a standardized calling convention specified in the ABI can not be legally distributed AFAIK. (Ignoring the system library exception.) Some things to think on: http://www.bitlaw.com/copyright/maskwork.html Someone has actually gone to the trouble of making a license for hardware: http://technocrat.net/d/2007/2/5/14355 <-- Some interesting discussion regarding a draft version of this license. http://www.tapr.org/ohl.html <-- A page with the complete license (follow the links on the top) Unfortunately the hardware license above is not aimed at HDL code according to the author. Another hardware license is the one included in Opencores' DDR SDRAM controller: http://www.opencores.org/projects.cgi/web/ddr_sdr/overview (Unfortunately I cannot link directly to the license file as Opencores now requires you to register to look at files in the CVS repository.) I'm not sure how much thought that went into the creation of this license and I'm therefore not willing to use it myself without reading the opinion of a lawyer about it. My personal belief is that there might be some problems with GPL as a license for HDL code. On the other hand, Sun has released OpenSparc under the GPL which I see as a clear indication that the GPL is a viable license for hardware. See http://www.opensparc.net/faqs/licensing/ for what they think this means in a hardware design. (They are using GPLv2 at the moment.) /AndreasArticle: 134817
Hi,
I wrote a dual-port ram model according to xst example, it should be
inferred to a dual-port block ram with both ports writable at the same
time but different addresses. However, I got an error msg - "You are
apparently trying to describe a RAM with several write ports for
signal <x>. This RAM cannot be implemented using distributed
resources." Any hints what might have gone wrong? thanks,
always @ (posedge clk)
if(ena)
begin
if(wea)
mem[addra] <= dia;
doa<=mem[addra];
end
always @ (posedge clk)
if(enb)
begin
if(web)
mem[addrb] <= dib;
dob<=mem[addrb];
end
Article: 134818On Aug 19, 3:22=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Tue, 19 Aug 2008 06:20:51 -0700 (PDT), rickman wrote: > > > =A0always @(posedge clock) > > =A0 =A0if (enable1) begin > > =A0 =A0 =A0if (write1) begin > > =A0 =A0 =A0 =A0mem[address1] <=3D write_data1; > > =A0 =A0 =A0 =A0read_data1 <=3D write_data1 ; > > =A0 =A0 =A0end else begin > > =A0 =A0 =A0 =A0read_data1 <=3D mem[address1]; > > =A0 =A0 =A0end > > =A0 =A0end > > =A0 =A0if (enable2) begin > > =A0 =A0 =A0if (write2) begin > > =A0 =A0 =A0 =A0mem[address2] <=3D write_data2; > > =A0 =A0 =A0 =A0read_data2 <=3D write_data2 ; > > =A0 =A0 =A0end else begin > > =A0 =A0 =A0 =A0read_data2 <=3D mem[address2]; > > =A0 =A0 =A0end > > =A0 =A0end > > >How about this as adualportmemory? > > It's a fine model, but I can't find a synth tool that > will infer DP memory when both ports can write. > > If only one of the two ports has write, it's OK. > -- Xilinx people, can you explain why? I experience the same situation here, the dual-port ram models provided by XST are the same as the above.Article: 134819
jack.harvard@googlemail.com wrote: > Hi, > > I wrote a dual-port ram model according to xst example, it should be > inferred to a dual-port block ram with both ports writable at the same > time but different addresses. However, I got an error msg - "You are > apparently trying to describe a RAM with several write ports for > signal <x>. This RAM cannot be implemented using distributed > resources." Any hints what might have gone wrong? thanks, > > always @ (posedge clk) > if(ena) > begin > if(wea) > mem[addra] <= dia; > doa<=mem[addra]; > end > > always @ (posedge clk) > if(enb) > begin > if(web) > mem[addrb] <= dib; > dob<=mem[addrb]; > end Have you used an attribute (or directive) to help the synthesizer realize you want BlockRAM rather than distributed RAM? You haven't mentioned the synthesizer.Article: 134820
On Sep 2, 2:07=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > jack.harv...@googlemail.com wrote: > > Hi, > > > I wrote a dual-port ram model according to xst example, it should be > > inferred to a dual-port block ram with both ports writable at the same > > time but different addresses. However, I got an error msg - "You are > > apparently trying to describe a RAM with several write ports for > > signal <x>. This RAM cannot be implemented using distributed > > resources." Any hints what might have gone wrong? thanks, > > > always @ (posedge clk) > > =A0if(ena) > > =A0 =A0begin > > =A0 =A0 if(wea) > > =A0 =A0 =A0 mem[addra] <=3D dia; > > =A0 =A0 doa<=3Dmem[addra]; > > =A0 =A0end > > > always @ (posedge clk) > > =A0if(enb) > > =A0 =A0begin > > =A0 =A0 if(web) > > =A0 =A0 =A0 mem[addrb] <=3D dib; > > =A0 =A0 dob<=3Dmem[addrb]; > > =A0 =A0end > > Have you used an attribute (or directive) to help the synthesizer > realize you want BlockRAM rather than distributed RAM? > > You haven't mentioned the synthesizer. Yes, if (* bram_map=3D"yes" *) should do?Article: 134821
On Aug 18, 4:10=A0pm, andersod2 <thechrisander...@gmail.com> wrote: > Ok, thanks much guys. =A0Haven't had time to work on this the last > couple of days, so will get back to it soon. =A0I was indeed using async > ram and had no idea that synchronous was required. =A0I read in one of > the xilinx docs (can't remember which) that the above declaration I > posted was all I needed for inference. =A0I think I will go the > instantiation route, though as that seems a bit more sure-fire. =A0Will > post if I have more problems with that route. Xilinx has async read ram distributed in the CLBs. You would use an async read template or similar behavior to infer them. As such, ISE may not have been inferring registers, but 32x1 or 16x2 distributed rams for your project. Still takes a lot of time to stitch together enough of them though. AndyArticle: 134822
On Sep 1, 10:11=A0am, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote: > Hi, > In a fairly large design I am doing some debugging on the system board > directly. When I discover a mistake and modify the vhdl code, the > whole design goes through synthesis and place-and-route. Many parts of > the design are never touched by my modifications, and I wonder if it > is possible to speed up the debug-modify-compile loop by setting up my > project in such a way that only the modified parts need to go through > the compile loop. The places I modify are typically inside entities > that are instantiated on the top-level, so in my opinion this should > be possible, but I do not know the tool, ISE 10.1, well enough to know > where to set the right flags. It is kind of irritating to wait for 5 > minutes to compile just because I insert an inverter. The really big > things are generated with coregen anyway so I am not supposed to > change anything in those modules anyway. > > Will be perfectly happy with a link to documentation to read as I am > not that familiar with the ISE tool yet. > > -- > Svenn Svenn, I recommend looking at using partitions to save compile time when making small changes - here's a white paper from Xilinx... http://www.xilinx.com/support/documentation/application_notes/xapp918.pdf Here are some additional Xilinx links on partitions: http://toolbox.xilinx.com/docsan/xilinx9/help/iseguide/mergedProjects/de_se= tup/html/de_setup_partitions_overview.htm http://toolbox.xilinx.com/docsan/xilinx92/help/iseguide/mergedProjects/de_s= etup/html/de_setup_p_partition_properties.htm http://toolbox.xilinx.com/docsan/xilinx10/isehelp/ds_p_using_partitions_des= ign_reuse_split.htm Hope this helps... AdamArticle: 134823
On Sep 2, 6:48=A0am, "jack.harv...@googlemail.com" <jack.harv...@googlemail.com> wrote: > On Sep 2, 2:07=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > > Have you used an attribute (or directive) to help the synthesizer > > realize you want BlockRAM rather than distributed RAM? > > > You haven't mentioned the synthesizer. > > Yes, if (* bram_map=3D"yes" *) should do The attribute says "XST" so... Two suggestions: first try (* BRAM_MAP=3D"yes" *) Second, try to use the syntax explicitly defined in the Xilinx reference: http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0054_15.htm= l The message you got suggests to me it was trying to used distributed memory and the BRAM_MAP attribute didn't "take."Article: 134824
On Sep 2, 3:04=A0am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > <randomd...@gmail.com> wrote in message > > news:9212d27d-bd7c-479e-bacf-72345456c9bb@c58g2000hsc.googlegroups.com... > On Sep 1, 9:42 pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > > > > > <randomd...@gmail.com> wrote in message > > >news:61f17dbd-b201-4ea9-b646-49590a772e5a@73g2000hsx.googlegroups.com... > > On Sep 1, 8:21 am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > > > > <randomd...@gmail.com> wrote in message > > > >news:b24b1f24-0ecb-4eb1-8193-26bdc61a1ff9@73g2000hsx.googlegroups.com.= .. > > > On Sep 1, 4:52 am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > > > > > <randomd...@gmail.com> wrote in message > > > > >news:fdde256c-a1dd-4e7c-bae5-3f7b949f7004@x41g2000hsb.googlegroups.c= om... > > > > > > My main idea at the moment is an encrypting DIMM module, intended= to > > > > > protect against 'cold boot' attacks, and the scenario that an > > > > > attacker > > > > > is presented with a freshly-turned-off machine with some juicy > > > > > secret > > > > > still in a DIMM module, which they can then remove, throw in to s= ome > > > > > socket, and dump. > > > > > Perhaps the first order of business is to establish that this is a > > > > viable > > > > attack. Can someone really do that? SDRAM refresh cycles are on the > > > > order > > > > of <10 usec, otherwise data would be lost. I would think much simpl= er > > > > and > > > > more severe "attacks" would be available once you gained physical > > > > control > > > > of > > > > the machine. Cutting out the living and still beating heart idea to= ps > > > > them > > > > all in complexity. > > > > Yup, apparently so. Seehttp://citp.princeton.edu/memory/:) > > > > --------- > > > Thanks. > > > > In regards your original question, if viability encompasses usability= , > > > the > > > huge power footprint is a problem. Simpler, less intrusive solutions = are > > > likely possible. For example, drawing down the residual charge in the > > > memory > > > cells will also render their old contents inaccessible. > > > Hum, thanks - I hadn't thought of it in terms of power budget (I guess > > that shows my inexperience!). I'll look in to that in depth. What kind > > of less-intrusive solutions do you mean, though? How would you lower > > the residual power in each cell? The obvious way it to overwrite RAM > > with zeros on power-on, but this would be mitigated by transplanting > > the DIMM in question to another machine (or a custom board). > > > ------- > > I don't know if it can be done, whether entirely externally or even wit= h > > help on the memory chip. > > Do you mean from a technical perspective? > > > Speed > > I don't suppose you could be any more specific? Is my assertion that I > could use the extra spare clock (in a scenario where the system > expects CL3 memory and the boar duses CL2) incorrect? If not, surely I > could just tell the system that the DIMM is registered and do things > that way? I couldn't find any way for the memory modules to 'stall' > the host system, so I'm not sure how my approach could slow system > speed. Or perhaps you mean that getting my FPGA design to hit timing > would be difficult/impossible? > > ---------- > The only thing I had in mind was your CL2 to CL3. It's a noticeable > throughput hit. > > > and power draw, particularly for portables, > > are visible and of concern to end users. > > But I think there's a subset of those users that place more worry over > the security of their data. What kind of ballpark power demands do you > envision? Are my rough 'guestimates' of 'low tens to a couple hundred > mW' way out? > > ------- > Don't let me distract you. You're sniffing the right directions, and I > haven't spent nearly as much time thinking about this as you. Heh, OK. Thanks a lot for your input, and to other posters, as well :)
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