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On Sep 30, 6:01 am, thutt <thutt...@comcast.net> wrote: > vlod...@gmail.com writes: > > Guys, > > > I am designing a conventional Digital down converter on virtex > > -4 Sx55 FPGA for GSM applications. > > > The Input clock frequency is above 160 Mhz for the initial CIC > > decimation filter. After decimation , the data is fed to low pass > > filter at a very low rate of ~1 Mhz > > > The issue is ,I am not able to generate this low frequency clcok with > > Virtex -4 DCM , obviously the min output frequency is 32 Mhz. > > > After I looked into the previous threads , i dont feel its a clean way > > to generate the divided clock by internal clock divider or clock > > gating circuit in FPGA . > > > Can anyone let me know any other way of generating the low frequency > > clock or is it safe to use internal clock divider considering my > > asynchronous design ( FIFO between each filter stage) ? > > > Iam using the latest FIR compiler to generate the LP filter core. but > > i do see the option of input sample per no of clock cycles in > > previous Distributed FIR core which made life easy. but the FIR > > compiler core doesnt have this option. > > > Please advice > > > Thanks in Advance > > > Vijay > > I'm certainly no expert in the field of hardware design, but I've had > good luck using the master clock signal and an 'enable' that runs at > the desired clock speed. I've successfully used this technique to > divide the Spartan 3E 50MHz clock down to 230Khz for serial port > transmission. > > I'd be happy to provide the entity which produces the 'enable' signal > and an example of how to use it if you're interested. please provide, I have currently been using a divided clock for spi-modules when I run into the problem of not having any more clock-buffer ressources in the spartan-3dsp that I am using. I developed a clock enabler circuit that was basically a counter and a pulse shortener to have an enable pulse that is 1 sys_clk wide every nth sys_clk period, where n is number of division. In my case 16. The shift registers and the state machine gets this 16ths enable to catch data on the sys_clk rising edge. Pulse shortener is made with one flip-flop clocked by sys_clk taking qn to and with sys_clk. Both the counter and the pulse shortener is clocked by the negative edge of sys_clk to have the clock enable signal high when rising_edge on sys_clk happens. (Does using negative edge (inverted sys_clk) need another clock buffer?) Now I have the issue that the SPI sclk that I generate needs to have a clock enable that is double the rate of the one that enables the shift registers in order to enable sclk toggling between the shift register clock enables. This seems like an awful lot of extra code (and logic) just to avoid spending a global clock buffer or risk hazards by using local nets and use the good old if risng_edge(sclk) then.... I could surely add another pulse shortener to the counter as the higher frequencies are available but I wonder if that is the best way to do it. I don't have enough DCMs to spend one on each SPI. We need them for FIR filters. I think I have understood the benefits of using clock enable, both through not having enough ressources and through different postings in webforums, so I sat down and coded and coded but didn't really like what I saw as a result. I have searched on the net for some hours without finding any document that really shows a best-practices solution on how to generate and use clock enables for peripheral serial devices. I really wonder why. It is not rocket science, is it? -- SvennArticle: 135426
FP wrote: > I have a quick question. I dont see Xilinx Virtex -5 sx95t device in > the list of devices in Xilinx ISE and CoreGen. How do I fix this > issue? I have unistalled and reinstalled ISE. Maybe you are using webpack. See: http://www.xilinx.com/ise_eval/index.htmArticle: 135427
On Oct 1, 4:43=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > FP wrote: > > I have a quick question. I dont see Xilinx Virtex -5 sx95t device in > > the list of devices in Xilinx ISE and CoreGen. How do I fix this > > issue? I have unistalled and reinstalled ISE. > > Maybe you are using webpack. > See:http://www.xilinx.com/ise_eval/index.htm Thank you for your quick reply. I am using Webpack.Article: 135428
On Oct 1, 5:53=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > me_rythm wrote: > > I have made a program which calculate FFT of two images (1024X1024) and > > then convolve them. I wish to know which FPGA chips would be best for t= his > > task, I want the result of the algorithm in real time (more than 30hz).= It > > takes around 10 seconds on my machine(AMD 1.8 Ghz Dual Core) for just o= ne > > convolution of both the images. I am thinking to use xilinx XC3S500E (5= 00k > > gates). I have no experience in FPGA, if anyone can help me i would rea= lly > > appreciate. > > You would do better to post in comp.arch.fpga. =A0(added) > > How many bits per sample? =A0Are you using the SSE feature > of the AMD machine? =A0That lets you process multiple 8 bit > values in one instruction, but might require assembly coding. > > I suggest looking at the systolic array architecture as > it works well for many problems like this. =A0You don't really > need FPGA experience, but digital logic experience helps a lot. > > Could you build such a device out of 7400 series TTL? > If so, you can figure out how to do it in an FPGA, but much > faster (in your time) and cheaper. =A0The thought process is > very different from C coding. > > Is this a commercial product or a class project? > > -- glen Did you take a look at this document? http://www.xilinx.com/support/documentation/ip_documentation/xfft_ds260.pdf To achieve the speed you need you may need a much larger part or one with more block RAM and multiplier resources.Article: 135429
me_rythm wrote: > I have made a program which calculate FFT of two images (1024X1024) and > then convolve them. I wish to know which FPGA chips would be best for this > task, I want the result of the algorithm in real time (more than 30hz). It > takes around 10 seconds on my machine(AMD 1.8 Ghz Dual Core) for just one > convolution of both the images. I am thinking to use xilinx XC3S500E (500k > gates). I have no experience in FPGA, if anyone can help me i would really > appreciate. You would do better to post in comp.arch.fpga. (added) How many bits per sample? Are you using the SSE feature of the AMD machine? That lets you process multiple 8 bit values in one instruction, but might require assembly coding. I suggest looking at the systolic array architecture as it works well for many problems like this. You don't really need FPGA experience, but digital logic experience helps a lot. Could you build such a device out of 7400 series TTL? If so, you can figure out how to do it in an FPGA, but much faster (in your time) and cheaper. The thought process is very different from C coding. Is this a commercial product or a class project? -- glenArticle: 135430
On Oct 1, 10:44 am, cs_post...@hotmail.com wrote: > Project behind schedule... but Quartus decides that today is the day > to demand a new license file. > > Which the server has promised but not yet mailed. > > Don't you just love control-freak software? Note to self: Next time don't ignore the "your license will expire in xx days" messages.Article: 135431
FP wrote: > On Oct 1, 4:43 pm, Mike Treseler <mtrese...@gmail.com> wrote: >> FP wrote: >>> I have a quick question. I dont see Xilinx Virtex -5 sx95t device in >>> the list of devices in Xilinx ISE and CoreGen. How do I fix this >>> issue? I have unistalled and reinstalled ISE. >> Maybe you are using webpack. >> See:http://www.xilinx.com/ise_eval/index.htm > > Thank you for your quick reply. I am using Webpack. This devices is not supported in the Webpack version. You need the full software version to use a XC5VSX95T device. Ed McGettigan -- Xilinx Inc.Article: 135432
On Wed, 1 Oct 2008 08:14:38 -0700 (PDT), Gabor <gabor@alacron.com> wrote: >On Sep 30, 4:53 am, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> To be honest, 580 us would surprise me too, but I don't know the >> internal details of MPMC. If it needs some intervention from the host >> (PPC or Microblaze), that would explain it. >> >> I would also double-check what is happening with C_SKIP_SIM_INIT_DELAY. >> Does initialisation take another 200 us without it? >> >> Anyway I am glad the simulation is basically working. >> >> - Brian > >I have seen similar timing with MIG 2.2 and DDR 2 memory attached to a >Virtex 5. > >It seems that the controller does a lot of calibration cycles to the >DRAM. I don't >think that the 200 uS startup delay was included as I also set the >appropriate >bit to skip it during simulation. Good answer to both questions; I think we have an explanation for the long startup time, and verified that it cannot easily be further reduced. - BrianArticle: 135433
Rob, Can you post a snippet of the failing path trace from TWR? Is the clock requirement 4X of the TS_SYS_CLK timespec as this multicycle exception is indicating? When you say the constraint is being ignored, what exactly do you mean? Are you looking for a header for the TS_MC_PHY_INIT_DATA_SEL_0, or are you seeing violations on paths that start from the */u_phy_init/u_ff_phy_init_data_sel instance? 'Greg Bring up this design in PlanAhead and search for the instances to make sure nothing simply like hierarchy separators is messing up the constraint? 'Greg "Rob" <BertyBooster@googlemail.com> wrote in message news:014cfdc3-140e-49aa-aa0c-d2c5f76d1f7f@a1g2000hsb.googlegroups.com... > Hi all, > > I'm having problems with ISE seemingly ignoring timing constraints set > in the UCF file. One of the constraints ignored comes from Xilinx's > MIG tool and looks like this: > > INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = > "TNM_PHY_INIT_DATA_SEL"; > TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO > FFS > "TS_SYS_CLK" * 4; > > I'm not getting any errors, such as unable to locate nets, rather the > constraint seems ignored and looking in the timing report it is these > very paths that are failing (by a long way). I thought that if the > target nets don't exist then you get a translate error. > > I am using partitions in the design. I've tried to do a build after a > "clean up project files" and the constraint is still ignored. > > Any ideas? > > RobArticle: 135434
To Group,
Sorry, I accidentally sent this to the wrong group.
CTW
>
>
> Hi everyone,
>
> I'm having a hell of a time trying to get an a/d pmc module working on a
> PMC_SPAN extension card on a MVME 5500 motherboard. I have the 2 PMC
> slots
> on the 5500 card populated with 2 VMetro FPGA01 PMC cards and they seem to
> work ok. After the system boots and I do a PCIDeviceShow(0) and I see
> devices 0 (host PCI bridge?),6 (First FPGA01 card) and 10 (PCI2PCI
> Bridge).
> PCIDeviceShow(1) shows devices 0,6 and 10 also with 6 being the 2nd FPGA01
> card.
> PCIDeviceShow(2) or (3) show no signs of my a/d card?
>
> I've attached a PDF file that shows the internal debug statements
> generated
> during autoconfiguration. In it certainly looks like device 10 on bus 0
> is
> acting as a bridge to the a/d card and it looks like it is being
> configured
> ok as far as I can tell. However after VxWorks boots I have tried using
> PCIFindDevice with the Vendor Id etc. to find the a/d card without
> success.
> I can use the input output calls (pciConfigWordLongIn/out etc) to talk to
> the FPGA01 cards but not the a/d. It seems like the bridge is not working
> but it seemed to work ok during auto config?
>
> Does anyone see what might be going on from the included dump file?
>
> Any help is appreciated.
>
> Chuck W.
>
>
>
Article: 135435glen herrmannsfeldt wrote: > > I think ICMP Source has been deprecated for more than 20 years. See > > http://www.google.com/search?q=icmp+source+quench+deprecated > > Is it that long ago? > > I remember trying to ftp a new version of NCSA Telnet to a PC, > (all the way from NCSA), the PC sending out source quench as > fast as it could, as its buffers kept overrunning. That would > have been a little less than 20 years ago. > > Many early PC ethernet cards had small buffers. Geesh! I just read a post by Dan Lanciani and it made me think of all the installs I did with Crynwr pkt drivers and BYU's IPX. Then I come here and I'm treated to another trip down the memory lane with NCSA Telnet! ;) I wonder if I'll now run into someone asking a question about Pegasus Mail, Spyder analyzers, and Coherent (Unix clone) Or a flame war will break about about Kermit being superior to NCSA Telnet! ;) -- hsb "Somehow I imagined this experience would be more rewarding" Calvin ******************************************************************** Due to the volume of email that I receive, I may not be able to reply to emails sent to my account. Please post a followup instead. ********************************************************************Article: 135436
> > Rob wrote: > > You may also want to use an older version of EDK that supports the > V2 PRO if you don't want to update the hardware I have used the library for the board which has all the specifications of the board, well i have shifted myself to 9.1i and the library is working fine...rob have u got any tutorials or materials in order to interface DDR..plz mail meArticle: 135437
ooppsss sorry the last msg was for gabor...im so screwed up with this stuff rob u r right man this is really really tricky...the more i get into it the more its getting complicated...Article: 135438
> > DDR interfaces on V2Pro devices is tricky, although do-able. well if u say they r do able then u may help me in this regard... > > Unfortunately it looks as though Xilinx have stopped supporting this. > >www.xilinx.com/memory nolonger mentions the V2. then wat is the possible solution for this?? > > How fast are you hoping to run the memory? Is it possible to use the > > Virtex-4 or Virtex-5 instead? sir, im using 512MB DDR RAM...virtex 4 and virtex 5 may not be the options available to me as i have the hardware and im not willing to waste it and buy new board for virtex 4 or 5...Article: 135439
Hi, I implemented some single precision floating point units in FPGA (IEEE 754 fully compliant) to calculate some complex mathematical equations, meanwhile, to debug the design modules, I've also got the C source code implementing the equations, with all the variables defined in single precision floating point. The Verilog code should have the same precision as I would expect from the C code. However, I found there are differences between the results generated from FPGA and C, the precision is about 10**(-5), I suppose this could be caused by round off errors. In Verilog, the round off is implemented as "round to the nearest (if equal, round to even)", just wondering when it is done in C, how the round off works, and how AMD/Intel processor does the round off for single precision floating point? thank you/merci/danke, -jArticle: 135440
Heiner Litz schrieb: > thanks @all > > I have already worked with with wrapper files, however found it too > time consuming to handle all the inputs/outputs. > > I will try a wrapper with only clk/res as IO and then use the KEEP > directive. > > heiner > You can disable the automated insertion of IO symbols with XST. To prevent the mapped from throwing away all logic from your design, disable the "trim unconnected signals" in ISE. > On Oct 1, 1:25 am, Andy <jonesa...@comcast.net> wrote: >> On Sep 30, 2:27 pm, Kevin Neilson >> >> >> >> <kevin_neil...@removethiscomcast.net> wrote: >>> Heiner Litz wrote: >>>> Hi, >>>> I want to perform reasonable post place&route timing analysis for some >>>> RTL modules. The modules have a higher pin count as the FPGA itself. >>>> ISE always tries to map the modules I/Os to specific IO pads, so its >>>> not possible to make post P&R timing analysis for such (internally >>>> used) modules. >>>> The post synthesis timing is unrealistic, so how can I get a timing >>>> estimation including wire delay for dedicated modules? >>>> Any ideas? >>> If the problem is that you don't have enough pins on the device, you >>> could make sure all the I/O are registered, instruct the synthesizer not >>> to add IOB pads, and put syn_keep or syn_preserve (or whatever) HDL >>> directives on the I/O registers to make sure they don't get pruned. >>> Then you could have a static timing analysis even though no pins are >>> connected. You won't be able to easily use this for a simulation, since >>> none of the I/Os will come out to top-level ports. -Kevin >> No, just turn all those external registers into a parallel/serial >> shift register, and only output the serial output. >> >> Reverse for the input: serial/parallel shift register, and the only >> chip-level input is the serial input. >> >> A clock, input and output pin; should fit in anything. >> >> Andy >Article: 135441
Hi, Have you implemented the sticky bit in your verilog implementation? Normally three more bits are added to the mantissa used internally. These bits are Guard, Round and Sticky. Guard and Round are just bit 25 and bit 26 of the mantissa. The sticky bit is an OR of all signals passed bit 27. The sticky bit is needed to have a correct rounding. Göran Bilski <jack.harvard@googlemail.com> wrote in message news:24a86a51-5aa4-4086-bfb4-a5b027bbf42c@f36g2000hsa.googlegroups.com... > Hi, > > I implemented some single precision floating point units in FPGA (IEEE > 754 fully compliant) to calculate some complex mathematical equations, > meanwhile, to debug the design modules, I've also got the C source > code implementing the equations, with all the variables defined in > single precision floating point. The Verilog code should have the same > precision as I would expect from the C code. However, I found there > are differences between the results generated from FPGA and C, the > precision is about 10**(-5), I suppose this could be caused by round > off errors. In Verilog, the round off is implemented as "round to the > nearest (if equal, round to even)", just wondering when it is done in > C, how the round off works, and how AMD/Intel processor does the round > off for single precision floating point? > > thank you/merci/danke, > -jArticle: 135442
Svenn Are Bjerkem wrote:
>
> I think I have understood the benefits of using clock enable, both
> through not having enough ressources and through different postings in
> webforums, so I sat down and coded and coded but didn't really like
> what I saw as a result.
>
> I have searched on the net for some hours without finding any document
> that really shows a best-practices solution on how to generate and use
> clock enables for peripheral serial devices. I really wonder why. It
> is not rocket science, is it?
Hi Svenn,
No it's not. Try something like this...
gen_enable : process(clk, res_n)
begin
if res_n = 0 then
count <= 0;
enable <= '0';
elsif rising_edge(clk) then
count <= (count + 1) mod 16;
if count = 15 then
enable <= '1';
else
enable <= '0';
end if;
end if;
end process;
do_stuff : process(clk, res_n)
begin
if res_n = 0 then
-- insert resets here
elsif rising_edge(clk) then
if enable = '1' then
-- insert enabled code here
end if;
end if;
end process;
HTH., Syms.
Article: 135443On 2008-10-02, jack.harvard@googlemail.com <jack.harvard@googlemail.com> wrote: > nearest (if equal, round to even)", just wondering when it is done in > C, how the round off works, and how AMD/Intel processor does the round > off for single precision floating point? You can actually control this on the x86 architecture. In C99 the function fesetround() can control this behavior according to the man page I'm reading on my Linux machine. /AndreasArticle: 135444
Hi, Does anybody make a standalone (i.e. non PC-based) programmer for Altera devices? Our product uses a Cyclone which loads its config from a EPCS1 1-Mbit EEPROM at power-up. To program the EEPROM in production we are using a PC running Quartus, and a ByteBlaster. This works OK, but is a bit cumbersome and prone to error (e.g. operator selects wrong object file) To program the Microchip PICs in the same product we use a fag-packet sized programmer from www.kanda.com - these are battery powered, data downloaded via a cable from a PC, the only user interface is one button and a green/red LED, completely idiot-proof. I've been trying to find an equivalent product for Altera devices, without success. I'm now considering making one for my own use, based on an MCU + external Flash chip. If I did, would it be worth selling?Article: 135445
On Oct 1, 4:33=A0pm, Svenn Are Bjerkem <svenn.bjer...@googlemail.com>
wrote:
> On Sep 30, 6:01 am, thutt <thutt...@comcast.net> wrote:
> I have currently been using a divided clock for spi-modules when I run
> into the problem of not having any more clock-buffer ressources in the
> spartan-3dsp that I am using. I developed a clock enabler circuit that
> was basically a counter and a pulse shortener to have an enable pulse
> that is 1 sys_clk wide every nth sys_clk period, where n is number of
> division. In my case 16.
Sounds good.
> The shift registers and the state machine gets this 16ths enable to
> catch data on the sys_clk rising edge.
>
> Pulse shortener is made with one flip-flop clocked by sys_clk taking
> qn to and with sys_clk. Both the counter and the pulse shortener is
> clocked by the negative edge of sys_clk to have the clock enable
> signal high when rising_edge on sys_clk happens. (Does using negative
> edge (inverted sys_clk) need another clock buffer?)
>
No, but it is also unneeded and not helpful to use the negative edge
of the clock. You should be using the rising edge for the clock
enable, using the negative edge simply cuts down by 1/2 the max clock
rate that you can run the design at.
> Now I have the issue that the SPI sclk that I generate needs to have a
> clock enable that is double the rate of the one that enables the shift
> registers in order to enable sclk toggling between the shift register
> clock enables.
So you need something that fires at 8 as well as 16.
> This seems like an awful lot of extra code (and logic)
A lot?? Once you have the counter to count your longest period
enable, adding additional count enables is simply adding a couple
lines of code. In the example below, signal 'ce2' which occurs every
8th clock cycle added one more case to the case statement, and three
assignments. This will get implemented as a simple decode of the
counter states, each clock enable will be implemented in a single
logic cell.
if rising_edge(clock) then
if (reset =3D '1') or (count =3D 15) then
count <=3D 0;
else
count <=3D count + 1;
end if;
case count is
when 7 =3D> ce2 <=3D '1';
when 15 =3D> ce1 <=3D '1'; ce2 <=3D '1';
when others =3D> ce1 <=3D '0'; ce2 <=3D '0';
end case;
end if;
> just to avoid spending a global clock buffer or risk hazards by using
> local nets and use the good old if risng_edge(sclk) then....
The issue is being able to pass timing analysis and reliably crossing
clock domains when you generate multiple clocks.
> I could
> surely add another pulse shortener to the counter as the higher
> frequencies are available but I wonder if that is the best way to do
> it. I don't have enough DCMs to spend one on each SPI. We need them
> for FIR filters.
I have no idea why you are using any DCMs for SPI. At the start you
said that you had implemented the counter and clock enable both
running off of the system clock. In any case, it is simple to add
whatever additional clock enables you may need.
>
> I think I have understood the benefits of using clock enable, both
> through not having enough ressources and through different postings in
> webforums, so I sat down and coded and coded but didn't really like
> what I saw as a result.
>
What did you see? Why did you not like it?
> I have searched on the net for some hours without finding any document
> that really shows a best-practices solution on how to generate and use
> clock enables for peripheral serial devices.
You didn't look too hard then. Symon reply also shows how to generate
and use the clock enables.
> I really wonder why. It
> is not rocket science, is it?
>
Not rocket science, just simple sequential boolean logic.
KJ
Article: 135446news@rblack01.plus.com wrote: > Hi, > > Does anybody make a standalone (i.e. non PC-based) programmer for > Altera devices? > Our product uses a Cyclone which loads its config from a EPCS1 1-Mbit > EEPROM at power-up. To program the EEPROM in production we are using > a PC running Quartus, and a ByteBlaster. This works OK, but is a bit > cumbersome and prone to error (e.g. operator selects wrong object > file) > > To program the Microchip PICs in the same product we use a fag-packet > sized programmer from www.kanda.com - these are battery powered, data > downloaded via a cable from a PC, the only user interface is one > button and a green/red LED, completely idiot-proof. > > I've been trying to find an equivalent product for Altera devices, > without success. I'm now considering making one for my own use, based > on an MCU + external Flash chip. If I did, would it be worth selling? > If you're in development, why is the Byteblaster cumbersome--I don't find it to be so. And when you transfer to production, Altera can ship your flash device pre-programmed.Article: 135447
On Oct 1, 6:59=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > FP wrote: > > On Oct 1, 4:43 pm, Mike Treseler <mtrese...@gmail.com> wrote: > >> FP wrote: > >>> I have a quick question. I dont see Xilinx Virtex -5 sx95t device in > >>> the list of devices in Xilinx ISE and CoreGen. How do I fix this > >>> issue? I have unistalled and reinstalled ISE. > >> Maybe you are using webpack. > >> See:http://www.xilinx.com/ise_eval/index.htm > > > Thank you for your quick reply. I am using Webpack. > > This devices is not supported in the Webpack version. =A0You need the ful= l > software version to use a XC5VSX95T device. > > Ed McGettigan > -- > Xilinx Inc. This sort of issue pops up a lot on the Xilinx forums. Perhaps the WebPack download page should have a more evident link to the device support on the Xilinx site. I found the information in the ISE Design Suite release notes, but it isn't obvious to the average WebPack user (read newbie) that you need to search around for this information. Just my 2 cents, GaborArticle: 135448
On Thu, 2 Oct 2008 10:13:20 +0100, "Symon" <symon_brewer@hotmail.com>
wrote:
>Svenn Are Bjerkem wrote:
>>
>> I think I have understood the benefits of using clock enable, both
>> through not having enough ressources and through different postings in
>> webforums, so I sat down and coded and coded but didn't really like
>> what I saw as a result.
>>
>> I have searched on the net for some hours without finding any document
>> that really shows a best-practices solution on how to generate and use
>> clock enables for peripheral serial devices. I really wonder why. It
>> is not rocket science, is it?
>
>Hi Svenn,
>No it's not. Try something like this...
>
>gen_enable : process(clk, res_n)
> begin
> if res_n = 0 then
> count <= 0;
> enable <= '0';
> elsif rising_edge(clk) then
> count <= (count + 1) mod 16;
> if count = 15 then
> enable <= '1';
> else
> enable <= '0';
> end if;
> end if;
> end process;
or: (2 changes; (a) using default initialisations
(b) extend by adding a 2x clock enable)
gen_enable : process(clk, res_n)
begin
if res_n = 0 then
count <= 0;
enable <= '0';
enable_2x <= '0';
elsif rising_edge(clk) then
enable <= '0';
enable_2x <= '0';
count <= (count + 1) mod 16;
if count = 15 then
enable <= '1';
-- else
-- enable <= '0';
end if;
if count(2 downto 0) = 7 then
-- = 3 for a 90 degree phase shift
enable_2x <= '1';
end if;
end if;
end process;
Hardware generated by any of these is tiny; too small to be worth
worrying about unless your target is a PAL16V8.
- Brian
Article: 135449On Thu, 2 Oct 2008 00:51:21 -0700 (PDT), "jack.harvard@googlemail.com" <jack.harvard@googlemail.com> wrote: >Hi, > >I implemented some single precision floating point units in FPGA (IEEE >754 fully compliant) to calculate some complex mathematical equations, >meanwhile, to debug the design modules, I've also got the C source >code implementing the equations, with all the variables defined in >single precision floating point. The Verilog code should have the same >precision as I would expect from the C code. However, I found there >are differences between the results generated from FPGA and C, the >precision is about 10**(-5), I suppose this could be caused by round >off errors. In Verilog, the round off is implemented as "round to the >nearest (if equal, round to even)", just wondering when it is done in >C, how the round off works, and how AMD/Intel processor does the round >off for single precision floating point? The Intel processor implements all the rounding modes specified in P754. How you actually select them is another matter. If you haven't already found Prof. Kahan's papers on P754, do so... Unfortunately C is a TERRIBLE language for this purpose (working in single precision floating point); the Visual C compilers especially so; they take liberties with precision, tending to assume you really want double precision and silently implementing it for you... ... then by forcing data into volatile "float" variables, you finally get your code to round as expected. Then you decide to abstract over it with a function, and.... C specifies that float arguments passed to functions are automagically coerced into doubles, so your code automagically breaks again... Personally I wouldn't worry about the Verilog unless you are ABSOLUTELY CERTAIN the C code is doing EXACTLY what you expect... it may turn out that the Verilog implementation is accumulating single precision float rounding errors exactly as it should, while the C code is assuming you didn't want what you asked for and giving you double precision instead. - Brian (no I don't much like C; why do you ask? :-)
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