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andrea.cortis@gmail.com wrote:
> However, I am not clear yet how do I get the results of a fpga
> computation back to my PC. Is there any cable I am missing (maybe
> serial)? How do I read and use this stream?
Pg 28:
On the board, LEDs 0, 1, 2, and 3 are lit,
indicating that the counter is running.
An fpga output is a high or low voltage on a device pin.
The counter pins are connected to LEDs for this demo.
Maybe your board has demos for other interfaces like rs232 or usb?
-- Mike Treseler
Article: 135551On Oct 7, 1:58=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > andrea.cor...@gmail.com wrote: > > However, I am not clear yet how do I get the results of a fpga > > computation back to my PC. Is there any cable I am missing (maybe > > serial)? How do I read and use this stream? > > Pg 28: > On the board, LEDs 0, 1, 2, and 3 are lit, > indicating that the counter is running. > > An fpga output is a high or low voltage on a device pin. > The counter pins are connected to LEDs for this demo. > > Maybe your board has demos for other interfaces like rs232 or usb? > > =A0 =A0 =A0 =A0 -- Mike Treseler Thanks Mike, When I run the tutorial the four leds are lit indeed: so far so good. A demo is exactly what I am looking for: a demonstration of how to make a simple program that takes two variables in input (say a and b) from the pc, calculates their sum c=3Da+b on the FPGA, and finally passes the variable c to the pc for further computations. The Spartan board I have does have a rs232 interface. Does anybody know of such a demo for my board? Many thanks again. AndreaArticle: 135552
On Oct 5, 6:48=A0pm, Peter Alfke <al...@sbcglobal.net> wrote: > On Oct 4, 9:09=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > Hi, > > I have no such experiences and ask for the question answers: > > > is it possible that two clock system blocks with one clock running > > half of other's of same clock source don't need asynchronous input/ > > output buffers in best circuit and logic design? > > > Especially, for example Intel and AMD CPU chip's, their cache I runs > > half frequency of CPU clock and gets almost 1/2 data rate as documents > > show. > > > What is their designs standout? I know Xilinx chip has divided clock > > outputs in addition to the main clock output and never have such an > > experiences to use the technique. > > > I need a guidance and direction instructions on the subject. A book or > > a paper reference is preferred. > > > Thank you. > > > Weng > > Weng, let me explain the basics: > You want to drive a system with two clocks, one of them has half the > frequency of the other. > The important question is now: what is the phase relationship between > the frequencies? Or, in simpler terms, assuming you use rising edge > triggering of the flipflops and registers: What is the timing delay > between rising edges of both clocks. > If you are sure that there is no delay (which I would never really > believe) then there is no problem. > If, however there is a short systematic delay, where the rising edge > of f2 is always a few ns later than the rising edge of f1, then any > data transfer from f1-based to f2-based might be unreliable, because > the f2 clock might pick up either the old data or the new data that > had just been changed by f1. That's would be a race condition, or a > hold-time violation. In the opposite direction, there is no problem, > provided you still have enough set-up time available, after you lost > some due to the phase difference. > This all assumes that the phase relationship is known and stable. If > it isn't, then you should treat the phase relationship as unknown and > use asynchronous FIFOs or some handshaking. > If your system is slow, you can deliberately offset the rising edges > by half a period of the faster clock, which would give you well- > defined timing relationship and clock margin (but you gave up half the > potential speed) > Peter Alfke, still there, lurking on weekends...- Hide quoted text - > > - Show quoted text - Hi Peter, Glad to receive your advice again. "This all assumes that the phase relationship is known and stable. If it isn't, then you should treat the phase relationship as unknown and use asynchronous FIFOs or some handshaking. " I fully agree with the above point. WengArticle: 135553
On Oct 5, 8:54=A0pm, Simon <goo...@gornall.net> wrote: > Hi Weng, > > When I was struggling with metastability, Philip Freidin was good > enough to point out where I was going wrong. I think his explanation > was very clear and helpful - it's athttp://tinyurl.com/473w92if you > want to have a look... > > Cheers, > =A0 =A0 =A0Simon (just giving back, and feeling good about it :) Hi Simon, I read the recommended comments and it is the standard asynchronous input/output handshaking. One does it and it must sacrify 4 clocks, 2 for output control signals, and 2 for input back control signals. Peter has a very nice paper describing the situations. But I don't think Intel 2GHz chip use the handshaking method, since every signals delay is at least 4 clocks, while their document is 2 clock for cache I part. So that I think Intel is using enable signal to control cache I part to get the full core and cache I as a synchronous system, not sacrifying any data delays. I have experiences designing a sucessful system with 3 clock rate in a Xilinx chip using global clock as only clock source and use asistant enable signals to control slow parts of design. For a high perfomance processor chip, 4 clock delays are unacceptable. Do you agree? Peter too? Thank you. WengArticle: 135554
One other problem I've had is that the tools don't seem to be able to handle buried tri-state control of busses. :-( NialArticle: 135555
Hi all I want to buy a FPGA experimantal board for getting into this area as a designer. Which boards are popular among EDA students ? Which board you can recomand from your experince when you were new at FPGA area ? Thanks ECArticle: 135556
Hi all What is the input to those FPGA boards ? How exactly the FPGA component on board is progarmmed ? For example if it is a XILINX component then the we would be coding and simulating on the XILINX EDA software and then synthsise to the same component on board and then JTAGing the synthesed model to the board ? Please clarify the real process from VHDL to the chip on bord programmed and running . Thanks in advance ECArticle: 135557
On Oct 8, 5:02=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > One other problem I've had is that the tools don't seem to be able to > handle buried tri-state control of busses. > > :-( > > Nial So it sounds like if you were transferring a design from Xilinx to Actel you'd have no problems in either case :) Xilinx timing constraints for I/O only work from the clock pin, not the internal net. That being said you could use the datasheet to find timing from an internal clock net to the pad if you use IOB registers. Newer Xilinx parts (after Virtex and Spartan 2) don't have internal tristate buses. Their synthesis emulates tristate buses with LUTs to ease migration of older designs, though. The last time I looked at Actel, my local FAE was so eager to grab sockets away from Xilinx he offered to port the design himself. Perhaps you can get direct assistance on this from your FAE? Good Luck, GaborArticle: 135558
I'm currently using Wireshark which in general is great software. However there appears to be a problem in quoting received packet checksums as good despite being seemingly good. Is there an alternative network sniffer which would give a clear indication of packets with incorrect checksums, preferably not using the WinPcap driver so to get a clear comparison. Has anyone else come across this problem with Wireshark with large packets?Article: 135559
On Oct 8, 8:03=A0am, "Bar Nash" <waves...@netvision.net.il> wrote: > Hi all > > I want to buy a FPGA experimantal =A0board for getting into this area as = a > designer. > > Which boards are popular among EDA students ? > > Which board you can recomand from your experince when you were new at FPG= A > area ? > > Thanks > EC Most posting here probably had no access to FPGA boards when they were new at FPGA. I myself started my digital design career using 7400 TTL logic and schematics drawn with pencil on vellum. You will find life much easier than we did, however. I suggest to look at the "evaluation" boards offered by Xilinx and Altera on their respective websites. The "most popular" at any time is probably the least expensive one that has the latest revision of silicon on it. As you might guess this is a moving target. Many boards are priced under $100 US, and you may even get discounts through a University program. Before you buy a board, however I would download and test-drive the tools. Xilinx and Altera both offer free "web" versions. Xilinx calls theirs ISE (we've all forgotten what it stands for) and Altera's is Quartus. Perhaps one of these will feel more logical and comfortable for you than the other. It will also only work with their own silicon (hence the $0 price tag) so you should then buy the board from the same source. Good luck on your new venture, GaborArticle: 135560
On Wed, 8 Oct 2008 14:03:11 +0200, "Bar Nash" <wavesoft@netvision.net.il> wrote: >Hi all > >I want to buy a FPGA experimantal board for getting into this area as a >designer. > >Which boards are popular among EDA students ? > >Which board you can recomand from your experince when you were new at FPGA >area ? Digilent http://www.digilentinc.com/ has several Xilinx FPGA boards that range from inexpensive (US$100) to kind of steep for a beginner (US$1500). Note that they also carry CPLD boards, so know what you're getting. Many of the "official" development boards available from Xilinx are produced by Digilent. http://www.knjn.com/ has some interesting dev boards based around Altera and Xilinx chips. I haven't used their boards but have gotten a couple of JTAG cables from them. Digelent's Nexsys-2 board (the inexpensive one) is more than adequate for learning your way around. -- Rich Webb Norfolk, VAArticle: 135561
Hi, I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So I put around 200 inverters in series and get the desired delay. So I did port map the BASIC cell "INV" according to the XST settings. But when i place and route I guess the optimizer removes all the intermediate buffers and I get very less delay when I do a post route simulation. How can I get rid of this problem? Thanks in advance. -PratapArticle: 135562
On 8 okt, 16:35, Pratap <pratap.i...@gmail.com> wrote: > Hi, > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So > I put around 200 inverters in series and get the desired delay. So I > did port map the BASIC cell "INV" according to the XST settings. > But when i place and route I guess the optimizer removes all the > intermediate buffers and I get very less delay when I do a post route > simulation. > How can I get rid of this problem? > Thanks in advance. > -Pratap If you have a clock signal of 100MHz, then just delay with one clock tick...Article: 135563
For a paper I'm working on which covers detecting malicious hardware in FPGAs, I would like to be able to parse through the HDL code (Leon3 processor) and locate groups of logic (at all levels of description) that behave like a mux. I have seen options in the synthesis tools that do this, so it should be possible (how effective?). Does anyone have any good references on algorithms that do this? Better yet, does anyone know of open source projects that do this? Currently I have a VHDL parser based on JavaCC snd a bunch of malicious circuits ready for uncovering. Thanks, ---Matthew HicksArticle: 135564
On Oct 8, 10:35=A0am, Pratap <pratap.i...@gmail.com> wrote: > Hi, > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So > I put around 200 inverters in series and get the desired delay. So I > did port map the BASIC cell "INV" according to the XST settings. > But when i place and route I guess the optimizer removes all the > intermediate buffers and I get very less delay when I do a post route > simulation. > How can I get rid of this problem? > Thanks in advance. > -Pratap First of all, 200 inverters may have about 10nS delay, but the routing to connect them will have many times this much. Second, any number of inverters greater than 1 will be optimised. To keep your logic, it's better to instantiate LUT components (assuming you don't decide to use a clock instead). Check out the libraries guide for available LUT's in your logic family. You can also use carry chain elements for finer delay resolution (because of dedicated routing). Regards, GaborArticle: 135565
<lbraeckm@gmail.com> wrote in message news:84d1168c-6ccc-4847-b36a-390fbd9dc425@v39g2000pro.googlegroups.com... > On 8 okt, 16:35, Pratap <pratap.i...@gmail.com> wrote: >> Hi, >> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So >> I put around 200 inverters in series and get the desired delay. >> -Pratap > > If you have a clock signal of 100MHz, then just delay with one clock > tick... I get the feeling that isn't what the OP wants. Your suggestion will give a delay of between the FF's clock to out and 10ns plus clock to out, for an asynchronous input. Cheers, Syms.Article: 135566
On Oct 8, 7:35=A0am, Pratap <pratap.i...@gmail.com> wrote: > Hi, > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So > I put around 200 inverters in series and get the desired delay. So I > did port map the BASIC cell "INV" according to the XST settings. > But when i place and route I guess the optimizer removes all the > intermediate buffers and I get very less delay when I do a post route > simulation. > How can I get rid of this problem? > Thanks in advance. > -Pratap Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns delay, but that delay is stable over temperature, voltage, and processing, because it is referenced to a 200 MHz clock (I call that servo-stabilized). Peter Alfke, XilinxArticle: 135567
Hi, I have been writing Verilog code for many years but the time has come for me to learn VHDL. Please recommend either a book or web reference or learning VHDL that would be good for someone that is experienced in FPGA architecture and Verilog. Thank You Tom tom_cip_11551@hotmail.comArticle: 135568
On Oct 8, 10:35=A0am, Pratap <pratap.i...@gmail.com> wrote: > Hi, > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So > I put around 200 inverters in series and get the desired delay. So I > did port map the BASIC cell "INV" according to the XST settings. > But when i place and route I guess the optimizer removes all the > intermediate buffers and I get very less delay when I do a post route > simulation. Logically a string of 2n inverters can be replaced with a wire. Logically a string of 2n+1 inverters can be replaced with a wire and a change to the contents of the LUT(s) that use that inverted signal. That's exactly what logic optimizers do. > How can I get rid of this problem? > Thanks in advance. 1. There really is no good and reliable method for generating fixed time delays in an FPGA without a free running clock. 2. 10 ns +/- ??. In other words, what sort of tolerance on the nominal 10 ns is acceptable? The tighter the tolerance the harder it becomes. 3. Most times when people think they need a delay line, they really don't because there are better and more robust ways to implement the design that do not require a delay line. You might want to describe what you're doing and why you think you need the delay line. That should generate responses on alternative design approaches. Kevin JenningsArticle: 135569
On Oct 8, 10:11=A0am, Matthew Hicks <mdhic...@uiuc.edu> wrote: > For a paper I'm working on which covers detecting malicious hardware in F= PGAs, > I would like to be able to parse through the HDL code (Leon3 processor) a= nd > locate groups of logic (at all levels of description) that behave like a > mux. =A0I have seen options in the synthesis tools that do this, so it sh= ould > be possible (how effective?). =A0Does anyone have any good references on = algorithms > that do this? =A0Better yet, does anyone know of open source projects tha= t > do this? =A0Currently I have a VHDL parser based on JavaCC snd a bunch of= malicious > circuits ready for uncovering. > > Thanks, > > ---Matthew Hicks Since this is an FPGA forum, almost nothing gets implemented as a mux. On the other hand, I learned a long time ago how to make any combinatorial boolean function from muxes. So, finding hardware that behaves like a mux could result in virtually all the combinatorial logic, or none of it. What specific aspects of the behavior of a mux are you interested in? AndyArticle: 135570
> So it sounds like if you were transferring a design from Xilinx > to Actel you'd have no problems in either case :) No, I don't think that's the case. > Xilinx timing constraints for I/O only work from the clock pin, not > the internal net. That being said you could use the datasheet > to find timing from an internal clock net to the pad if you use > IOB registers. I wouldn't mind that if only I could find that information out for the Actel device. I have an internal PLL that phase aligns the internal clock to the input clock so need to take this into account. It's just simple timing constraints I'm applying, it _should_ be simple. > Newer Xilinx parts (after Virtex and Spartan 2) don't have internal > tristate buses. Their synthesis emulates tristate buses with > LUTs to ease migration of older designs, though. I don't have any internal tri-states. I have four bi-directional data busses, the external tri-state for these was done in the VHDL module so I didn't have to repeat this at the top level of the design. The Actel tools don't look like they can handle this. > The last time I looked at Actel, my local FAE was so eager > to grab sockets away from Xilinx he offered to port the > design himself. Perhaps you can get direct assistance on > this from your FAE? He's trying but struggling. Nial.Article: 135571
Just speculating, but I'd bet large processors use derived clocks, with known phase relationships, to avoid the typical asynchronous clock boundary crossing logic wherever possible. Running large cache structures at twice the clock frequency needed is too power hungry. They might have been able to get away with it in the past, when caches were smaller and power consumption was less important, but not any longer. AndyArticle: 135572
> On Oct 8, 10:11 am, Matthew Hicks <mdhic...@uiuc.edu> wrote: > >> For a paper I'm working on which covers detecting malicious hardware >> in FPGAs, >> I would like to be able to parse through the HDL code (Leon3 >> processor) and >> locate groups of logic (at all levels of description) that behave >> like a >> mux. I have seen options in the synthesis tools that do this, so it >> should >> be possible (how effective?). Does anyone have any good references >> on algorithms >> that do this? Better yet, does anyone know of open source projects >> that >> do this? Currently I have a VHDL parser based on JavaCC snd a bunch >> of malicious >> circuits ready for uncovering. >> Thanks, >> >> ---Matthew Hicks >> > Since this is an FPGA forum, almost nothing gets implemented as a mux. > On the other hand, I learned a long time ago how to make any > combinatorial boolean function from muxes. So, finding hardware that > behaves like a mux could result in virtually all the combinatorial > logic, or none of it. What specific aspects of the behavior of a mux > are you interested in? > > Andy > I have to disagree with this statement at both the high and low levels. At the high level (HDL) the if, case, and conditional assignment statements all have the behavior of a mux. At the low level, I believe that there are mux components in the FPGA fabric, in every slice infact, at least in Xilinx's case. The behavior is the key for me. I am trying to find all selectors in a design, even if the user implements them at a structural level using primitive logic gates. I want to keep the search at the HDL level, so I'm not trying to look at the configuration of LUTs to see if they behave like muxes or even at the post-synthesis netlist. ---Matthew HicksArticle: 135573
Peter Alfke schrieb: [Ah, back again?] > On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote: >> Hi, >> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So >> I put around 200 inverters in series and get the desired delay. So I >> did port map the BASIC cell "INV" according to the XST settings. >> But when i place and route I guess the optimizer removes all the >> intermediate buffers and I get very less delay when I do a post route >> simulation. >> How can I get rid of this problem? >> Thanks in advance. >> -Pratap > > Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns > delay, but that delay is stable over temperature, voltage, and > processing, because it is referenced to a 200 MHz clock (I call that > servo-stabilized). > Peter Alfke, Xilinx Which jitter does this give? Thanks, ThomasArticle: 135574
On Oct 8, 10:42=A0am, Matthew Hicks <mdhic...@uiuc.edu> wrote: > > On Oct 8, 10:11 am, Matthew Hicks <mdhic...@uiuc.edu> wrote: > > >> For a paper I'm working on which covers detecting malicious hardware > >> in FPGAs, > >> I would like to be able to parse through the HDL code (Leon3 > >> processor) and > >> locate groups of logic (at all levels of description) that behave > >> like a > >> mux. =A0I have seen options in the synthesis tools that do this, so it > >> should > >> be possible (how effective?). =A0Does anyone have any good references > >> on algorithms > >> that do this? =A0Better yet, does anyone know of open source projects > >> that > >> do this? =A0Currently I have a VHDL parser based on JavaCC snd a bunch > >> of malicious > >> circuits ready for uncovering. > >> Thanks, > > >> ---Matthew Hicks > > > Since this is an FPGA forum, almost nothing gets implemented as a mux. > > On the other hand, I learned a long time ago how to make any > > combinatorial boolean function from muxes. So, finding hardware that > > behaves like a mux could result in virtually all the combinatorial > > logic, or none of it. What specific aspects of the behavior of a mux > > are you interested in? > > > Andy > > I have to disagree with this statement at both the high and low levels. = =A0 > At the high level (HDL) the if, case, and conditional assignment statemen= ts > all have the behavior of a mux. =A0At the low level, I believe that there= are > mux components in the FPGA fabric, in every slice infact, at least in Xil= inx's > case. > > The behavior is the key for me. =A0I am trying to find all selectors in a= design, > even if the user implements them at a structural level using primitive lo= gic > gates. =A0I want to keep the search at the HDL level, so I'm not trying t= o > look at the configuration of LUTs to see if they behave like muxes or eve= n > at the post-synthesis netlist. > > ---Matthew Hicks Every 4-input LUT is effectively a 16-to-1 mux with fixed data at its 16 inputs and a 4-bit variable at its address. Peter Alfke
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