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Messages from 136975

Article: 136975
Subject: Re: i2c interface
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Tue, 16 Dec 2008 12:42:54 -0800
Links: << >>  << T >>  << A >>
iam using i2c protocol for interfacing c3038 camera having
omniVision's CMOS image sensor ov6630....

i think it is clear from above code that iam using SCL as clock for
this process not the system clock......so i don't think that there is nested
clock

--------

You have a clock within a combinatorial statement. Very bad.

If the camera is the master and you are using it's clock then
you need to start each register transfer with this:
SDA_proc:process(SCL)
begin
if(SCL'event and SCL='0')then
 if(bit_cnt<8) then
    if(temp='0') then
      SDA<=data_register(7);
      temp<='1';  -- make temp a signal
      bit_cnt<=bit_cnt+1; -- and bit_cnt too
    else
      data_register<=data_register(6 downto 0) & '0';
      SDA<=data_register(7);
      bit_cnt<=bit_cnt+1;

There should be a delay from the clock edge to the data
change so you might have some problems there. I don't know.

If the camera is the slave and you are using FPGA clk then
you need to start each register transfer with this:
SDA_proc:process(clk)
begin
if(clk'event and clk='0')then
if(clk_en='1')then -- clk_en determines polling speed and delay
 SCL_1<=SCL;
 if(bit_cnt<8) then
  if(SCL='0' and SCL_1='1') then -- do once per SCL edge
    if(temp='0') then
      SDA<=data_register(7);
      temp<='1';
      bit_cnt<=bit_cnt+1;
    else
      data_register<=data_register(6 downto 0) & '0';
      SDA<=data_register(7);
      bit_cnt<=bit_cnt+1;

Then again if you are using the FPGA clock it would be better
to sync up all your signals with a four phase clock. I
have code for that if you are interested.

How are you detecting the STOP and START conditions?

Are you using a simulator?

You will also need to drive your SDA in open collector
configuration. What FPGA are you using?

Brad Smallridge
Ai Vision




Article: 136976
Subject: Re: Problem with infering BRAM in XST
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Tue, 16 Dec 2008 13:06:47 -0800
Links: << >>  << T >>  << A >>
Xilinx is promoting the "read address" register
method now to infer BRAM's so there's got to
be a read register to latch the address. When you
add a register outside the BRAM, to speed things
up as you say, perhaps the synthesizer doesn't
know what address register it should consider the
BRAM read address register or, worse, you don't
have a BRAM address register latch at all within
the BRAM.

You also have to have, I believe, shared variables
in order to get two write ports. Check me on this.

Brad Smallridge
AiVision



Article: 136977
Subject: Microblaze without external ram
From: Jan <1@2.3>
Date: Tue, 16 Dec 2008 23:21:25 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm trying to plan a new product. I started out with a design that 
involved a FPGA and an external Micro controller. However, I might want 
to try to embed the Micro as a MicroBlaze.

Is it possible to implement the MicroBlaze using purely internal BRAM?

Does there exists an USB core with Chapter 9 source in the open source 
community?

Thank you in advance!

Regards
    Jan

Article: 136978
Subject: Re: i2c interface
From: KJ <kkjennings@sbcglobal.net>
Date: Tue, 16 Dec 2008 19:12:41 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 15, 11:29=A0am, GrIsH <girish_thesi...@hotmail.com> wrote:
> On Dec 15, 2:57=A0am, Gabor <ga...@alacron.com> wrote:
> > If this is a master I2c interface then you should be generating
> > SCL yourself. =A0If that is the case why not run everything on
> > your system clock.

>
> yes...i have master i2c interface.and iam using i2c protocol for
> interfacing camera c3038......and it can transfer the data at the rate
> of 400kbit/sec maximum. so i could not use fast system clock as SCL..
>

You missed the point.  Since you're the I2C master and generating SCL
yourself, you use the system clock to generate your logic you would
not *use* SCL as a clock itself.  Here is an example to illustrate,
I'm assuming here that the system clock runs at 10x the SCL clock rate
for illustration since you mentioned that in another part of the
thread.  This is just a snippet, not the entire code.

constant Sys_Clocks_Per_Scl_Clock: natural :=3D 10;
signal scl_counter: natural range 0 to (Sys_Clocks_Per_Scl_Clock: -
1);
signal scl_rising_edge: std_ulogic;
signal scl_falling_edge: std_ulogic;
...
process(clock)
begin
  if rising_edge(clock) then
    -- Counter for generating scl
    if (reset =3D '1')
    or (scl_counter =3D (Sys_Clocks_Per_Scl_Clock - 1)) then
      scl_counter <=3D 0;
    else
      scl_counter <=3D scl_counter + 1;
    end if;
    -- Now generate scl itself
    if (reset =3D '1')
    or (scl_falling_edge =3D '1') then
      scl <=3D '0';
    elsif (scl_rising_edge =3D '1') then
      scl <=3D '1';
    end if;
    -- Other logic that needs to happen on 'edges' of scl
    if (scl_rising_edge =3D '1') then
      -- Now do whatever it is you'd like to do on "rising
      -- edges" of scl
    end if;
    if (scl_falling_edge =3D '1') then
      -- Now do whatever it is you'd like to do on "falling
      -- edges" of scl.  For example, the code that you
      -- had in your original post
      if(temp=3D'0') then
          SDA<=3Ddata_register(7);
           temp:=3D'1';
           bit_cnt:=3Dbit_cnt+1;
      else
           data_register<=3Ddata_register(6 downto 0) & '0';
           SDA<=3Ddata_register(7);
           bit_cnt:=3Dbit_cnt+1;
       end if;
    end if;
  end if;
end process;

-- Personally, I like using concurrent assignment to signals here
since
-- then they can be 'waved' in simulation more readily.
Equivalently,
-- these could be defined as variables and moved up into the process
-- above.
scl_rising_edge <=3D '1' when (scl_counter =3D (Sys_Clocks_Per_Scl_Clock -
1)) else '0';
scl_falling_edge <=3D '1' when (scl_counter =3D (Sys_Clocks_Per_Scl_Clock/
2 - 1)) else '0';

Kevin Jennings

Article: 136979
Subject: Re: i2c interface
From: KJ <kkjennings@sbcglobal.net>
Date: Tue, 16 Dec 2008 19:17:43 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 15, 11:54=A0am, GrIsH <girish_thesi...@hotmail.com> wrote:
> -------------------------------------------------------------------
> i think it is clear from above code that iam using SCL as clock for
> this process not the system clock......so i don't think that there is
> nested
> clock ...................................................................=
........=AD...

It may not be nested, but you are misusing scl as a clock in your code
since you will be creating a gated clock where the gating term is
defined by "when data_tx and (bit_cnt<8)".

Gated clocks in FPGAs are a big mistake because the timing analysis
(if you perform it) inevitably fails.  If you don't do the analysis
then you stare at your board and wonder why the design doesn't work
for more than 2 minutes (or sometimes doesn't work in those first 2
minutes).

KJ

Article: 136980
Subject: Gigabit Ethernet PHY without NDA?
From: Matt Ettus <boyscout@gmail.com>
Date: Tue, 16 Dec 2008 22:54:42 -0800 (PST)
Links: << >>  << T >>  << A >>

I've been using a National Semi DP83865 Gigabit Ethernet PHY chip for
a while now.  It has 4 problems:

- Burns 1.25 Watts (and gets hot)
- Needs 2 voltages, 1.8 and 2.5 Volts, and 1.8 is used nowhere else in
my system
- Can't maintain a connection on 100 meters of Cat-5
- It is a very large chip

So I decided to look around for a replacement.  I have found
candidates from Marvell, Vitesse, and Broadcom.  All claim to use
about half the power, are much smaller, and don't need the 1.8V
supply.

The problem is that all of them require an NDA just to see the
datasheet.  Because I intend to publish the design (this is open
source hardware), I am not in a position where I can sign an NDA.  In
fact, there are FPGA development boards out there with published
schematics that have a page marked "this page redacted due to an NDA
on the Marvell 88E1111".  This seems nuts to me.  I mean, what could
possibly be NDA-worthy in the datasheet for a 4 year old part that
implements a technology (GbE) which is nearly a decade old?

Does anyone have any suggestions as to non-NDA encumbered GbE PHY
chips?  All I need is GMII or RGMII.

Thanks,
Matt

Article: 136981
Subject: Re: Microblaze without external ram
From: backhus <nix@nirgends.xyz>
Date: Wed, 17 Dec 2008 08:16:46 +0100
Links: << >>  << T >>  << A >>
Jan schrieb:
> Hi,
> 
> I'm trying to plan a new product. I started out with a design that 
> involved a FPGA and an external Micro controller. However, I might want 
> to try to embed the Micro as a MicroBlaze.
> 
> Is it possible to implement the MicroBlaze using purely internal BRAM?
> 
> Does there exists an USB core with Chapter 9 source in the open source 
> community?
> 
> Thank you in advance!
> 
> Regards
>    Jan
Hi Jan,
of course you can, but your code and data size is very limited then.
Some of our students did it with the opencores aeMB some years ago.

Since the BRAMs are very fast you may implement the MB core without 
cache to save some BRAMS and reduce the size of the core.

Instead of implementing a USB core inside a FPGA you may think about 
using a Cypress FX2 chip. This is even USB 2 compatible.
(Take a look at the EFM01 from http://www.cesys.de/)

For the software part you may find information and reference code in the 
linux sources (linux/usb_ch9.h etc.).

Have a nice synthesis
   Eilert

Article: 136982
Subject: Re: clock reducing leads what
From: Thomas Stanka <usenet_nospam_valid@stanka-web.de>
Date: Tue, 16 Dec 2008 23:48:16 -0800 (PST)
Links: << >>  << T >>  << A >>
On 15 Dez., 08:09, sreenivas.jyo...@gmail.com wrote:
> can anyone give the techniques on "Impact on output by Reducing Clock
> Frequency"

Yes, you or your employee (with skills in digital design)

> If the logic contains internal register than what kind of
> things to take care.
>
> Let say i have a clok called fpga_clk = 50 MHz, with 50% duty cycle
> and by reducing it to 10 or 5 MHz with fixed duty cycle.

You need to know your design well then deceide the impact. There is no
chance to answer this without detail knowlegde of your design.
eg. if you have a counter that measures a fixed time, this counter
will be wrong when reducing clock frequency. If you need to have an
output toggeling at 50 MHz you will be in trouble when reducing the
clock to 5 MHz.

bye Thomas


Article: 136983
Subject: Re: SystemVerilog OOP and OVM Summary
From: "vlsichipdesigner@gmail.com" <vlsichipdesigner@gmail.com>
Date: Wed, 17 Dec 2008 00:55:14 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 6, 3:05=A0am, Amal <akhailt...@gmail.com> wrote:
> Here is a presentation I prepared that summarizes the some of the
> SystemVerilog OOP and OVM v2.0 features.
>
> =A0http://www.slideshare.net/akhailtash/ovm-features-summary-presentation=
/
>
> Enjoy,
> -- Amal

hi Amal,
Wonderful presentation,
I am running a technical portal http://www.vlsichipdesign.com
here in i share my 10+years of experiences, please go through the
website and let me know your feedback.

Can i use your presentation, in my site i will give your credit to
you , please reply

my prayers,

Article: 136984
Subject: Re: Gigabit Ethernet PHY without NDA?
From: Allan Herriman <allanherriman@hotmail.com>
Date: 17 Dec 2008 10:16:21 GMT
Links: << >>  << T >>  << A >>
Matt Ettus <boyscout@gmail.com> wrote in news:3dbf05f8-b8cb-4036-800e-
940af73ce1e8@n33g2000pri.googlegroups.com:

> 
> I've been using a National Semi DP83865 Gigabit Ethernet PHY chip for
> a while now.  It has 4 problems:
> 
> - Burns 1.25 Watts (and gets hot)
> - Needs 2 voltages, 1.8 and 2.5 Volts, and 1.8 is used nowhere else in
> my system
> - Can't maintain a connection on 100 meters of Cat-5
> - It is a very large chip
> 
> So I decided to look around for a replacement.  I have found
> candidates from Marvell, Vitesse, and Broadcom.  All claim to use
> about half the power, are much smaller, and don't need the 1.8V
> supply.
> 
> The problem is that all of them require an NDA just to see the
> datasheet.  Because I intend to publish the design (this is open
> source hardware), I am not in a position where I can sign an NDA.  In
> fact, there are FPGA development boards out there with published
> schematics that have a page marked "this page redacted due to an NDA
> on the Marvell 88E1111".  This seems nuts to me.  I mean, what could
> possibly be NDA-worthy in the datasheet for a 4 year old part that
> implements a technology (GbE) which is nearly a decade old?
> 
> Does anyone have any suggestions as to non-NDA encumbered GbE PHY
> chips?  All I need is GMII or RGMII.


The last time I looked at PHYs (a few years ago), the good ones required 
NDAs for the datasheets, and the ones that didn't have NDAs weren't worth 
using.

I don't see how this clashes with open source hardware though.  You need 
to document the design of the interface to the PHY but this isn't the 
same thing as violating the NDA for the PHY datasheet.

The schematic merely shows the pinout.  The pinout isn't covered by the 
NDA, as that information is already published in schematics that you can 
download.  
For example, I found this schematic containing an 88E1111 in less than a 
minute of searching:  
http://www.xilinx.com/support/documentation/boards_and_kits/ml50x_schemat
ics.pdf
Most NDAs contain a clause that invalidates them if the information 
becomes public through some other means.


An NDA might be more of a problem for the software; device driver source  
typically contains information about many of the PHY internal registers.


Disclaimer: I am not a lawyer, and you should read the terms of the NDA 
very closely.

Regards,
Allan

Article: 136985
Subject: LEON3 processor
From: =?windows-1252?Q?GaLaKtIkUs=99?= <taileb.mehdi@gmail.com>
Date: Wed, 17 Dec 2008 04:24:31 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi everybody,
I googled for energy consumprtion of LEON3 processor but didn't find
anything.
I need statistics of statis/dynamic power consumption for FPGA
(Xilinx, Altera) and ASIC.

Thanks in advance

Article: 136986
Subject: Re: Gigabit Ethernet PHY without NDA?
From: John Adair <g1@enterpoint.co.uk>
Date: Wed, 17 Dec 2008 04:39:41 -0800 (PST)
Links: << >>  << T >>  << A >>
We have had the same problem and partially why we have not as yet got
a phy module at gigabit available. We didn't think it was worth
incorporating in development boards, or modules, if our customers
couldn't get the basic information. The other problem with these
companies is getting smallish numbers of chips is generally expensive
and difficult. I can only hope these companies stop being so snobbish
as they get rapid volume turnoff in the current recession in their
favoured consumer markets.

John Adair
Enterpoint Ltd.


On 17 Dec, 06:54, Matt Ettus <boysc...@gmail.com> wrote:
> I've been using a National Semi DP83865 Gigabit Ethernet PHY chip for
> a while now. =A0It has 4 problems:
>
> - Burns 1.25 Watts (and gets hot)
> - Needs 2 voltages, 1.8 and 2.5 Volts, and 1.8 is used nowhere else in
> my system
> - Can't maintain a connection on 100 meters of Cat-5
> - It is a very large chip
>
> So I decided to look around for a replacement. =A0I have found
> candidates from Marvell, Vitesse, and Broadcom. =A0All claim to use
> about half the power, are much smaller, and don't need the 1.8V
> supply.
>
> The problem is that all of them require an NDA just to see the
> datasheet. =A0Because I intend to publish the design (this is open
> source hardware), I am not in a position where I can sign an NDA. =A0In
> fact, there are FPGA development boards out there with published
> schematics that have a page marked "this page redacted due to an NDA
> on the Marvell 88E1111". =A0This seems nuts to me. =A0I mean, what could
> possibly be NDA-worthy in the datasheet for a 4 year old part that
> implements a technology (GbE) which is nearly a decade old?
>
> Does anyone have any suggestions as to non-NDA encumbered GbE PHY
> chips? =A0All I need is GMII or RGMII.
>
> Thanks,
> Matt


Article: 136987
Subject: xilinx: FSL - FSL_Has_Data vs FSL_S_Exists
From: "danmarco" <danmarco@gmail.com>
Date: Wed, 17 Dec 2008 07:21:50 -0600
Links: << >>  << T >>  << A >>
Hi, 

I'm trying to understands the FSL signals:

both FSL_Has_Data and FSL_S_Exists seem to indicate that there is
currently data in the FIFO - why then are two signals needed? 

thanks.



Article: 136988
Subject: Re: Microblaze without external ram
From: "jeffg" <jeffrey_a_graham@yahoo.com>
Date: Wed, 17 Dec 2008 07:22:02 -0600
Links: << >>  << T >>  << A >>
>Hi,
>
>I'm trying to plan a new product. I started out with a design that 
>involved a FPGA and an external Micro controller. However, I might want 
>to try to embed the Micro as a MicroBlaze.
>
>Is it possible to implement the MicroBlaze using purely internal BRAM?
Yes it is simple to implement a microblaze with internal BRAM.

>
>Does there exists an USB core with Chapter 9 source in the open source 
>community?
>
Have you considered using one of the many USB2.0 interface chips they are
really cheap and kinda handy for reprogramming the FPGA. Lots of the cheap
demo boards operate this way.

>Thank you in advance!
>
>Regards
>    Jan
>





Article: 136989
Subject: Re: BUFGMUX placement
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 17 Dec 2008 13:59:33 -0000
Links: << >>  << T >>  << A >>
Raph,

Yes it is. You're using too many clocks. If you insist on using all these
clocks, you are on the way to destruction. (BTW, I spent 2 seconds
googling - how to do fpga clocking - and found an apparently decent article
explaining why this is true. You did google for an answer, right? Maybe not,
here's the link...
http://www.design-reuse.com/articles/4854/fpga-clock-schemes.html)

Whatever, I suggest you RTM.
http://www.xilinx.com/support/documentation/user_guides/ug331.pdf
Try the section "Quadrant Clock Routing", like you were told to do in the
original error message.
Finally, if you post again, tell us specifically for what you're using each
of all these clocks, and ask questions about what you don't understand in
the user guide linked above.
Good luck, Symon.



raph wrote:
> thanks for your replies but it is not that...
> if you are interested see :
>
> http://tech.groups.yahoo.com/group/leon_sparc/message/14447
>
> On Dec 15, 3:55 pm, Gael Paul <gael.p...@gmail.com> wrote:
>> Hi Raph,
>>
>> I suggest checking your Leon3 configuration. It is likely that you
>> have a ASIC configuration with clock-gating. When targeting an FPGA,
>> I believe you should get a single clock per core.
>>
>> - gael






Article: 136990
Subject: Re: LEON3 processor
From: Jon Beniston <jon@beniston.com>
Date: Wed, 17 Dec 2008 08:47:00 -0800 (PST)
Links: << >>  << T >>  << A >>
On 17 Dec, 12:24, GaLaKtIkUs=99 <taileb.me...@gmail.com> wrote:
> Hi everybody,
> I googled for energy consumprtion of LEON3 processor but didn't find
> anything.
> I need statistics of statis/dynamic power consumption for FPGA
> (Xilinx, Altera) and ASIC.

Which FPGA and which ASIC? It makes a big difference. Also, what the
processor is doing makes a big difference.

Jon

Article: 136991
Subject: Re: Gigabit Ethernet PHY without NDA?
From: nico@puntnl.niks (Nico Coesel)
Date: Wed, 17 Dec 2008 17:36:16 GMT
Links: << >>  << T >>  << A >>
Matt Ettus <boyscout@gmail.com> wrote:

>
>I've been using a National Semi DP83865 Gigabit Ethernet PHY chip for
>a while now.  It has 4 problems:
>
>- Burns 1.25 Watts (and gets hot)
>- Needs 2 voltages, 1.8 and 2.5 Volts, and 1.8 is used nowhere else in
>my system
>- Can't maintain a connection on 100 meters of Cat-5
>- It is a very large chip
>
>So I decided to look around for a replacement.  I have found
>candidates from Marvell, Vitesse, and Broadcom.  All claim to use
>about half the power, are much smaller, and don't need the 1.8V
>supply.

Perhaps Micrel has a nice & cheap phy.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

Article: 136992
Subject: V4FX PPC405: DCR bus and synchronization
From: jetmarc@hotmail.com
Date: Wed, 17 Dec 2008 11:14:34 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello,

Trying to optimize a driver for a DCR peripherial on a V4FX PPC405
system, I wonder if I need to use the (slow) eieio synchronization
instruction all over.

The peripherial uses one single DCR registers to read a stream of data
from.  The PPC code has a tight loop with

   mtdcr() to get a word
   store the word to RAM
   eieio

The eieio is there because I thought that otherwise the DCR accesses
could become reordered.  I found a note in the datasheets, saying that
DCR must be handled like other memory.  However, there was no in-depth
explanation about DCR synchronization.  My case is a special one
because the whole stream of words is read from the same DCR register
and it's difficult to imagine how the PPC could benefit from
reordering such accesses.

I'd like to eliminate the eieio because it has unnecessary effects on
the store-to-RAM operation.  I tested the driver without eieio and it
works just fine (and is faster).  However I can't commit this
modification without a reference to a datasheet or appnote saying that
I can really do without the eieio.

Can you point me to a place to look for this?  Or if you think that I
must not eliminate the eieio, then please tell me so.

Best regards,
Marc

Article: 136993
Subject: # ** Error: netgen/map/stepper_drive_map.vhd(6692): Physical unit
From: denish <dinesh.twanabasu@gmail.com>
Date: Wed, 17 Dec 2008 11:23:57 -0800 (PST)
Links: << >>  << T >>  << A >>
simulation of the code in ise resulted following error in modelsim
# ** Error: netgen/map/stepper_drive_map.vhd(6692): Physical unit
hidden by declaration of 'ps' at line 651
           I could not figure out what the  error actually means.

Article: 136994
Subject: Re: # ** Error: netgen/map/stepper_drive_map.vhd(6692): Physical unit hidden by declaration of 'ps' at line 651
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Wed, 17 Dec 2008 11:33:16 -0800
Links: << >>  << T >>  << A >>
Probably a syntax error. Don't use ps as an identifier.

> simulation of the code in ise resulted following error in modelsim
> # ** Error: netgen/map/stepper_drive_map.vhd(6692): Physical unit
> hidden by declaration of 'ps' at line 651
>           I could not figure out what the  error actually means. 



Article: 136995
Subject: Advanced google group search doesn't work?
From: "MM" <mbmsv@yahoo.com>
Date: Wed, 17 Dec 2008 16:05:23 -0500
Links: << >>  << T >>  << A >>
Hi all,

I've been trying to find posts related to ISOCM in Virtex-4 and it seems as 
the google advanced group search got broken... Anyone else noticed this?


/Mikhail 



Article: 136996
Subject: Re: LEON3 processor
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 18 Dec 2008 01:01:05 -0000
Links: << >>  << T >>  << A >>
Try harder. These searches might help:-

how to google

calculate power consumption site:xilinx.com
calculate power consumption site:altera.com

Good luck, Syms.

GaLaKtIkUsT wrote:
> Hi everybody,
> I googled for energy consumprtion of LEON3 processor but didn't find
> anything.
> I need statistics of statis/dynamic power consumption for FPGA
> (Xilinx, Altera) and ASIC.
>
> Thanks in advance 



Article: 136997
Subject: Re: Advanced google group search doesn't work?
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 18 Dec 2008 01:05:14 -0000
Links: << >>  << T >>  << A >>
http://groups.google.com/groups/search?q=ISOCM

MM wrote:
> Hi all,
>
> I've been trying to find posts related to ISOCM in Virtex-4 and it
> seems as the google advanced group search got broken... Anyone else
> noticed this?
>
> /Mikhail 



Article: 136998
Subject: Re: Problem with infering BRAM in XST
From: Sudhir.Singh@email.com
Date: Wed, 17 Dec 2008 19:27:17 -0800 (PST)
Links: << >>  << T >>  << A >>
Thanks guys for your replies.
I have been using a component which has inferable BRAM VHDL code from
Xilinx docs. I use this component in my design whenever I need a BRAM.
Brad, yeah you do need a shared variable to get the two write ports.

Cheers
Sudhir


On Dec 17, 10:06=A0am, "Brad Smallridge" <bradsmallri...@dslextreme.com>
wrote:
> Xilinx is promoting the "read address" register
> method now to infer BRAM's so there's got to
> be a read register to latch the address. When you
> add a register outside the BRAM, to speed things
> up as you say, perhaps the synthesizer doesn't
> know what address register it should consider the
> BRAM read address register or, worse, you don't
> have a BRAM address register latch at all within
> the BRAM.
>
> You also have to have, I believe, shared variables
> in order to get two write ports. Check me on this.
>
> Brad Smallridge
> AiVision


Article: 136999
Subject: Re: Gigabit Ethernet PHY without NDA?
From: "H. Peter Anvin" <hpa@zytor.com>
Date: Wed, 17 Dec 2008 21:00:30 -0800
Links: << >>  << T >>  << A >>
Nico Coesel wrote:
> Perhaps Micrel has a nice & cheap phy.

Micrel has nothing gigabit on their website.

	-hpa



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