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Messages from 13750

Article: 13750
Subject: PLL in FPGAs?
From: Brett George <b.george@clarityeq.com>
Date: Tue, 22 Dec 1998 17:56:15 +1000
Links: << >>  << T >>  << A >>
Hi all,

Has anyone tried implementing a PLL in an FPGA (eg. ALTERA), we are
thinking of using it to reduce clock jitter from an externally generated
clock source.
Do they come in Macrofunctions?
Whal would be the accuracy of such a PLL?
eg. If the incoming clock had a frequency of 48kHz with jitter of 20 ns,
would
the implemented PLL be able to reduce the jitter to 1ns?

The delay throught the FPGA is not a problem, just the jitter.

Thanks in advance,
Brett.

Article: 13751
Subject: Re: Starting with FPGAs
From: Brett George <b.george@clarityeq.com>
Date: Tue, 22 Dec 1998 18:01:02 +1000
Links: << >>  << T >>  << A >>
Eldho,

*The  best link that I have seen for state diagrams is:

http://www.cs.berkeley.edu/~randy/CLD/CLD.html

*Think about the FPGA you need to use, eg. Xilinx, Altera, Atmel, Lattice etc.
The software is usually very helpful in writing state-diagrams.
Altera has a free copy of the software, which is very easy to use. You can
write (synchronous) state diagrams in AHDL but the VHDL compiler will
cost you.


Brett.


ekuria01@kepler.poly.edu wrote:

> Hello,  I developed an embedded application and would like to move it to an
> FPGA. Basically, I need some pointers to refrence material on how to do this.
>
> Some of the topics I need to learn about:
>
>   * Converting a flowchart to a state diagram.
>     (I can write the code up in VHDL once i have done the state diagram.)
>
>   * moving the code to an FPGA implementation.
>
> Please let me know of any book concerning these cocepts and procedures.
>
> Thank you in advance.
>
> Eldho kuriakose
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own



Article: 13752
Subject: Re: Magazine IEEE for FPGA ???
From: Brett George <b.george@clarityeq.com>
Date: Tue, 22 Dec 1998 18:04:04 +1000
Links: << >>  << T >>  << A >>
There was a good (& lengthy) article in a recent edition of SPECTRUM
(ieee for signal processing)

BG.

renzo.arce@st.com wrote:

> Hi,
> some body know which IEEE magazine contains articles about FPGA
> design and development.
>
> Thank you !
>
> Renzo Arce



Article: 13753
Subject: Re: Fast *Industrial* 22V10?
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 22 Dec 1998 12:03:17 +0100
Links: << >>  << T >>  << A >>
z80@ds2.com (Peter) writes:

> Not zero power, more like 30mA. This is 10x more than the entire draw
> of some of my products :)

What's the programming current of a ZPLD from Siemens? Negligeable?

Homann
-- 
   Magnus Homann  Email: d0asta@dtek.chalmers.se
                  URL  : http://www.dtek.chalmers.se/DCIG/d0asta.html
  The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html

Article: 13754
Subject: exporting synario schematics?
From: nick toop <nick@cortexco.demon.co.uk>
Date: Tue, 22 Dec 1998 12:04:11 +0000
Links: << >>  << T >>  << A >>
I have a Lattice/Synario Version 5.0 design kit.
I would like to export the schematics for documentation.
A screen snapshot does not get enough detail.

Is there a product which does this?
Do I have to buy the full price Synario system?

Synario does not allow print to file but can one install a "file
printer" on NT4.0?

Thanks,
-- 
nick toop

Article: 13755
Subject: SIS & CAD tools
From: Laurent Lemarchand <lemarch@univ-brest.fr>
Date: Tue, 22 Dec 1998 13:42:04 +0100
Links: << >>  << T >>  << A >>
For a talk, I'm looking for informations about the use
of the SIS/MIS II software routines from UCB
in industrial and academic CAD tools synthesis flow, 
particularly for the technology mapping of
circuits onto reprogrammable componants such as 
LUT-based FPGA.

Thanks in advance for your help.

L. Lemarchand.


-- 

------------
Laurent Lemarchand                  PhD student
Universite de Bretagne Occidentale  E-mail: lemarch@univ-brest.fr
UFR Sciences et Techniques          Tel: (33-2) 98 01 62 17
Departement d'Informatique          Fax: (33-2) 98 01 62 15
BP 809                                   (33-2) 98 01 69 80 
29285 Brest Cedex
------------

Article: 13756
Subject: Re: exporting synario schematics?
From: Lasse Langwadt Christensen <fuz@kom.auc.dk>
Date: Tue, 22 Dec 1998 15:53:19 GMT
Links: << >>  << T >>  << A >>
nick toop wrote:
> 
> I have a Lattice/Synario Version 5.0 design kit.
> I would like to export the schematics for documentation.
> A screen snapshot does not get enough detail.
> 
> Is there a product which does this?
> Do I have to buy the full price Synario system?
> 
> Synario does not allow print to file but can one install a "file
> printer" on NT4.0?
> 
> Thanks,
> --
> nick toop

all printers can be set to "file", just install any printer 
and choose "file" instead of lpt1  
some postscript printers will even have the choice of printing .eps

-- Lasse
----------------------------------------------------------
Lasse Langwadt Christensen, M.Sc. EE (to be in 1999)
Aalborg University, Department of communication technology 
Applied Signal Processing and Implementation (ASPI)      
http://www.kom.auc.dk/~fuz , ICQ# 13068090

Article: 13757
Subject: Xilinx - Viewlogic Virtex Support
From: Hitesh Patel <hiteshp@xilinx.com>
Date: Tue, 22 Dec 1998 08:58:32 -0800
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------3D60A427F6AF135341733864
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit



--------------3D60A427F6AF135341733864
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Over the past several months, there have been multiple requests
for Viewsim functional simulation support targeting Virtex. Xilinx
recognises this need since schematic based Viewlogic users
verify their design functionality using Viewsim. As a result,
Xilinx together with the help of Viewlogic and Philip Freidin will 
support functional simulation for Virtex. The planned schedule for 
support is as follows:

Q1 '99          - Support for gate level functional simulation library
                  (will be available via ftp)
Q2 '99 (A2.1)   - Functional Simulation support for block RAM and 
                  other specialty memory functions.
                   
This flow will support functional simulation for Virtex using
Viewsim and static timing analysis using TRCE for post-route
delay analysis.

Regards,
Hitesh Patel
Product Marketing Manager
EDA Partner Solutions
--------------3D60A427F6AF135341733864--

Article: 13758
Subject: Re: Atmel's PLD
From: Valentin Serb <vali@thcomm.dnt.ro>
Date: Tue, 22 Dec 1998 19:10:33 +0200
Links: << >>  << T >>  << A >>
sam wrote:
> 
> Does anyone have trouble when use Atmel's PLD ?
> I will never use Atmel's PLD . It's too bad .

I agree partially with sam's opinion. I used ATV2500 in a few designs,
and had troubles. Starting with the strange behavior of the part when
unused I/O's weren't connected to known levels (I haven't found any
refferals in the datasheet regarding this issue, although it is good
design practice). Then I found many defective parts in the equipment
which used them (it was a telecom equipment). I supposed there was some
sort of latch-up, since I could not reproduct the conditions. And the
fact that being OTP, one can not test the idea before the actual
implementation. Anyway, since the ATV2500 is no longer supported, I hope
the new parts coming on will be better.

Since these are my own opinions, any others would be appreciated

Valentin


Article: 13759
Subject: Re: MP3 and FPGA's
From: Tim Tyler <tt@cryogen.com>
Date: Tue, 22 Dec 1998 17:54:04 GMT
Links: << >>  << T >>  << A >>
Steve <reply.through.newsgroup@paranoid.com> wrote:

: Would it be practical to implement an MP3 decoder in an FPGA?

I don't know.  An FPGA will only be able to go as far as the serial
digital data, of course - you'd need to use a digital to analogue
convertor designed for audio applications, or an external DAC.

I don't know what MP3 is beyond a discrete cosine transform - but my
feeling is that existing FPGAs would be able to manage this task at the
required speed.

I'm curious to hear what the proposed application of this is, BTW.
-- 
__________
 |im |yler  The Mandala Centre  http://www.mandala.co.uk/  tt@cryogen.com

Become a computer programmer and never see the world again.

Article: 13760
Subject: Re: Atmel's PLD
From: rolavine@aol.com (Rolavine)
Date: 22 Dec 1998 18:58:27 GMT
Links: << >>  << T >>  << A >>
>Subject: Re: Atmel's PLD
>From: Valentin Serb

>I used ATV2500 in a few designs,
>and had troubles. Starting with the strange behavior of the part when
>unused I/O's weren't connected to known levels (I haven't found any
>refferals in the datasheet regarding this issue, although it is good
>design practice). 

Since pull ups, or downs are not built in, I alsways treated unused inputs as
if they were cmos types. I made unused I/O s outputs and assigned them to
static levels. I had trouble with this early on, and learned quickly.

Then I found many defective parts in the equipment
>which used them (it was a telecom equipment). I supposed there was some
>sort of latch-up, since I could not reproduct the conditions. And the
>fact that being OTP, one can not test the idea before the actual
>implementation. 
>
ATV2500s were available in ceramic UV errasable packages. If the code was not
protected you can read out the configuration data on a programmer and compare
it against what it is supposed to be. Also, If this is from a comercial
product, the engineer who did the PLD should have provided a set of test
vectors for the testing of the programmed device after it is programmed. So the
device can be functinally tested (not at speed but..) on the programmer.

Hope this helps, but it seems like your blaming the PLD when it maybe your
process. A further question can be made of the tools used for creating the
configuration data for the device but that is another story.

Rocky Lavine
Rocky Test
balanced engineering

Article: 13761
Subject: Re: Xilinx/CAST 16550 core
From: z80@ds2.com (Peter)
Date: Tue, 22 Dec 1998 20:33:22 GMT
Links: << >>  << T >>  << A >>

If you can find a competent logic designer who is not too busy, he can
probably do a 16550 equivalent (*especially* if you don't need all its
features) for you for considerably under $15k. 

And then you get all the design details and documentation. You could
even resell it for $1000 :)

>Does anyone but CAST supply a 16550 core?  They've just quoted $15K for
>the VHDL source or $7500 for a Xilinx netlist.  In either case, that's
>too much for this application.  Can it be found elsewhere?


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.

Article: 13762
Subject: Xilinx FPGA Express cmd line
From: "Steve" <reply.through.newsgroup@paranoid.com>
Date: Tue, 22 Dec 1998 20:38:26 GMT
Links: << >>  << T >>  << A >>
Does the Xilinx version support command line?  Foundation 1.5
seems to be able to bypass the Synopsys GUI and I think fe.exe
is the command line version.  Does anyone know how to use it?

Why?  Because I'm switching to a makefile and want to include
the synthesis in the make if possible.


Steve


Article: 13763
Subject: Re: Xilinx - Viewlogic Virtex Support
From: Ray Andraka <randraka@ids.net>
Date: Tue, 22 Dec 1998 16:58:42 -0500
Links: << >>  << T >>  << A >>
Allelujah!

Hitesh Patel wrote:

>   ------------------------------------------------------------------------
>
> Over the past several months, there have been multiple requests
> for Viewsim functional simulation support targeting Virtex. Xilinx
> recognises this need since schematic based Viewlogic users
> verify their design functionality using Viewsim. As a result,
> Xilinx together with the help of Viewlogic and Philip Freidin will
> support functional simulation for Virtex. The planned schedule for
> support is as follows:
>
> Q1 '99          - Support for gate level functional simulation library
>                   (will be available via ftp)
> Q2 '99 (A2.1)   - Functional Simulation support for block RAM and
>                   other specialty memory functions.
>
> This flow will support functional simulation for Virtex using
> Viewsim and static timing analysis using TRCE for post-route
> delay analysis.
>
> Regards,
> Hitesh Patel
> Product Marketing Manager
> EDA Partner Solutions



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13764
Subject: Re: PLL in FPGAs?
From: Bob Sefton <rsefton@home.com>
Date: Wed, 23 Dec 1998 02:18:42 GMT
Links: << >>  << T >>  << A >>
Brett -

It's easy to do the phase detector in an FPGA, but you'll need an
external VCO or VCXO and an analog loop filter to get the jitter
specs you want. If you tried to go all digital the best jitter you
could achieve would be 1/2 the period of your reference clock (I
think). To get 1ns jitter you'd need a 500MHz reference clock.

If you use a conventional PLL with VCXO you should be able to
easily achieve 1ns jitter (which is about 50ppm at 48kHz). In the
FPGA you'd just need a phase detector (normally 2 FFs and a few
gates), and a divider to divide your reference clock down if it's
not a 48kHz VCXO. You should be able to find an App note (Altera
or Xilinx) for this.

Bob S.


Brett George wrote:
> 
> Hi all,
> 
> Has anyone tried implementing a PLL in an FPGA (eg. ALTERA), we are
> thinking of using it to reduce clock jitter from an externally generated
> clock source.
> Do they come in Macrofunctions?
> Whal would be the accuracy of such a PLL?
> eg. If the incoming clock had a frequency of 48kHz with jitter of 20 ns,
> would
> the implemented PLL be able to reduce the jitter to 1ns?
> 
> The delay throught the FPGA is not a problem, just the jitter.
> 
> Thanks in advance,
> Brett.

Article: 13765
Subject: This topic is new to me, ANY ONLINE FPGA TUTORIALS?
From: "davegail" <davegail@mediaone.net>
Date: Tue, 22 Dec 1998 21:29:42 -0500
Links: << >>  << T >>  << A >>
davegail@mediaone.net


Article: 13766
Subject: Xilinx Simulator
From: #YEO WEE KWONG# <P7102672H@ntu.edu.sg>
Date: Wed, 23 Dec 1998 10:52:28 +0800
Links: << >>  << T >>  << A >>
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------_=_NextPart_001_01BE2E1F.46F73273
Content-Type: text/plain;
	charset="iso-8859-1"

Dear all,

I have been using Xilinx gate level simulator for testing my design and
realised that it gave me error which other simulator don't. Wonder
anyone can give some explanation. 

My problem :
I tried to synthesis and simulate a design that triggers on two edges of
the clock. I used Fusion HDL simulator by Viewlogic and it allows me to
simulate my design but when it comes to Xilinx simulator, it throws me
an error with "clock specification not supported". Can any kind soul
help

Yeo Wee Kwong


------_=_NextPart_001_01BE2E1F.46F73273
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2232.0">
<TITLE>Xilinx Simulator </TITLE>
</HEAD>
<BODY>

<P><FONT FACE=3D"Arial">Dear all,</FONT>
</P>

<P><FONT FACE=3D"Arial">I have been using Xilinx gate level simulator =
for testing my design and realised that it gave me error which other =
simulator don't. Wonder anyone can give some explanation. </FONT></P>

<P><FONT FACE=3D"Arial">My problem :</FONT>
<BR><FONT FACE=3D"Arial">I tried to synthesis and simulate a design =
that triggers on two edges of the clock. I used Fusion HDL simulator by =
Viewlogic and it allows me to simulate my design but when it comes to =
Xilinx simulator, it throws me an error with "clock specification not =
supported". Can any kind soul help</FONT></P>

<P><B><I><FONT COLOR=3D"#008080" FACE=3D"Bookman Old Style">Yeo Wee =
Kwong</FONT></I></B><B><I></I></B><B><I></I></B>
</P>

</BODY>
</HTML>
------_=_NextPart_001_01BE2E1F.46F73273--

Article: 13767
Subject: Re: VHDL books (seeking)
From: Edwin Naroska <edwin@mira.e-technik.uni-dortmund.de>
Date: Wed, 23 Dec 1998 10:12:47 +0100
Links: << >>  << T >>  << A >>
Hi,

Tim O wrote:

> Can anyone give suggestions for books on synthesizable VHDL.  I've
> been working with PLD designs with VHDL for a while so what I'm really
> looking for is something that _doesn't_ start out with the basics
> i.e., more advanced topics and techniques but still within the bounds
> of pratical, synthesizable code.  If it's written from a communication
> systems (or signal processing) perspective I'd probably weep from joy.
>

check out the comp.lang.vhdl FAQ at

        http://www.vhdl.org/comp.lang.vhdl/.

Part 2 lists books on VHDL as well as some books which were
frequently recommended in comp.lang.vhdl.


Edwin

Article: 13768
Subject: Re: [Question] How to make Random in VHDL
From: Edwin Naroska <edwin@mira.e-technik.uni-dortmund.de>
Date: Wed, 23 Dec 1998 10:21:56 +0100
Links: << >>  << T >>  << A >>
Hi,

John Huang wrote:

> Hi:
>     I need a method that can make random number(integer) in VHDL,

You may check out the following links to get a random generator
package

            http://erm1.u-strasbg.fr/db/
            http://rassp.scra.org/vhdl/models/math.html



Edwin

Article: 13769
Subject: Re: Atmel's PLD
From: Valentin Serb <vali@thcomm.dnt.ro>
Date: Wed, 23 Dec 1998 11:32:25 +0200
Links: << >>  << T >>  << A >>
Rolavine wrote:
> 
> >Subject: Re: Atmel's PLD
> >From: Valentin Serb
> 
> >I used ATV2500 in a few designs,
> >and had troubles. Starting with the strange behavior of the part when
> >unused I/O's weren't connected to known levels (I haven't found any
> >refferals in the datasheet regarding this issue, although it is good
> >design practice).
> 
> Since pull ups, or downs are not built in, I alsways treated unused inputs as
> if they were cmos types. I made unused I/O s outputs and assigned them to
> static levels. I had trouble with this early on, and learned quickly.

Yes, that's right. But the guys from Atmel didn't state in the
datasheet, that is MANDATORY to externally connect unused inputs, and to
assign the unused I/O's static levels explicitly. I would expect the
software to do that stuff.

> 
> Then I found many defective parts in the equipment
> >which used them (it was a telecom equipment). I supposed there was some
> >sort of latch-up, since I could not reproduct the conditions. And the
> >fact that being OTP, one can not test the idea before the actual
> >implementation.
> >
> ATV2500s were available in ceramic UV errasable packages. If the code was not
> protected you can read out the configuration data on a programmer and compare
> it against what it is supposed to be. Also, If this is from a comercial
> product, the engineer who did the PLD should have provided a set of test
> vectors for the testing of the programmed device after it is programmed. So the
> device can be functinally tested (not at speed but..) on the programmer.

Of course I tested the device after being programmed, but I wondered
about the great number of broken devices, when I could not test
anything. Unlike the 2500's Atmel's 89C51 controllers, behaved much more
reliable. Although used together in the application, in the majority of
cases, the 2500 was defective, and the 89C51 not.

And I had another problem with a 750, which when used in combination
with a codec device, altered the audio output. The supposition I made
was that the PowerDown feature, when activated generated some noise on
the supply lines. Replacing the devices with another series whithout the
PowerDown feature, solved the problem. I did not searh over for an
explanation, because my support from Atmel came through a third party
company and it was very slow.

> 
> Hope this helps, but it seems like your blaming the PLD when it maybe your
> process. A further question can be made of the tools used for creating the
> configuration data for the device but that is another story.
> 
> Rocky Lavine
> Rocky Test
> balanced engineering

Regards

Valentin


Article: 13770
Subject: Re: Problem with Xilinx Foundation
From: "Sergio A. Cuenca Asensi" <sergio@dtic.ua.es>
Date: Wed, 23 Dec 1998 13:19:08 +0100
Links: << >>  << T >>  << A >>


Rickman wrote:

>
> >
> > architecture arch2_rgbcore of rgbcore is
> > begin
> > process(clock,reset)
> > begin
> >  if reset='1' then
> >   rgb <= "000000";
> >  elsif (clock'event and clock='1') then
> >   case data(3 downto 0) is
> >    when "0000"|"0001"|"0010"|"0011" =>   rgb <= "000000";-- negro
> >    when "0100"|"0101"|"0110"|"0111" =>   rgb <= "010101";-- gris1
> >    when "1000"|"1001"|"1010"|"1011" =>   rgb <= "101010";-- gris2
> >    when "1100"|"1101"|"1110"|"1111" =>   rgb <= "111111";-- blanco
> >    when others => rgb <= "110000"; -- rojo
> >   end case;
> >  end if;
> > end process;
> > end arch2_rgbcore;
> >
> > Now the synthesis is OK but one error occurred in the Traslation phase
> > of the implementation
> >
> > Traslation report
> > ERROR:basnb:79 - Pin mismatch between block "U1", TYPE="RGBCORE", and
> > file
> >    "C:\MyDesign\FProj\BORRAR\xproj\ver2\RGBCORE.ngo" at pin "DATA<1>".
> > Please
> >    make sure that all pins on the instantiated component match pins in
> > the
> >    lower-level design block.  (Pin-name matching is case-insensitive.)
> >
>
> I am no guru, but I don't think your problem is in the architecture of
> your code. I have been using Foundation for a while and the only time I
> get this error is when I have made a change to either the schematic
> symbol or the VHDL code and the symbol pin list does not match the port
> list in the VHDL. It does not look like you changed this intentionally,
> but have you made an accidental typo, or did you accidentally change a
> pin on the symbol? Perhaps you changed the number of bits in a bus on
> one and not the other?
>
> If you don't see a problem, you might want to delete the symbol and add
> it back again. I have seen "invisible" problems where I had to do this
> to fix it. Of course, there are many bug fixes in V1.5 so an obvious
> suggestion is to upgrade. I haven't myself because I am in the middle of
> a design. But then I am still fighting bugs that I am told are fixed in
> V1.5i.
>
> Sometimes it seems that the only hard part of doing FPGA design is
> learning how to work around the tools!
>
> --
>
> Rick Collins
>
> redsp@XYusa.net
>
>

Thank you for your comments.
I think, I have found the cause of the ERROR, .
The problem is with the optimization process of FPGAExpress. In architecture
arch2 I have used all bits of data in order to asign the output rgb, but
really data(1) and data(0)  are not necesary to generate rgb bits.
I could have wrote:

case data(3 downto 2) is
    when "00" =>   rgb <= "000000";-- negro
    when "01" =>   rgb <= "010101";-- gris1
    when "10" =>   rgb <= "101010";-- gris2
    when "11" =>   rgb <= "111111";-- blanco
    when others => rgb <= "110000"; -- rojo
end case;


So I think that in the optimization process data(1), data(0), data(4) and
data(5)  are eliminated because no logic is generated by them.
The conclusion is that data is transformed in a 2-bit vector instead of  a
6-bit vector, but in the symbol generated from the .xnf file appear
data(5..0) and I donīt notice the change.
To confirm this I modify the arch2 adding a simple asignation.

architecture arch21_rgbcore of rgbcore is
 begin
 process(clock,reset)
 begin
  if reset='1' then
   rgb <= "000000";
  elsif (clock'event and clock='1') then
   case data(3 downto 0) is
    when "0000"|"0001"|"0010"|"0011" =>   rgb <= "000000";-- negro
    when "0100"|"0101"|"0110"|"0111" =>   rgb <= "010101";-- gris1
    when "1000"|"1001"|"1010"|"1011" =>   rgb <= "101010";-- gris2
    when "1100"|"1101"|"1110"|"1111" =>   rgb <= "111111";-- blanco
    when others => rgb <= "110000"; -- rojo
   end case;
  end if;
 end process;
 error<= data(5) and data(4) and data(1) and data(0); -- error is a out
std_logic
 end arch21_rgbcore;

Now the implementation is OK;

If my conclusion is rigth I wonder if I will have to make the simplification
"with a pencil"  before I write my vhdl code!!!!!
I hope 1.5v will be as good as Xilinx proclaim.


===================================================================
Sergio A. Cuenca Asensi
Dept. Tecnologia Informatica y Computacion (TIC)
Escuela Politecnica Superior, Campus de San Vicente
Universidad de Alicante
Ap. Correos 99, E-03080 ALICANTE
email   : sergio@dtic.ua.es
Phone : +34 96 590 39 34
Fax     : +34 96 590 39 02
===================================================================


Article: 13771
Subject: Re: Xilinx XC4000 cinfigured from EPC2?
From: Victor Snesarev <hw4@nortelnetworks.com>
Date: Wed, 23 Dec 1998 08:03:57 -0500
Links: << >>  << T >>  << A >>
Our Altera rep. at RTP, North Carolina will have samples available after
Christmas.

There's also a data sheet on Altera's web site:

http://www.altera.com/document/ds/dsconf.pdf

Sorry, cannot comment on Xilinx application of that chip.

Cheers,

Victor

Steve Dewey wrote:

> Carl
>
> Have you any availability info from Altera about the EPC2 ?
> Samples or production ? They were supposed to be available in October, but
> I've not seen any yet. I heard there were some production problems...
>
> Without _FIRM_ information from Altera I'd be very careful. (Remember the
> 6502 microprocessor core that never quite made it into Maxplus ? Look in the
> AHDL manual November 1995 page 130. I'm still waiting.)
>
> CPoirier@Kodak.com "Carl R. Poirier" writes:
>
> > I looking into loading an Altera EPC2 with configuration data for a Xilinx
> > XC40xx.  Does anyone know if this is possible?
> >
> > I'm interested in the ISP capability of Altera's EPC2 using the JTAG bus,
> > but I'm using Xilinx XC40xx devices.  I need the ability to reload the
> > configuration EPROM using only the JTAG port.
> >
>
> --
> Steve Dewey
> Steve@s-deweynospam.demon.co.uk
> Too boring to have an interesting or witty .sig file.



Article: 13772
Subject: Re: This topic is new to me, ANY ONLINE FPGA TUTORIALS?
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Wed, 23 Dec 1998 06:56:48 -0800
Links: << >>  << T >>  << A >>
You may find the material on The Programmable Logic Jump Station useful at
http://www.optimagic.com , especially the FAQ.

There is also information on the types of devices sold by various PLD
vendors, design software, books, boards, consultants, etc.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

davegail wrote in message ...
>davegail@mediaone.net
>
>


Article: 13773
Subject: some vhdl synthesis results
From: rk <rich.katz@nospam.gsfc.nasa.gov>
Date: Wed, 23 Dec 1998 12:30:20 -0500
Links: << >>  << T >>  << A >>

--------------4E92BF8216786F512DB091D3
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

hi,

i ran a series of tests, thought it might be interesting to post.

rk

========================================================

Below is a comparison of 3 VHDL synthesizers and how
they perform on some basic arithmetic operations.  Common
functions such as adders and incrementers were tested with
identical VHDL source used for each run.

The three synthesizers are labeled C, M, and E, (cheap,
medium, and expensive) which reflects their approximate cost
(order of magnitude).  C => 10^0, M => 10^3, and E => 10^6
in dollars.

Finally, some runs were made with a macro generator for
comparisons.

======================================================

Vectors are 8 bits

A carry out bit was used for each function

Mapped to Act 3 technology

Fanout limit set to 16

Delay constraint set to 1 usec (where available)

Optimized for area.

======================================================

A+B      Add two vectors

A+1      Increment vector

A+SL     Add a Std_Logic bit to a vector

A+B+1    Add two vectors and increment by 1

A+/-1    Incrementer/decrementer (i.e., stack pointer)

Add/Sub  Adder/subtractor

======================================================

         Area is in Act 3 modules
         ________________________


         A+B    A+1    A+SL   A+B+1  A+B+SL   A+/-1   Add/Sub

C         25     14     15      28     29       26

M         25     14     15      29     29       26

E         17     14     17      31     18       30

Macro     17     16                    18       30      28


Note: only a high-speed option was available for the macro incrementer.

--------------4E92BF8216786F512DB091D3
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<HTML>
<TT>hi,</TT><TT></TT>

<P><TT>i ran a series of tests, thought it might be interesting to post.</TT><TT></TT>

<P><TT>rk</TT><TT></TT>

<P><TT>========================================================</TT><TT></TT>

<P><TT>Below is a comparison of 3 VHDL synthesizers and how</TT>
<BR><TT>they perform on some basic arithmetic operations.&nbsp; Common</TT>
<BR><TT>functions such as adders and incrementers were tested with</TT>
<BR><TT>identical VHDL source used for each run.</TT><TT></TT>

<P><TT>The three synthesizers are labeled C, M, and E, (cheap,</TT>
<BR><TT>medium, and expensive) which reflects their approximate cost</TT>
<BR><TT>(order of magnitude).&nbsp; C => 10^0, M => 10^3, and E => 10^6</TT>
<BR><TT>in dollars.</TT><TT></TT>

<P><TT>Finally, some runs were made with a macro generator for</TT>
<BR><TT>comparisons.</TT><TT></TT>

<P><TT>======================================================</TT><TT></TT>

<P><TT>Vectors are 8 bits</TT><TT></TT>

<P><TT>A carry out bit was used for each function</TT><TT></TT>

<P><TT>Mapped to Act 3 technology</TT><TT></TT>

<P><TT>Fanout limit set to 16</TT><TT></TT>

<P><TT>Delay constraint set to 1 usec (where available)</TT><TT></TT>

<P><TT>Optimized for area.</TT><TT></TT>

<P><TT>======================================================</TT><TT></TT>

<P><TT>A+B&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Add two vectors</TT><TT></TT>

<P><TT>A+1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Increment vector</TT><TT></TT>

<P><TT>A+SL&nbsp;&nbsp;&nbsp;&nbsp; Add a Std_Logic bit to a vector</TT><TT></TT>

<P><TT>A+B+1&nbsp;&nbsp;&nbsp; Add two vectors and increment by 1</TT><TT></TT>

<P><TT>A+/-1&nbsp;&nbsp;&nbsp; Incrementer/decrementer (i.e., stack pointer)</TT><TT></TT>

<P><TT>Add/Sub&nbsp; Adder/subtractor</TT><TT></TT>

<P><TT>======================================================</TT><TT></TT>

<P><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Area is in Act
3 modules</TT>
<BR><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ________________________</TT>
<BR><TT></TT>&nbsp;<TT></TT>

<P><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; A+B&nbsp;&nbsp;&nbsp;
A+1&nbsp;&nbsp;&nbsp; A+SL&nbsp;&nbsp; A+B+1&nbsp; A+B+SL&nbsp;&nbsp; A+/-1&nbsp;&nbsp;
Add/Sub</TT><TT></TT>

<P><TT>C&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 25&nbsp;&nbsp;&nbsp;&nbsp;
14&nbsp;&nbsp;&nbsp;&nbsp; 15&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 28&nbsp;&nbsp;&nbsp;&nbsp;
29&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 26</TT><TT></TT>

<P><TT>M&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 25&nbsp;&nbsp;&nbsp;&nbsp;
14&nbsp;&nbsp;&nbsp;&nbsp; 15&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 29&nbsp;&nbsp;&nbsp;&nbsp;
29&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 26</TT><TT></TT>

<P><TT>E&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 17&nbsp;&nbsp;&nbsp;&nbsp;
14&nbsp;&nbsp;&nbsp;&nbsp; 17&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 31&nbsp;&nbsp;&nbsp;&nbsp;
18&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 30</TT><TT></TT>

<P><TT>Macro&nbsp;&nbsp;&nbsp;&nbsp; 17&nbsp;&nbsp;&nbsp;&nbsp; 16&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
18&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 30&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
28</TT>
<BR><TT></TT>&nbsp;<TT></TT>

<P><TT>Note: only a high-speed option was available for the macro incrementer.</TT></HTML>

--------------4E92BF8216786F512DB091D3--

Article: 13774
Subject: Version 8 of Verilog FAQ released
From: rajesh52@hotmail.com
Date: Thu, 24 Dec 1998 07:13:06 GMT
Links: << >>  << T >>  << A >>
Greetings

Version 8 of Verilog FAQ is ready and is moving to permanent place.

URL for Verilog FAQ is

http://www.angelfire.com/in/verilogfaq/index.html

Please feel free to send it to others. Update links if you have above
URLs on your webpages. Please subscribe from FAQ page to receive
automatic update notices in future.

Following addition/changes are present in version 8.

New Items
- List of two free verilog tutorials added.
- List of Verilog / EDA related conferences added.
- FSM Design and Analysis tools section added. Links to Cisco FSM and
  FSMDesigner added.

Updated items - FAQ page moved to Angelfire site. HTML is cleaned up. -
Information on SMASH mixed signal simulator added. - Information on J.
Bhasker's "Verilog HDL Synthesis, A Practical Primer" added  in list of
books. - Qualis quick reference card added in the list of free cards. - Links
for Analog Verilog and PLI updated.


Verilog Page is also updated and moved to permanent place. URL is
Verilog Page: http://www.angelfire.com/in/rajesh52/verilog.html


Thanks
Rajesh Bawankule (rajesh52@hotmail.com)

-----------== Posted via Deja News, The Discussion Network ==----------
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