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On Feb 20, 11:28=A0am, Ehsan <ehsan.hosse...@gmail.com> wrote: > On Feb 18, 12:24=A0am, Ehsan <ehsan.hosse...@gmail.com> wrote: > > > > > Hi all, > > > I've built a fairly large and complex design in VHDL and tried to > > implement it on a Xilinx virtex-4 FX100 fpga. I have verified the > > functionality of my design through the behavioural simulations. After > > that, I decided to implement it on the fpga. I chose a set of inputs > > the same as I used in the behavioural simulations and then run the > > hardware. When I read the outputs, which are some internal registers, > > they match the values read from the simulations. However, sometimes > > the results do not match. In all of these cases, I use the same inputs > > and moreover I reload the bitstream to the fpga to make the situation > > equal. I thought the timing constraints may be violated, so I reduced > > the clock frequency, however, no significant effect can be seen. I can > > conclude that the design is synthesized according to the desired > > functionality, since it generates the desired outputs in some > > instances. However, I cannot understand why it malfunctions > > occasionally for the fixed inputs. What type of errors can lead to > > this problem? What can I do when the error is not repeatable? > > > My design is basically controlled by an FSM which has 16 states. I > > send the start command and then it goes through all the states and > > finally asserts a done signal. Once the register values are incorrect, > > the done signal is also not set. So, something should stop the FSM > > from moving forward. > > > Thank you in advance for your comments. > > I just used the Chipscope to debug my design. What actually happens is > that the FSM goes to a wrong state in one of the transitions (always > the same). The FSM has 16 states and I designed it using StateCad tool > (included in Xilinx ISE). The FSM has a 4-bit counter, which counts up > every time it goes over the states. In the last state, it checks the > counter value and if it has reached the value of 10, it would go to > the idle state, otherwise it goes to another state and starts another > round. And this is where the error happens: sometimes when the counter > is still less than 10, it goes to the idle state. =A0The design is > synthesized using XST and the fsm is one-hot encoded. > > I'm not sure what I've done wrong. Please let me know if you have any > suggestions. I'm not sure I can help anymore than the others. I also not entirely clear about what your design is doing. In particular I don't understand what the counter is doing. You say it counts up every time it "goes over the states". I don't know what you mean by "goes over the states". Are you saying that in the last state of the FSM that the counter increments? Or are you saying that the counter increments while the FSM is in a particular state and that the FSM only changes when the counter is at some value? I think you are saying the former rather than the latter. When you describe your FSM to us, remember that we have no idea what it is doing, so it is better to explain the details that are important and not worry with the big picture. The point is that you may have a race condition. This is a bit like a timing violation in that some FFs will see the correct inputs and other FFs will see wrong inputs. So this can put the FSM and counter into corrupt states, but the cause is an async input that is changing while the clock edge is rising (or near it). Especially when you use a one hot FSM, if a bit is set when it is not supposed to it can create bizarre conditions with multiple bits running through the FSM as if it were multitasking. To see if this is happening, you can add a bit counter. If the value is ever anything but one, flag an error and stop the FSM/counter to see what you have. I suppose you can also see this with chipscope. Have you looked for this condition? Actually, that lit up a little lightbulb. The other way a race condition can show itself in a one-hot FSM is to cause a state bit to clear while the following state bit does not get set. Then no state bit is set and the FSM is in a corrupt condition that is likely to lock up. However, if you define the state with all bits clear as a valid state, such as the "start" or "idle" state, then this is how it may be getting there. Did you define your "idle" state as having no bits set? RickArticle: 138426
Don't have it here with me but I had a similar problem. Are you using the auto phase align or not? I had the phase alignment set to FIXED with an offset of 55, as I wasn't using the APA module. But then I had disabled the APA by grounding the enable line, so it was generating one set of RLOC for with and one set for without. Make sure you are consistent with your decision unlike me... i missed the enable line :( Hope that helpsArticle: 138427
Hello FPGA Gurus! I have just bought Xilinx ML507 board in order to learn Xilinx FPGAs and ISE tools. Latest experience with XC3130 FPGAs was 13 years ago, but those chips and tools were very easy to use. I was able to run all demos, I have downloaded all possible docs and refernce designs from Xilinx site for ML505 and ML507 boards. However, all these demos include precompiled .ACE and .BIT (some of them) files already, and there is no source where I can start and learn from, otherwise the board is of no use for me. Can you help me and advise where I can get a source for a least HELLO WORLD demo &!!! Many thanks, Regards, PavelArticle: 138428
Hi, I'm trying to use a microcontroller to configure a Spartan 3E using slave serial mode. Trouble is that it never completes - after starting, the DONE never goes high, and the INIT never goes low, so the process tries to run forever. I'm using the algorithm documented at the FPGA-FAQ site here: http://www.fpga-faq.com/FAQ_Pages/0038_Config_FPGA_from_a_processor.htm and my schematic is here: http://members.cox.net/ebrombaugh1/synth/armfpga/armfpga_pg1-3.pdf Things I've checked: - JTAG configuration with the same bitstream works fine. - I've verified that the mode select lines are all pulled high. - I wait for INIT to drop after pulling PROG_B low and before raising PROG_B. - I wait 5us after raising PROG_B before starting to clock data in. - I've verified that the CCLK signal is getting through correctly and meets the min pulse width spec. - I've verified that the DIN signal is transitioning. - I've verified that all the VCCAUX, VCCINT and VCCO2 levels are correct. An interesting observation - the DOUT pin is not transitioning the same way that DIN is - it pulses low at the start, goes high and stays that way throughout the rest of the process. I believe that it should follow DIN with a latency of 64 CCLK cycles, but I'm not seeing that. Any suggestions would be appreciated! EricArticle: 138429
Hey guys, Using uB for the first time and have some questions with how to mate the two parts of my design together. Basically I have a whole FPGA design which deserializes a camlink stream and performs some image processing, then generates the data and signals to write the processed image into the FIFO in my MicroBlaze custom IP to be accessed and used in my uB program. So do I try to import my microblaze design (generated pretty much entirely from wizards) into ISE or vice versa? Either way, I will need my "custom IP" to connect to the outside world, either incorporating the large VHDL design with just the I/O to clock and camera output, or to have the design separate and just pass the data/FIFO signals into my custom IP, which is my preferred method. So when I have to add ports to the custom IP, do I do so in the user_logic.vhd or in the NAME.vhd file? And what is the best way to bring it all together? As you can tell I am very new to this so any pointers to documentation would be grand. Thanks GintsArticle: 138430
http://www.aipst.com/AIPS7102.pdf http://www.aipst.com/aips7102.tar.gzArticle: 138431
On 21 Feb., 01:23, "Marty Ryba" <martin.ryba.nos...@verizon.net> wrote: > Hi gang, > > =A0 =A0 I have an idea for a tweak of my FPGA design that involves essent= ially > building a time interval counter. I found that there are some IP cores ou= t > there that get as much as 100ps resolution, but before I go that route I > want to experiment with something "free" first, especially since I don't > need any bells and whistles like embedded bus protocols or programmable > timers. Neither of the signals I want to time between are synchronous wit= h > my main clock, so I'm thinking of generating a new DCM just for this purp= ose > (I think I have a few left in my XC2V6000-5). Otherwise my fastest clock = is > either 133 MHz or maybe 204.8 MHz coming from an outside clock chip (I mi= ght > be able to goose it to 409.6 MHz). > > My question is there any good "how to" on writing a counter so that it ru= ns > at a maximum clock rate for my chip? I perused the Xilinx site, and there > were some very old articles on fast counters in antique chip architecture= s; > they provide OrCAD macros(?); not even VHDL. > > So, do I just naively code the counter and pray that synthesis does the > right things (I don't need a huge number of bits; my maximum time interva= l > is maybe 80 ns), or are there some tricks needed to get optimum clock spe= ed > (what could I rationally expect in this FPGA?)? > > Thanks for your help, > > Marty Hi Marty, the general way for fast design is reducing combinatorical logic. For counters (or FSMs) that means using shift register based designs. Depending on the number of clock cycles you want to count you can either design a simple FSM and use OneStateHot encoding, or build a Johnson counter with a small ripple generator (e.g. a edge detecting monoflop) or use a LFSR structure. All of these give you maximum speed. Have a nice synthesis EilertArticle: 138432
In comp.arch.fpga, Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: > Stef wrote: >> Hello, >> >> Xilinx provides IBIS files for the spartan (and other) devices. In these >> files the IBIS model of each possible IO driver type is given. But because >> the IO can be configured, there is no fixed IBIS for a completed design. >> >> After P&R, there is a pin mapping file which tells which pin has which >> IO standard and drive strength. Together with the IBIS file per IO type, >> it seems a fairly simple task of generating a specific IBIS file for the >> completed design. >> >> Is there an option in ISE or a separate tool to generate such an IBIS >> file? The task seems so simple, I'm tempted to try it myself. But that >> would be a waste of effort if the tool already exists. :-) >> > > Yes, there is a tool within the ISE distribution called IBISWriter that > does exactly what you want. Thanks! That indeed does (almost) exactly what I want! I had already searched the ISE (9.2) help for "IBIS", but that did not lead to this tool. But after another look at the processes window, it's staring me in the face: "Generate IBIS Model" :blush: After a quick look, the IBIS file looks allright except for 2 things: Pin numbers include the preceeding 'P', so pin one is "P1", not "1". This means Hyperlynx can not match them with my board's pin numbers. I have a BLVDS_25 I/O buffer and one pin (data_p) is correctly assigned BLVDS_25, but the other pin (data_n) is assigned BLVDS_25_O. The buffer is instantiated in VHDL with the IOBUFDS component. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Try to get all of your posthumous medals in advance.Article: 138433
reganireland@gmail.com wrote: > So do I try to import my microblaze design (generated pretty much > entirely from wizards) into ISE That's what I do - add the .xmp file in ISE like any .vhd source file, then select it and "View HDL Instantiation Template", copy the template and add it to my design. - Philip -- Wer Rechtschreibfehler findet darf sie behalten.Article: 138434
Hello guys, I am building a system wich employs the DDR controller generated by MIG 2.0 for a DDR memory + Spartan3E. So far the simulations work fine, and according to the waveforms on UG086. I am using a burst length of 4. My doubt is: for writting, after sending a burst (4 times data), can I continue sending data continuously within the same write command, or should I always terminate the command (with the burst_done signal) and send another write command again in order to write another block in a burst with lenght 4 ? Of course, all of this provided the attention to the auto refresh request. All of your help is welcome.Article: 138435
Hi, > I'm having trouble loading my bitstream into the parallel NOR flash > using the indirect method with a Spartan 3A DSP. =A0 I imagine using Impact, you tried to use to program Flash EDK ? I also now using 3400 with Flash 28F640, I not have problem in Impact or in EDK. The links to the Flash are OK ? Respect the Pinout ? Kappa.Article: 138436
On Sun, 22 Feb 2009 21:47:09 -0800 (PST), emeb <ebrombaugh@gmail.com> wrote: >Hi, > >I'm trying to use a microcontroller to configure a Spartan 3E using >slave serial mode. Trouble is that it never completes - after >starting, the DONE never goes high, and the INIT never goes low, so >the process tries to run forever. > >I'm using the algorithm documented at the FPGA-FAQ site here: > >http://www.fpga-faq.com/FAQ_Pages/0038_Config_FPGA_from_a_processor.htm > >and my schematic is here: > >http://members.cox.net/ebrombaugh1/synth/armfpga/armfpga_pg1-3.pdf > >Things I've checked: >- JTAG configuration with the same bitstream works fine. Stupid question #1 : does this give that annoying Impact message that some clock option has been changed from CCLK to JTAG (but the original bitstream is unchanged)? If not, perhaps you just need to re-run Bitgen with the CCLK option? - BrianArticle: 138437
On 23 feb, 10:48, Jaime Andr=E9s Aranguren Cardona <jaime.arangu...@gmail.com> wrote: > Hello guys, > > I am building a system wich employs the DDR controller generated by > MIG 2.0 for a DDR memory + Spartan3E. So far the simulations work > fine, and according to the waveforms on UG086. > > I am using a burst length of 4. My doubt is: for writting, after > sending a burst (4 times data), can I continue sending data > continuously within the same write command, or should I always > terminate the command (with the burst_done signal) and send another > write command again in order to write another block in a burst with > lenght 4 ? Of course, all of this provided the attention to the auto > refresh request. > > All of your help is welcome. Hi, The answer was there: "The user must terminate the transfer on a column boundary and must re-initialize the controller for the next row of transactions on a column boundary" Now the question is different: I can get (in simulation) all the signals working, except cntrl0_ddr_dq and cntrl0_ddr_dqs (the most important ones!). I did a loopback between cntrl0_rst_dqs_div_out and cntrl0_rst_dqs_div_in, but both stay all the time in LOW, whereas in the simulation filed delivered by MIG I can see them toggling sometimes to HIGH; the simulation filed delivered by MIG also do a simple loopback. What else can I be missing? What tips should I be aware of to get this running? Kind regards.Article: 138438
On Feb 23, 7:31=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Sun, 22 Feb 2009 21:47:09 -0800 (PST), emeb <ebromba...@gmail.com> wro= te: > >Hi, > > >I'm trying to use a microcontroller to configure a Spartan 3E using > >slave serial mode. Trouble is that it never completes - after > >starting, the DONE never goes high, and the INIT never goes low, so > >the process tries to run forever. > > >I'm using the algorithm documented at the FPGA-FAQ site here: > > >http://www.fpga-faq.com/FAQ_Pages/0038_Config_FPGA_from_a_processor.htm > > >and my schematic is here: > > >http://members.cox.net/ebrombaugh1/synth/armfpga/armfpga_pg1-3.pdf > > >Things I've checked: > >- JTAG configuration with the same bitstream works fine. > > Stupid question #1 : does this give that annoying Impact message that som= e clock > option has been changed from CCLK to JTAG (but the original bitstream is > unchanged)? > If not, perhaps you just need to re-run Bitgen with the CCLK option? > > - Brian Yeah, it's really too bad that Xilinx can't figure out how to start up with whatever clock was used for configuration... Also in answer to your DOUT observation, I believe that DOUT only follows the DIN after configuration is complete, otherwise running multiple slave serial configs in series would not work. i.e. the first device "eats" the first bitstream and passes remaining bitstreams to the next FPGA in line, etc. Regards, GaborArticle: 138439
On 23 feb, 13:57, Jaime Andr=E9s Aranguren Cardona <jaime.arangu...@gmail.com> wrote: > On 23 feb, 10:48, Jaime Andr=E9s Aranguren Cardona > > > > > > <jaime.arangu...@gmail.com> wrote: > > Hello guys, > > > I am building a system wich employs the DDR controller generated by > > MIG 2.0 for a DDR memory + Spartan3E. So far the simulations work > > fine, and according to the waveforms on UG086. > > > I am using a burst length of 4. My doubt is: for writting, after > > sending a burst (4 times data), can I continue sending data > > continuously within the same write command, or should I always > > terminate the command (with the burst_done signal) and send another > > write command again in order to write another block in a burst with > > lenght 4 ? Of course, all of this provided the attention to the auto > > refresh request. > > > All of your help is welcome. > > Hi, > > The answer was there: > > "The user must terminate the transfer on a > column boundary and must re-initialize the controller for the > next row of transactions on a column boundary" > > Now the question is different: I can get (in simulation) all the > signals working, except cntrl0_ddr_dq and cntrl0_ddr_dqs (the most > important ones!). I did a loopback between cntrl0_rst_dqs_div_out and > cntrl0_rst_dqs_div_in, but both stay all the time in LOW, whereas in > the simulation filed delivered by MIG I can see them toggling > sometimes to HIGH; the simulation filed delivered by MIG also do a > simple loopback. > > What else can I be missing? What tips should I be aware of to get this > running? > > Kind regards.- Ocultar texto de la cita - > > - Mostrar texto de la cita - Hello guys. Again, I could find it myself: I just had to put the testbench side of the bus in Hi-Z. Now the signals (all of them) show correct activity. Nevertheless, thanks for reading. Regards.Article: 138440
On Feb 23, 5:31=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Sun, 22 Feb 2009 21:47:09 -0800 (PST), emeb <ebromba...@gmail.com> wro= te: > >Hi, > > >I'm trying to use a microcontroller to configure a Spartan 3E using > >slave serial mode. Trouble is that it never completes - after > >starting, the DONE never goes high, and the INIT never goes low, so > >the process tries to run forever. > > >I'm using the algorithm documented at the FPGA-FAQ site here: > > >http://www.fpga-faq.com/FAQ_Pages/0038_Config_FPGA_from_a_processor.htm > > >and my schematic is here: > > >http://members.cox.net/ebrombaugh1/synth/armfpga/armfpga_pg1-3.pdf > > >Things I've checked: > >- JTAG configuration with the same bitstream works fine. > > Stupid question #1 : does this give that annoying Impact message that som= e clock > option has been changed from CCLK to JTAG (but the original bitstream is > unchanged)? > If not, perhaps you just need to re-run Bitgen with the CCLK option? Yes - when using impact for the JTAG configuration it does give the msg: INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory, but the original bitstream file remains unchanged. Rerunning bitgen with -g StartupClk:Cclk doesn't change the behavior. Note that this option is the default. Thanks, EricArticle: 138441
On Feb 23, 6:44=A0am, gabor <ga...@alacron.com> wrote: > Also in answer to your DOUT observation, I believe that DOUT only > follows the DIN after configuration is complete, otherwise running > multiple slave serial configs in series would not work. =A0i.e. the > first device "eats" the first bitstream and passes remaining > bitstreams to the next FPGA in line, etc. Good point - it's got to hold the DOUT high until it's got all its own data before passing the remaining on any further devices in the chain. So that little clue doesn't mean anything. Another thing - checking the device status via JTAG from impact while trying to configure from software shows that it is in mode '111' (slave serial) as intended, no CRC error (or any other errors) and it's in CFG_RDY mode (INIT_B =3D 1). It's like the CCLK and DIN pins aren't even hooked up, even though I can see them toggling with my 'scope. There is some mention in the datasheet about terminating the CCLK input. I haven't done that, but I'm driving it from a GPIO pin which doesn't have real fast edges. Do you suppose that might be an issue? EricArticle: 138442
Hi all, to cover the needs of my application, I wish to generate from a 50 MHz crystal attached to my cyclone2 fpga (EP2C35) the four phase (0, 90, 180 and 270 degrees) at 60 MHz. I tried to cascade 2 PLL: - one PLL to generate 60 MHz from the crystal, - one PLL to generate 90, 180 and 270 degrees from the previously generated 60 MHz clock. Quartus2 complaints that the input clock for the second PLL "must be driven by a non-inverted input clock pin". So I guess PLL macros cannot be cascaded. How could I resolve this issue? Has anyone a better design? Thanks a lot.Article: 138443
Bert wrote: > Quartus2 complaints that the input clock for the second PLL "must be > driven by a non-inverted input clock pin". So I guess PLL macros > cannot be cascaded. > > How could I resolve this issue? Has anyone a better design? Maybe using one PLL with two outputs at 0° and 90° and then inverting the outputs for 180° and 270° work. At least a test project compiles without errors and with 0 warnings (after supressing the LogicLock feature warning; I like 0 warnings :-) http://www.frank-buss.de/tmp/ClockTest.zip -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 138444
Have you checked that the mode pins M0-2 are in the correct state for this mode of operation? John Adair Enterpoint Ltd. emeb wrote: > Hi, > > I'm trying to use a microcontroller to configure a Spartan 3E using > slave serial mode. Trouble is that it never completes - after > starting, the DONE never goes high, and the INIT never goes low, so > the process tries to run forever. > > I'm using the algorithm documented at the FPGA-FAQ site here: > > http://www.fpga-faq.com/FAQ_Pages/0038_Config_FPGA_from_a_processor.htm > > and my schematic is here: > > http://members.cox.net/ebrombaugh1/synth/armfpga/armfpga_pg1-3.pdf > > Things I've checked: > - JTAG configuration with the same bitstream works fine. > - I've verified that the mode select lines are all pulled high. > - I wait for INIT to drop after pulling PROG_B low and before raising > PROG_B. > - I wait 5us after raising PROG_B before starting to clock data in. > - I've verified that the CCLK signal is getting through correctly and > meets the min pulse width spec. > - I've verified that the DIN signal is transitioning. > - I've verified that all the VCCAUX, VCCINT and VCCO2 levels are > correct. > > An interesting observation - the DOUT pin is not transitioning the > same way that DIN is - it pulses low at the start, goes high and stays > that way throughout the rest of the process. I believe that it should > follow DIN with a latency of 64 CCLK cycles, but I'm not seeing that. > > Any suggestions would be appreciated! > > EricArticle: 138445
On Feb 23, 10:09=A0am, John Adair <g...@enterpoint.co.uk> wrote: > Have you checked that the mode pins M0-2 are in the correct state for > this mode of operation? Yes, I've checked them with both a voltmeter and a scope. Also, the JTAG status (via iMPACT) shows them in the correct state. EricArticle: 138446
It's also worth sometimes putting in a few extra clock edges at the end. Also watch the LED on as it may clamp DONE low enough not be seen as a high. John Adair Enterpoint Ltd. On 23 Feb, 17:23, emeb <ebromba...@gmail.com> wrote: > On Feb 23, 10:09=A0am, John Adair <g...@enterpoint.co.uk> wrote: > > > Have you checked that the mode pins M0-2 are in the correct state for > > this mode of operation? > > Yes, I've checked them with both a voltmeter and a scope. Also, the > JTAG status (via iMPACT) shows them in the correct state. > > EricArticle: 138447
On Feb 23, 10:34=A0am, John Adair <g...@enterpoint.co.uk> wrote: > It's also worth sometimes putting in a few extra clock edges at the > end. Also watch the LED on as it may clamp DONE low enough not be seen > as a high. Yes, after I finish sending the bitstream data I continue to provide CCLK transitions while holding DIN high. During this time my firmware watches both the INIT and DONE lines - neither of them changes state. The DONE LED never comes on either, so it's not an issue of the logic level not registering a '1' either. When I configure it via JTAG the DONE LED does light up and the voltage on the DONE line is about 1.9V (it's a blue LED). The MCU specs a min Vih of 2.0V, so this might be an issue once I get that LED to turn on though. Thanks, EricArticle: 138448
I Am a postgraduate student an my thesis subject is an implement of an fm digital demodulator.I have already implement a digital down converter with I and Q base band signals in 2 complement format.Has anyone an idea about how i can achieve demodulation with these two base band signals.I use a cyclone III altera FPGA. -- xristos ------------------------------------------------------------------------ xristos's Profile: http://www.fpgacentral.com/group/member.php?userid=15 View this thread: http://www.fpgacentral.com/group/showthread.php?t=88112Article: 138449
Jaime Andrés Aranguren Cardona wrote: > I am building a system wich employs the DDR controller generated by > MIG 2.0 for a DDR memory + Spartan3E. So far the simulations work > fine, and according to the waveforms on UG086. I am also interested in using DDR with the Spartan 3E (such as on the Digilent Spartan 3E board.) Most of my problems should be relatively simple. I don't need the full speed, or even bursts of more than one. I haven't looked at UG086 yet. -- glen
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