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Messages from 13900

Article: 13900
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: ems@riverside-machines.com.NOSPAM
Date: Fri, 01 Jan 1999 12:47:19 GMT
Links: << >>  << T >>  << A >>
On Thu, 31 Dec 1998 19:12:43 -0800, "Bruce Nepple"
<brucen@imagenation.extra.com> wrote:

> Peter, you seem to be missing the point which is that the cross coupled
> latch, as I described it, will oscillate, illustrating the effect which
> causes metastability.  You claim that model is bogus.  You are incorrect.

I think this is somewhat unfair on Peter. It's obvious, and I'm sure
he agrees, that your thought experiment will work; if you change two
inputs to an async circuit 'simultaneously' then it may oscillate.

What he actually said was 'go to the lab... try it' (and presumably
not with a 1973-vintage 7400). A *real* circuit recovers from
metastable behaviour, and the tendency to recover is experimentally
measured as the tau parameter (which, in xilinx app notes, is 1/K2).
An XC4005E-3 has a tau of about 0.05, which means, in practice, that
you're *very* unlikely to see any metastable event continue for more
than about 2ns beyond the normal propagation delay (corresponding
figures for 74F logic are 0.4 and about 11ns, respectively). In other
words, infinite oscillation doesn't happen, and, with better
technologies, you may not get *any* oscillation.

>There is no need to reply further if you cannot answer this 2 part question:

Or, of course, if you don't want to.

Evan

Article: 13901
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: rk <stellare@NOSPAMerols.com>
Date: Fri, 01 Jan 1999 07:58:12 -0500
Links: << >>  << T >>  << A >>
Wen-King Su wrote:

> In a previous article "Bruce Nepple" <brucen@imagenation.extra.com> writes:
>
> ;If a cross coupled latch does not go unstable when there is a race on its
> :input, then why is it not, then, a metastable free synchronizer? (which
> ;according to theories I am familiar with, is impossible).
>
> Metastable does not equate oscillation.  When output stays in the illegal
> region for an extented period of time, even if it is not oscillating, it
> is still called metastable.  Oscillation-free synchronizer does exist and
> is being used in many places.

to summarize from what i have read, if a flip-flop goes "metastable" it may:

    1. oscillate

    2. transition to one value and then return to the original one

    3. have a delayed propagation delay time

    4. hang out at non-logic levels.

comments?

rk

Article: 13902
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: "Frank Bemelman" <fbemelx@euronet.nl>
Date: Fri, 1 Jan 1999 16:31:31 +0100
Links: << >>  << T >>  << A >>
Bruce Nepple heeft geschreven in bericht ...
>Peter, you seem to be missing the point which is that the
cross coupled
>2 nand gates with 1 ns prop delay and 0 ns. rise/fall time,
are connected as
>a simple RS latch.  The R and S inputs are connected
together.  Initially
>they are connected to ground, and then are brought to logic
1.  The ideal
>latch then oscillates forever (as a digital ring
oscillator).


Not knowing very much about digital stuff, I apologize for
my possibly stupid thoughts,
but post them anyway here:

I can understand that this ideal flipflop oscillates like
mad at 500 mhz or would it oscillate at perhaps 250 mhz ?

Assuming 5 volts vcc, and rise/fall 2.5 volts/ns, would the
flipflop then go into a stable condition with logic ouput
levels at 2.5 volts ?

What interests me now is, what happens if one gate has 1 ns
prop delay, and the other one 1.1 ns prop delay. It would
not oscillate forever anymore (I suppose) but how many
oscillations would occur before it's stable ?

Also, if prop delays are exactly 1 ns, and rise/fall is 10
ns, does it oscillate also ? In my imagination it would
oscillate. I am now under the impression that equal gates
would always oscillate ?

Apart from these ''ideal'' flipflops, what are my chances to
see a few oscillations if I simply take an old 7400
nand-gate and wire them for this experiment ? I would have
done that already, but unfortunately I do not have an
oscilliscope here.

Happy new year,
Frank Bemelman
(reageren per email ? verwijder dan de 'x' uit mijn
emailadres)


Article: 13903
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: wen-king@myri.com (Wen-King Su)
Date: 1 Jan 1999 11:18:20 -0800
Links: << >>  << T >>  << A >>
In a previous article rk <stellare@NOSPAMerols.com> writes:
:
;Wen-King Su wrote:
:
;> In a previous article "Bruce Nepple" <brucen@imagenation.extra.com> writes:
:>
;> ;If a cross coupled latch does not go unstable when there is a race on its
:> :input, then why is it not, then, a metastable free synchronizer? (which
;> ;according to theories I am familiar with, is impossible).
:>
;> Metastable does not equate oscillation.  When output stays in the illegal
:> region for an extented period of time, even if it is not oscillating, it
;> is still called metastable.  Oscillation-free synchronizer does exist and
:> is being used in many places.
;
:to summarize from what i have read, if a flip-flop goes "metastable" it may:
;
:    1. oscillate
;
:    2. transition to one value and then return to the original one
;
:    3. have a delayed propagation delay time
;
:    4. hang out at non-logic levels.

The word meta-stable refers to a system that remains in a state near a
local energy maximum because all the forces acting on it more or less
canceled out.  The little imballance in forces eventually will push the
system away from the local maximum, but the amount of time it takes is
unbounded. 

When there is an oscillation in a properly designed latch, the output
state itself is not meta-stable.  It is the state of the oscillatory
behavior that is meta-stable.  The latch is bi-stable with respect to its
output state, but mono-stable with respect to its oscillatory behavior.
That means the output eventually settles into one of two states, and the
oscillatory behavior eventually settle to the state of non-oscillation.
A properly designed oscillator is also mono-stable with respect to its
oscillatory behavior, except the stable point is when the circuit is
oscillating.  An oscillator made of an odd number of inverters does not
have a stable output state.  It is astable with respect to output state.

It is not possible to design a latch that will never be excited into a
meta-stable state with respect to its output, for at some point in its
operation it has to make transition across the meta-stable point -- or
else you didn't need to have a latch.  But it is possible to design one
that will never be excited into a meta-stable state with respect to its
oscillatory behavior.  Or more precisely you can say it will not be excited
into a state where its oscillatory behavior will stay meta-stable for
longer than some fraction of the cycle time of any possible oscillation.

Article: 13904
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: rk <stellare@NOSPAMerols.com>
Date: Fri, 01 Jan 1999 15:05:04 -0500
Links: << >>  << T >>  << A >>
Wen-King Su wrote:

> In a previous article rk <stellare@NOSPAMerols.com> writes:
> :
> ;Wen-King Su wrote:
> :
> ;> In a previous article "Bruce Nepple" <brucen@imagenation.extra.com> writes:
> :>
> ;> ;If a cross coupled latch does not go unstable when there is a race on its
> :> :input, then why is it not, then, a metastable free synchronizer? (which
> ;> ;according to theories I am familiar with, is impossible).
> :>
> ;> Metastable does not equate oscillation.  When output stays in the illegal
> :> region for an extented period of time, even if it is not oscillating, it
> ;> is still called metastable.  Oscillation-free synchronizer does exist and
> :> is being used in many places.
> ;
> :to summarize from what i have read, if a flip-flop goes "metastable" it may:
> ;
> :    1. oscillate
> ;
> :    2. transition to one value and then return to the original one
> ;
> :    3. have a delayed propagation delay time
> ;
> :    4. hang out at non-logic levels.
>
> The word meta-stable refers to a system that remains in a state near a
> local energy maximum because all the forces acting on it more or less
> canceled out.  The little imballance in forces eventually will push the
> system away from the local maximum, but the amount of time it takes is
> unbounded.
>
> When there is an oscillation in a properly designed latch, the output
> state itself is not meta-stable.  It is the state of the oscillatory
> behavior that is meta-stable.  The latch is bi-stable with respect to its
> output state, but mono-stable with respect to its oscillatory behavior.
> That means the output eventually settles into one of two states, and the
> oscillatory behavior eventually settle to the state of non-oscillation.
> A properly designed oscillator is also mono-stable with respect to its
> oscillatory behavior, except the stable point is when the circuit is
> oscillating.  An oscillator made of an odd number of inverters does not
> have a stable output state.  It is astable with respect to output state.
>
> It is not possible to design a latch that will never be excited into a
> meta-stable state with respect to its output, for at some point in its
> operation it has to make transition across the meta-stable point -- or
> else you didn't need to have a latch.  But it is possible to design one
> that will never be excited into a meta-stable state with respect to its
> oscillatory behavior.  Or more precisely you can say it will not be excited
> into a state where its oscillatory behavior will stay meta-stable for
> longer than some fraction of the cycle time of any possible oscillation.

hi,

somehow the above seems kind of complicated.  the previous post attempted to list
the symptoms as to  what is commonly referred to as metastability of flip-flops.
perhaps to be more precise, i could have said these are the symtoms that i've seen
or read about when you don't meet the timing specifications of the flip-flop and
saved you a lot of typing.

some formal definitions i have seen of the term refer to when the circuit is
steady at a "stable" point which in the absence of noise can last indefinitely and
do not mention oscillation as a metastable state of its own although that is
perfectly reasonable.  one can, if you are careful, get a simple input stage to
oscillate and stay in that particular state of oscillation for hours.  done it,
not theoretical..  nevertheless, improper operation of a flip-flop can occur if
the specs are not met and METASTABLE OPERATION DOES NOT REQUIRE OSCILLATION as
said by the more previous poster. THE ABOVE LIST BACKS UP THAT POINT.

happy new years,

rk

happy new years,

rk

Article: 13905
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: murray@pa.dec.com (Hal Murray)
Date: 1 Jan 1999 23:09:20 GMT
Links: << >>  << T >>  << A >>
In article <368CC663.A2F4C70@NOSPAMerols.com>, rk <stellare@NOSPAMerols.com> writes:

> to summarize from what i have read, if a flip-flop goes "metastable" it may:
>     1. oscillate
>     2. transition to one value and then return to the original one
>     3. have a delayed propagation delay time
>     4. hang out at non-logic levels.

I'd add runt pulses to the list.


-- 
These are my opinions, not necessarily my employers.

Article: 13906
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: z80@ds2.com (Peter)
Date: Fri, 01 Jan 1999 23:13:40 GMT
Links: << >>  << T >>  << A >>

>When there is an oscillation in a properly designed latch, the output
>state itself is not meta-stable.  It is the state of the oscillatory
>behavior that is meta-stable.  

I think what you are describing is a latch whose *latch* can hang
around half-way between 0 and 1 (this is what most people call
"metastable") and this can *theoretically* last forever.

But any buffers which follow the latch *could* oscillate if fed with
such a logic level.

(The latch itself won't be oscillating because if it were it would
immediately jump out of the metastable state.)

The net effect if such a whole device is that when it is in the
metastable state, you can get a burst of oscillation at the output
pin.

This is quite common. Get a 74HC244, 74AC244, or almost anything, and
feed it with a slow input waveform. Its output will almost certainly
oscillate around the transition.

Whether the output of a simple D-type, e.g. 74HC74 will also oscillate
when its latch front end is metastable I don't know but I would expect
it will.

>It is not possible to design a latch that will never be excited into a
>meta-stable state with respect to its output, for at some point in its
>operation it has to make transition across the meta-stable point -- or
>else you didn't need to have a latch.

One could probably inject noise; this could be used to set a finite
upper time limit on any metastable state.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.

Article: 13907
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: murray@pa.dec.com (Hal Murray)
Date: 2 Jan 1999 00:50:45 GMT
Links: << >>  << T >>  << A >>
> One could probably inject noise; this could be used to set a finite
> upper time limit on any metastable state.

DING DING DING....

Nope.  For every case that the noise helps there is the opposite case
where it pushes things back in the wrong direction.

Rule 0 of metastability is that there is no upper limit.  There is
only a decay time.  If you don't believe or understand that you
don't understand metastability yet.

~10 years ago, there was a wave of "cures" for metastablity.  They
usually involved some kludgy circuit to detect the bad case and then
reach around and reset it.  None of them cured the problem.  They
just made it harder to analyze and often more likely to screwup.

-- 
These are my opinions, not necessarily my employers.

Article: 13908
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: rk <stellare@NOSPAMerols.com>
Date: Fri, 01 Jan 1999 20:23:30 -0500
Links: << >>  << T >>  << A >>
Hal Murray wrote:

> In article <368CC663.A2F4C70@NOSPAMerols.com>, rk <stellare@NOSPAMerols.com> writes:
>
> > to summarize from what i have read, if a flip-flop goes "metastable" it may:
> >     1. oscillate
> >     2. transition to one value and then return to the original one
> >     3. have a delayed propagation delay time
> >     4. hang out at non-logic levels.
>
> I'd add runt pulses to the list.
>
> --
> These are my opinions, not necessarily my employers.

opinion? it's a fact!  you are correct - we should refine case 2 above as the signal may
not make it all the way to the opposite logic state;  i've seen a bunch of them go
partly up and then back down.

thanks,

rk


Article: 13909
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: wen-king@myri.com (Wen-King Su)
Date: 1 Jan 1999 18:43:19 -0800
Links: << >>  << T >>  << A >>
In a previous article z80@ds2.com (Peter) writes:
:
;
:>When there is an oscillation in a properly designed latch, the output
;>state itself is not meta-stable.  It is the state of the oscillatory
:>behavior that is meta-stable.  
;
:I think what you are describing is a latch whose *latch* can hang
;around half-way between 0 and 1 (this is what most people call
:"metastable") and this can *theoretically* last forever.
;
:But any buffers which follow the latch *could* oscillate if fed with
;such a logic level.

That is not really oscillation.  It is just an amplification of noise.
You get the same thing when, instead of a latch, the previous stage is a
small buffer driving a huge capacitive load.  No meta-stability there. 

;(The latch itself won't be oscillating because if it were it would
:immediately jump out of the metastable state.)

Latches with the right properties does oscillate.  But as I said, it is
not the output state in this case that is meta-stable.  Rather, it is the
oscillatory behavior that is meta-stable.  The state space of an output
goes from VOL to VOH.  The state space of the oscillatory behavior, in
the simplest case, is a fixed frequency oscillation with a duty factor
ranging between 0% and 100%.  When output is potentially meta-stable, it
means there is a local energy maximum somewhere in between VOL and VOH.
When oscillatory behavior is potentially meta-stable, it means there is
a local energy maximum somewhere between 0% and 100% duty factor. 
A latch that is meta-stable in its output moves toward a stable state by
having its output voltage change in a direction away from the maximum
energy voltage point.  A latch that is meta-stable in its oscillatory
behavior moves toward a stable state by having its duty cycle move away
from the maximum energy duty cycle point  -- which means one of the phases
of the output wave-form gets smaller and smaller until it disappears. 

Article: 13910
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: rk <stellare@NOSPAMerols.com>
Date: Fri, 01 Jan 1999 22:29:38 -0500
Links: << >>  << T >>  << A >>
Wen-King Su wrote:

> In a previous article z80@ds2.com (Peter) writes:
> :
> ;
> :>When there is an oscillation in a properly designed latch, the output
> ;>state itself is not meta-stable.  It is the state of the oscillatory
> :>behavior that is meta-stable.
> ;
> :I think what you are describing is a latch whose *latch* can hang
> ;around half-way between 0 and 1 (this is what most people call
> :"metastable") and this can *theoretically* last forever.
> ;
> :But any buffers which follow the latch *could* oscillate if fed with
> ;such a logic level.
>
> That is not really oscillation.  It is just an amplification of noise.
> You get the same thing when, instead of a latch, the previous stage is a
> small buffer driving a huge capacitive load.  No meta-stability there.

hmmm ... i believe that you can get a buffer to oscillate.  remember, there
are parasitic inductances in the supplies and there is capacitave coupling
back to the gate.  with older cmos technology (around '84 or so) you could get
an input buffer to go into a self-sustaining oscillation, with a somewhat
stable period, running more or less indefinitely, the outputs switching from
rail to rail.  if you look closely, you can see the feedback onto the gate
with your scope.

happy new years!

rk

Article: 13911
Subject: Re: program flow chart to state machine ?
From: ekuria01@kepler.poly.edu
Date: Sat, 02 Jan 1999 04:22:20 GMT
Links: << >>  << T >>  << A >>
Eli, Thank you very much for your response! I came across a 30 day downlaod
progam called state cad whcih will let me draw staete diagrams and convert to
vhdl and optimize it for fpgas.

Just a really stupid question (this will show you how ignorant i am of this
field) .. What exactly is a netlist ?

My expertiese is assembly coding and that sort of work. I really want to get
my hands into FPGAs.

Well, i know i would need a-d converter to do the digital peak detection, and
have worked out a way to do it. I just wanted to hear if anyone had any
detailed histories or examples of it.

My project is a digital AGC which has to do some twisted stuff to find the
signal in some sick S/N conditions.  It works as a microcontroller, I just
have to make it work in a completly digital world (with some A-Ds of course).

I doubt that it would be as easy as generating the state diagram (whcih in
itself is pretty involved when you have over 1000 lines of assembly code) and
creating vhdl from it.

Well, Thank you again for your response.

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    

Article: 13912
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: wen-king@myri.com (Wen-King Su)
Date: 1 Jan 1999 21:52:35 -0800
Links: << >>  << T >>  << A >>
In a previous article rk <stellare@NOSPAMerols.com> writes:
:
;Wen-King Su wrote:
:
;> In a previous article z80@ds2.com (Peter) writes:
:> :
;> ;
:> :>When there is an oscillation in a properly designed latch, the output
;> ;>state itself is not meta-stable.  It is the state of the oscillatory
:> :>behavior that is meta-stable.
;> ;
:> :I think what you are describing is a latch whose *latch* can hang
;> ;around half-way between 0 and 1 (this is what most people call
:> :"metastable") and this can *theoretically* last forever.
;> ;
:> :But any buffers which follow the latch *could* oscillate if fed with
;> ;such a logic level.
:>
;> That is not really oscillation.  It is just an amplification of noise.
:> You get the same thing when, instead of a latch, the previous stage is a
;> small buffer driving a huge capacitive load.  No meta-stability there.
:
;hmmm ... i believe that you can get a buffer to oscillate.  remember, there
:are parasitic inductances in the supplies and there is capacitave coupling
;back to the gate.

That is still amplified noise, even though it is the switching noise of
the buffer itself that is getting amplified.  Meta-stable condition is a
different beast, for it is something that still exists when all noises
are eliminated.  Funny thing about your example is if you write in the
parasitic capacitances and inductances explicitly in the feedback path
of your circuit representation, what you have is no longer amplified noise
but a bona fide oscillation.  Noise is merely a poorly characterized signal.
When you put the parasitic elements into your circuit representation, you
ended up defining part of it.

Article: 13913
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: z80@ds2.com (Peter)
Date: Sat, 02 Jan 1999 08:31:01 GMT
Links: << >>  << T >>  << A >>

Noise injection won't avoid the *onset* of metastability but it can
certainly terminate it. Consider injecting a sinewave into the latch.
After all, it is *noise* which terminates it, in all practical
devices, AFAIK.

>Nope.  For every case that the noise helps there is the opposite case
>where it pushes things back in the wrong direction.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.

Article: 13914
Subject: Re: How to import EDIF file in Foundation Software?
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Sat, 02 Jan 1999 11:59:45 GMT
Links: << >>  << T >>  << A >>
On Thu, 31 Dec 1998 09:36:11 +0100, Le mer Michel
<michel.lemer@ago.fr> wrote:

>So why did xilinx say us we needed Xilinx Foundation and Xilinx Alliance and asked us
>to PAY for both?

Perhaps the salesperson misunderstood your existing design entry
requirements?

Cheers
Stuart
An employee of Saros Technology, The HDL Solutions Company:
Renoir
Model Technology
Exemplar Logic
TransEDA
www.saros.co.uk
(I sell these products, so paint me biased)

Article: 13915
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: murray@pa.dec.com (Hal Murray)
Date: 2 Jan 1999 12:42:14 GMT
Links: << >>  << T >>  << A >>
In article <368ed8b9.401797193@news.netcomuk.co.uk>, z80@ds2.com (Peter) writes:
> 
> Noise injection won't avoid the *onset* of metastability but it can
> certainly terminate it. Consider injecting a sinewave into the latch.
> After all, it is *noise* which terminates it, in all practical
> devices, AFAIK.

If you have a system that is carefully ballanced in the metastable
state and then you hit it with noise you will kick it out of that
state.  But if you have a system that is leaving a metastable state
the same noise might kick it back closer to dead center.

Suppose you hit a system with a runt pulse that isn't quite big enough
to push things into a metastable state.  Normally, that runt would
get ignored.  With some noise, the pulse might become big enough to
cause troubles.  Similarly, a pulse that was big enough to cause
a clean transition to the other state might get reduced by noise
to a pulse that is small enough to cause trouble.

Those arguments hold for a sine wave as well as random noise.

I think all those cases ballance out.  It's probably easier to
show that if you assume some symmetry.


I don't think that noise is required to exit the metastable state.
I could be wrong here.  I think that is just a convenient way to
explain things.

The standard recipe has an exponential decay on the probability of
remaining metastable.  That corresponds to positive feedback on the
cross coupled amplifiers.  As long as the system isn't exactly in the
wrong state it will eventually leave without any noise.  It may take
an arbitarily long time.  That "exact" match is an analog test not
an n-bit compare.  The time-to-leave corresponds to how close to
the exact match the system was.

[Digital simulations without noise may get stuck forever.]

------

What happens to metastability if I build a FF with something
really strange like Josephson Junctions?

-- 
These are my opinions, not necessarily my employers.

Article: 13916
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: rk <stellare@NOSPAMerols.com>
Date: Sat, 02 Jan 1999 08:53:14 -0500
Links: << >>  << T >>  << A >>
Wen-King Su wrote:

> In a previous article rk <stellare@NOSPAMerols.com> writes:
> :
> ;Wen-King Su wrote:
> :
> ;> In a previous article z80@ds2.com (Peter) writes:
> :> :
> ;> ;
> :> :>When there is an oscillation in a properly designed latch, the output
> ;> ;>state itself is not meta-stable.  It is the state of the oscillatory
> :> :>behavior that is meta-stable.
> ;> ;
> :> :I think what you are describing is a latch whose *latch* can hang
> ;> ;around half-way between 0 and 1 (this is what most people call
> :> :"metastable") and this can *theoretically* last forever.
> ;> ;
> :> :But any buffers which follow the latch *could* oscillate if fed with
> ;> ;such a logic level.
> :>
> ;> That is not really oscillation.  It is just an amplification of noise.
> :> You get the same thing when, instead of a latch, the previous stage is a
> ;> small buffer driving a huge capacitive load.  No meta-stability there.
> :
> ;hmmm ... i believe that you can get a buffer to oscillate.  remember, there
> :are parasitic inductances in the supplies and there is capacitave coupling
> ;back to the gate.
>
> That is still amplified noise, even though it is the switching noise of
> the buffer itself that is getting amplified.  Meta-stable condition is a
> different beast, for it is something that still exists when all noises
> are eliminated.  Funny thing about your example is if you write in the
> parasitic capacitances and inductances explicitly in the feedback path
> of your circuit representation, what you have is no longer amplified noise
> but a bona fide oscillation.  Noise is merely a poorly characterized signal.
> When you put the parasitic elements into your circuit representation, you
> ended up defining part of it.

good morning, wen-king:

i was responding to peter from X's point, i believe, that buffers could
oscillate, not merely amplify noise.

i wouldn't call the oscillation "ability" of even the lowly buffer amplified
noise but a nice oscillator!  as you say, if you write in the parasitics you get
a "bona fide" oscillator which is quite correct.  with regards to putting in
parasitics into my circuit representation, it is not defining part of what i'm
defining, but what's in real circuits.

happy new year!

rk



Article: 13917
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: murray@pa.dec.com (Hal Murray)
Date: 2 Jan 1999 14:20:31 GMT
Links: << >>  << T >>  << A >>
Another basic question...


How does the MTBF depend upon the rise time of the signals?

Are there other interesting parameters that should be considered?

I'd guess that decay time varies over temp and Vcc the same way
that prop time does.

-- 
These are my opinions, not necessarily my employers.

Article: 13918
Subject: XILINX PC104 FPGA card Now available from APS
From: APS <resp@associatedpro.com>
Date: Sat, 02 Jan 1999 10:24:12 -0500
Links: << >>  << T >>  << A >>
The APS-X240 is an FPGA development board with the following features:

* PC104 Format or use stand alone
*240 pin QFP FPGA
*5v or 3.3v operation
*SPARTAN,4000E/XL/XLA,5200
*2 256K SRAMs
*Decode Pals Socketed
*Eprom Socketed
*Xchecker Cable Port
*DMA/IRQ/Address Select
*Oscillator Socket
*Up to 180K Gates (4085)

The Board is available with XILINX Foundation Software.
One popular version is the board with a
SPARTAN XCS40-3PQ240C
256K SRAM on board
Board Price.....................................   $690.00

The same board with a XILINX Foundation VHDL Base kit
which includes:
Synopsys FPGA express,
Schematic capture
M1.5i Router
Board and Software Price:................ $1440.00

Options available include a PC ISA CARD carrier
The board is shipped with a VHDL boilerplate and C control program.

details are available at http://www.associatedpro.com
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 13919
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: rk <stellare@NOSPAMerols.com>
Date: Sat, 02 Jan 1999 11:56:47 -0500
Links: << >>  << T >>  << A >>
Hal Murray wrote:

> In article <368ed8b9.401797193@news.netcomuk.co.uk>, z80@ds2.com (Peter) writes:
> >
> > Noise injection won't avoid the *onset* of metastability but it can
> > certainly terminate it. Consider injecting a sinewave into the latch.
> > After all, it is *noise* which terminates it, in all practical
> > devices, AFAIK.
>
> If you have a system that is carefully ballanced in the metastable
> state and then you hit it with noise you will kick it out of that
> state.  But if you have a system that is leaving a metastable state
> the same noise might kick it back closer to dead center.
>
> Suppose you hit a system with a runt pulse that isn't quite big enough
> to push things into a metastable state.  Normally, that runt would
> get ignored.  With some noise, the pulse might become big enough to
> cause troubles.  Similarly, a pulse that was big enough to cause
> a clean transition to the other state might get reduced by noise
> to a pulse that is small enough to cause trouble.
>
> Those arguments hold for a sine wave as well as random noise.
>
> I think all those cases ballance out.  It's probably easier to
> show that if you assume some symmetry.
>
> I don't think that noise is required to exit the metastable state.
> I could be wrong here.  I think that is just a convenient way to
> explain things.
>
> The standard recipe has an exponential decay on the probability of
> remaining metastable.  That corresponds to positive feedback on the
> cross coupled amplifiers.  As long as the system isn't exactly in the
> wrong state it will eventually leave without any noise.  It may take
> an arbitarily long time.  That "exact" match is an analog test not
> an n-bit compare.  The time-to-leave corresponds to how close to
> the exact match the system was.
>
> [Digital simulations without noise may get stuck forever.]

you might want to refer to INTRODUCTION TO VLSI SYSTEMS, mead and conway, for some
analysis.  i list this one since it was a fairly popular book and probably is easy
for most to get access too.

rk

Article: 13920
Subject: Re: IS: 2001, A Logic Odyssey (WAS: 22V10 Metastability - help please)
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 02 Jan 1999 21:46:16 +0100
Links: << >>  << T >>  << A >>
rk <stellare@NOSPAMerols.com> writes:

> the logic in a gray coded state machine can glitch as much as it
> wants, it's a don't care, as it only cares about what happens at the
> clock edge.  if you choose to insert an asynchronous input into the
> combinational logic of a state machine, any state machine, then you
> can have problems, irregardless of what the coding is.

Exactly. You seem to agree that gray coding a SM is not a cure-all for
asynchronous inputs to SMs.
 
Homann
-- 
   Magnus Homann  Email: d0asta@dtek.chalmers.se
                  URL  : http://www.dtek.chalmers.se/DCIG/d0asta.html
  The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html

Article: 13921
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10
From: Ron Cline <rcline@swcp.com>
Date: Sat, 02 Jan 1999 13:51:05 -0700
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> 
> Another basic question...
> 
> How does the MTBF depend upon the rise time of the signals?
> 

The signals that count are the actual data and clock signals at the
latch or flip-flop.  Usually these signals are buffered beforehand
through at least a couple levels of logic (for example, in the PLDs
being discussed in this thread) so the rise times are internally
determined, with low first-order sensitivity (in terms of metastable
MTBF) to rise times at the pins.  The answer to your question for those
signals at the internal FF is that there is roughly a linear
relationship between internal rise time and MTBF since this directly
affects the acquisition window duration of the data being captured into
the latch.  This linear relationship is less important than the
exponential dependence on tau (see below).

> Are there other interesting parameters that should be considered?
> 

(See below.)

> I'd guess that decay time varies over temp and Vcc the same way
> that prop time does.
> 

Decay time is determined primarily by the metastability time constant of
the latch, the "tau."  This is directly related to the intrinsic gate
delay of the process (as well as the circuit design) and appears in the
exponent of the MTBF equation.  Dependence on temp and Vcc is similar to
the dependence of lightly-loaded gate delay.  A good estimate can be
made by using the percentage increase from typical to worst-case values
of gate delay in an ASIC library.  (Roughly a 50% increase.) 
Manufacturers will usually show only typical values of tau, as
"guaranteeing" tau is problematic on many practical levels.  ("Show me
that failure again...")  The best approach is to allow yourself plenty
of margin, and cross your fingers.

Ron Cline

Article: 13922
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: Ron Cline <rcline@swcp.com>
Date: Sat, 02 Jan 1999 13:57:14 -0700
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> 
> What happens to metastability if I build a FF with something
> really strange like Josephson Junctions?

A Josephson Junction, inherently a latch, will be metastability free, as
will any other quantum device.  It just picks a universe to exist in.

>

Now the other end of the scale.  And, perhaps, back to the continuous
realm.  What's the inherent tau (metastability time constant) of someone
stuck in a moral dilemma? 

Ron Cline

Article: 13923
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: z180@nospam24.com (Peter)
Date: Sat, 02 Jan 1999 21:38:17 GMT
Links: << >>  << T >>  << A >>

>How does the MTBF depend upon the rise time of the signals?

Very strongly. The faster the edges, the less likely it is to happen.

>Are there other interesting parameters that should be considered?

The design of the silicon. Faster gates will hang around in the met.
state for less time. This is the biggest factor by far.

>I'd guess that decay time varies over temp and Vcc the same way
>that prop time does.

I would think only to the extent that the silicon gets faster at low
temp.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.

Article: 13924
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: John Woodgate <jmw@jmwa.demon.co.uk>
Date: Sat, 2 Jan 1999 22:56:01 +0000
Links: << >>  << T >>  << A >>
<368E882A.94671344@swcp.com>, Ron Cline <rcline@swcp.com> wrote:
>What's the inherent tau (metastability time constant) of someone
>stuck in a moral dilemma? 

Well, if they are 'on the horns of a dilemma', I suppose their
metastable equilibrium is likely to be very short or very painful.
-- 
Regards, John Woodgate, Phone +44 (0)1268 747839 Fax +44 (0)1268 777124. 
OOO - Own Opinions Only. You can fool all of the people some of the time, but 
you can't please some of the people any of the time.



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