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Messages from 14025

Article: 14025
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: murray@pa.dec.com (Hal Murray)
Date: 8 Jan 1999 03:25:09 GMT
Links: << >>  << T >>  << A >>

> Someone claims to be developing a 100% metastable-proof FF. Hmmm..,
> since a FF has to make a decision as to whether a signal is above a
> threshhold or below it and the signal can be exactly on the threshold,
> this would seem unlikely. 

It's like the second law of thermo.  There is no way to make a
metastable-proof FF.  Your alarm bells should ring whenever anybody
even hints in that direction.


> Now that I think about it though, perhaps you could use an integrating
> window detector to determine is a signal was anywhwere near threshold
> around the sampling window. If so, the FF's clock enable could be
> disabled. (The delay through the threshold detector could be balanced by
> a fixed delay of the signal to be sampled using speed of light delay).  

That's a typical example of the sort of kludges that people come up
with.  In this case, I think I can find the flaw.

You have just moved the problem.  Remember, you also have to meet
the setup and hold times for the clock enable.  What if the input
signal changes a bit earlier so the clock enable is changing at
the wrong time?



-- 
These are my opinions, not necessarily my employers.

Article: 14026
Subject: Re: How to use Special Pins as IO on Xilinx FPGA???
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Thu, 7 Jan 1999 19:39:31 -0800
Links: << >>  << T >>  << A >>
Instantiate the TDO and connect to the signal you want to be output on that
pin;

TDO rclk(.O (regclkout));   //regclkout uses the TDO pin P181

where rclk is just my name for the instance.

Bruce

asax@my-dejanews.com wrote in message <770t6k$g55$1@nnrp1.dejanews.com>...
>Hi,
>
>Is there anyone who can tell me how to assign a signal to the special pin
on
>Xilinx FPGA. I am using XC4028 device and want to use TDO (special pin) as
an
>output signal in my design. I can not lock this pin using UCF file. Design
is
>in verilog HDL and I am using leonardo for synthesis.
>
>Any help would be greatly appreciated.
>
>--
>Amit Saxena
>MTS
>GDA Tech. Inc
>San Jose, CA
>
>-----------== Posted via Deja News, The Discussion Network ==----------
>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own


Article: 14027
Subject: Re: which FPGA to choose ?
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Thu, 7 Jan 1999 19:50:25 -0800
Links: << >>  << T >>  << A >>
I agree with what I've seen so far, and my simplified spin on it is:

Three major vendors are Xilinx, Altera, Actel.

Xilinx is cool for register based math, where small dual port register files
are useful.

Altera is cool if you need good sized RAM blocks

Actel is cool if you don't want your design to be duplicatable, since there
is not an EEPROM that can just be copied and applied to any blank part.
Also, they have pure static cmos parts that will have very low standby power
consumption.  Actel has a unique internal probing feature that is killer
during debug.

The Xilinx software is pretty tweaky, though.
Altera software is reputed to be the easiest to learn.
Not sure about Actel's latest stuff.

My advice has always been to fit the fpga to the design and suffer through
the software.

Bruce



ekuria01@kepler.poly.edu wrote in message
<76upbd$io7$1@nnrp1.dejanews.com>...
>Hello, I must convert a microcontroller based digital AGC to an FPGA. The
>AGC in question uses relatively simple math (adds, shifts, and Look up
>Tables). I also need to implement digital peak detectors that peak detect
>using and A/D converter.
>
>       I am a novice with FPGAs and my expertiese only extends to micro
coding
>for controllers. Any help on how to choose FPGAs, and what company FPGAs
sound
>apt for my application will be greatly appreciated.
>
>       Thank you all in advance.
>
>Eldho Kuriakose
>
>-----------== Posted via Deja News, The Discussion Network ==----------
>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own


Article: 14028
Subject: Re: fpga socket
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 07 Jan 1999 23:47:04 -0500
Links: << >>  << T >>  << A >>
Sometimes you have to wonder if customers are worth the trouble. Why
can't we just do our design work without them? ... Oh yeah, that money
thing!  ;^)


Ray Andraka wrote:
> 
> Yeah, I got the joke now.  When I first read it, I was a bit bleary-eyed and
> it went right over my head.
> 
> Nice to see others think sockets are the devil's work.  I'm working with a
> customer right now that is insisting on socketing memories and a xilinx.  No
> amount of convincing is changing his mind.  Guess I'll be spending time in the
> lab!
> 
> Rickman wrote:
> 
> > Ray Andraka wrote:
> > >
> > > Chris Eilbeck wrote:
> > >
> > > > > The xilinx is infinitely programmable
> > > >
> > > > I think you must have more patience than me, Ray :)
> > > >
> > >
> > > No, possibly more experience though.  While I've seen people use the
> > > programmability as a crutch to bolster bad design practice, it is not
> > > something I do.  A functional simulation followed by a thorough static
> > > timing analysis leads to a near 100% record of first time successes with
> > > xilinx designs.  I have taken advantage of reconfiguration on many
> > > occasions to do very thorough board testing...100% interconnect and at
> > > speed worst case memory pattern testing that would be difficult any
> > > other way.
> >
> > Ray, I think this was just a joke about the idea of spending the rest of
> > your life programming a Xilinx part "infinitely".   =8^)
> >
> > --
> >
> > Rick Collins
> >
> > redsp@XYusa.net
> >
> > remove the XY to email me.
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Article: 14029
Subject: Re: fpga socket
From: rk <stellare@NOSPAMerols.com>
Date: Fri, 08 Jan 1999 00:55:07 -0500
Links: << >>  << T >>  << A >>
hi,

well, for pqfp and mqfp parts the sockets are less than fun, shall we say,
although sometimes you're just stuck with them, like for test and evaluation
boards, something i have to do often enough.  the clam shell ones seem to offer
the chance to fix things up some, although some (rather unique) requirements keep
pushing me to the open top ones.  'cuss 'em all the time.  soldering the parts to
the board seems to be the way to go as the parts are reliable and just work; i do
that, when possible, for otp devices.

on the other hand, what sort of experience have you had with bga parts?  one
vendor raved about them and showed sockets that looked relatively good.
definitely the parts weren't fragile, like the pqfp's, which are in my opinion a
poster child for ISP.  also, what experience have people had with bga's on pcb's?

thanks,

good evening,

rk

====================

Ray Andraka wrote:

> Yeah, I got the joke now.  When I first read it, I was a bit bleary-eyed and
> it went right over my head.
>
> Nice to see others think sockets are the devil's work.  I'm working with a
> customer right now that is insisting on socketing memories and a xilinx.  No
> amount of convincing is changing his mind.  Guess I'll be spending time in the
> lab!
>
> Rickman wrote:
>
> > Ray Andraka wrote:
> > >
> > > Chris Eilbeck wrote:
> > >
> > > > > The xilinx is infinitely programmable
> > > >
> > > > I think you must have more patience than me, Ray :)
> > > >
> > >
> > > No, possibly more experience though.  While I've seen people use the
> > > programmability as a crutch to bolster bad design practice, it is not
> > > something I do.  A functional simulation followed by a thorough static
> > > timing analysis leads to a near 100% record of first time successes with
> > > xilinx designs.  I have taken advantage of reconfiguration on many
> > > occasions to do very thorough board testing...100% interconnect and at
> > > speed worst case memory pattern testing that would be difficult any
> > > other way.
> >
> > Ray, I think this was just a joke about the idea of spending the rest of
> > your life programming a Xilinx part "infinitely".   =8^)
> >
> > --
> >
> > Rick Collins
> >
> > redsp@XYusa.net
> >
> > remove the XY to email me.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka



Article: 14030
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: rk <stellare@NOSPAMerols.com>
Date: Fri, 08 Jan 1999 01:00:19 -0500
Links: << >>  << T >>  << A >>
Brad Taylor wrote:

> I know,  I'm sure you are right about this, but I can't help trying!

me neither; tried to beat it for quite a while, schemes like multiple flip-flops
w/ voting, window detectors, different thresholds w/ comparators, on and on and
on.  always just seems to move the problem.

btw, a looooooooong time ago, played a practical joke w/ perpetual motion
machine on the boss, he went around explaining how it worked, then he found out
the trick (a little battery in the base :), no raise that year.

good night!

rk

---------------------------------------------------------------


>  I
> guess I shouldn't speculate in so public a forum. At least there is
> someone around to catch it. There is another flaw, since the
> "integrating" window detector has to detect a transition near threshold
> and then remember that for say a few ns, it is in effect a sampling
> system which can go metastable.  If the Clock enable's value is
> undefined, the FF cannot work of course.
>
> So we have speed of light, law of gravity, time travel, perpetual motion
> and metastable free sampling.  I might also add Rob's law of hardware
> which states that you cannot install and configure a PC add-in card
> without losing a day.
>
> Best Wishes,
> Brad
>
> Hal Murray wrote:
> >
> > > Someone claims to be developing a 100% metastable-proof FF. Hmmm..,
> > > since a FF has to make a decision as to whether a signal is above a
> > > threshhold or below it and the signal can be exactly on the threshold,
> > > this would seem unlikely.
> >
> > It's like the second law of thermo.  There is no way to make a
> > metastable-proof FF.  Your alarm bells should ring whenever anybody
> > even hints in that direction.
> >
> > > Now that I think about it though, perhaps you could use an integrating
> > > window detector to determine is a signal was anywhwere near threshold
> > > around the sampling window. If so, the FF's clock enable could be
> > > disabled. (The delay through the threshold detector could be balanced by
> > > a fixed delay of the signal to be sampled using speed of light delay).
> >
> > That's a typical example of the sort of kludges that people come up
> > with.  In this case, I think I can find the flaw.
> >
> > You have just moved the problem.  Remember, you also have to meet
> > the setup and hold times for the clock enable.  What if the input
> > signal changes a bit earlier so the clock enable is changing at
> > the wrong time?
> >
> > --
> > These are my opinions, not necessarily my employers.



Article: 14031
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: rk <stellare@NOSPAMerols.com>
Date: Fri, 08 Jan 1999 01:08:46 -0500
Links: << >>  << T >>  << A >>
Roy McCammon wrote:

> rk wrote:
> > EVERY CIRCUIT IS CONSIDERED GUILTY UNTIL PROVEN INNOCENT!
>
> Nice in pricipal, but very difficult to apply
> in practice.

yeah, difficult, but if you take that philosophy, barto's law, things tend to work
at power-on. i've also seen a lot of development schedules where key milestone is
getting electrons on the board; most of the time, in my opinion,  effort is more
valuable up front doing the design/analysis/simulations and i use as my design speed
metric "time to working system" rather than the "time to board built" which is often
more popular.

i think we've all seen in the old days guys who design with the soldering irons.
now they do it with the parts burner or the reprogrammable fpga.  my designs are
mostly OTPs, cqfp, soldered to the board.  in general, zero defects is a good goal,
and is very achievable.

note that the law was quoted w.r.t. a gentleman who took the approach, test it and
see if it's ok.  if not ...  of course i've seen a ton of designers fail miserably
with that approach.  usually subtle timing problems that appear randomly with
different place and routes, over environmental temp test, or when a new lot of parts
is procured.  in every one of those cases where i was called in to troubleshoot, the
timing analysis was either not done or incorrectly done.

good night!

rk

Article: 14032
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: John Woodgate <jmw@jmwa.demon.co.uk>
Date: Fri, 8 Jan 1999 09:34:28 +0000
Links: << >>  << T >>  << A >>
<w05ogoaswm3.fsf@ash.comlab>, Jamie Lokier <spamfilter.dec1998@tantaloph
ile.demon.co.uk> wrote, having noted that I prefer NOT to receive an e-
mail copy:
>I don't know if it's possible to construct a device that guarantees a
>metastability time limit.  I am not convinced by the hand-waving
>arguments around here that say it's impossible -- but the maths is not
>simple. 

AIUI, one form of metastability involves the two active devices in a
flip-flop being 'on' together. This is analogous to a balanced see-saw.
There have been many crazy patents on non-balanceable see-saws or
analogues thereof, detecting the balanced condition by some means and
'tipping the balance'. IIRC, it can't be done without an external energy
source (which could, of course, have been stored from previous see-
sawing). In the same way, a very fast AND gate, with curious logic
levels, could detect the 'both on' condition and correct it, but the
latency of the AND gate still alows the condition to persist for a
(maybe very) short time.
-- 
Regards, John Woodgate, Phone +44 (0)1268 747839 Fax +44 (0)1268 777124. 
OOO - Own Opinions Only. ERROR! OUT OF CORNFLAKES. Please check cereal port 
configuration.

Article: 14033
Subject: Re: =?iso-8859-1?Q?G=F6mmer=20gris=F6ron=2E=2E=2E?=
From: Joachim Strombergson <emwchim@emw.ericsson.se>
Date: Fri, 08 Jan 1999 12:11:36 +0100
Links: << >>  << T >>  << A >>
Tja!

Magnus Homann wrote:
> thor@sm.luth.se (Jonas Thor) writes:
> =

> > Hej!
> >
> > Jag har uppt=E4ckt ett lustigt beteende hos min 1 =E5rige
> > (groenendal/collie/border collie). Han =E4lskar gris=F6ron, men n=E4r=
 han =E4r
> > m=E4tt s=E5 g=F6mmer han =F6ronen (grisens =F6ron ...). Han b=E4ddar =
in de i sin
> > s=E4ng, trycker in de mellan kuddarna i soffan, g=F6mmer bakom bokhyl=
lan
> > osv.
> >
> > Jag antar att han beter sig som ekorren och bunkrar upp sin mat. =C4r=

> > detta beteende vanligt hos hundar? Det =E4r min f=F6rsta hund, s=E5 j=
ag har
> > inte sett detta bettende f=F6rut.
> >
> > God fors=E4ttning p=E5 det nya =E5ret!
> =

> Nja, jag tycker att du skall anv=E4nda en PLD. Ta tex de senaste Lattic=
e
> 2032VE, den har bara fyra nanoskeunders f=F6rdr=F6jning. P=E5 s=E5 s=E4=
tt tj=E4nar
> man en klockcykel. Akta dig f=F6r metastabilitet, bara!

Jag skulle snarare gissa att Collien liksom vi andra sett p=E5 tok f=F6r
m=E5nga "productivity gap"-slides det senaste =E5ret och nu =E4gnar sig =E5=
t
"reuse" av =F6ron. Intressant att notera =E4r =E4ven att samma =F6ron b=E5=
de
fungerar i soffa s=E5v=E4l som bakom bokhylla. =D6ron verkar mao vara h=F6=
gst
rekonfigurerbara... :-)

(Lycka till med hunden iaf. Vi h=F6res.)
-- =

Med v=E4nlig h=E4lsning, Yours

Joachim Str=F6mbergson - Alltid i harmonisk sv=E4ngning
---------------- Ericsson Microwave Systems AB -----------------
Joachim Str=F6mbergson            http://www.ericsson.se/microwave
     ASIC System on Silicon engineer, nice to CUTE animals.    =

* Opinions above, expressed or implicit, are strictly personal *
------------- Spamfodder: regeringen@regeringen.se -------------

Article: 14034
Subject: Re: 22V10 Metastability - help please
From: murray@pa.dec.com (Hal Murray)
Date: 8 Jan 1999 12:08:19 GMT
Links: << >>  << T >>  << A >>

What do people designing safety critical systems do about
metastability?

I'd guess that they make a list of all the places where
signals cross clock domains and check each one carefully.

Where do they get recovery time data to backup their calculations?
I haven't seen anything but typicals from vendors, and that's all
been in ap-notes rather than data sheets.


-- 
These are my opinions, not necessarily my employers.

Article: 14035
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10
From: Dan Prysby <dprysby1@email.mot.com>
Date: Fri, 08 Jan 1999 09:31:48 -0600
Links: << >>  << T >>  << A >>
Brad Taylor wrote:
> 
> Someone claims to be developing a 100% metastable-proof FF. Hmmm..,
> since a FF has to make a decision as to whether a signal is above a
> threshhold or below it and the signal can be exactly on the threshold,
> this would seem unlikely.

So if a combination of 3 FFs sample 1 signal close enough in time
and each has a different threshold by design, then only 1 will go
metastable. Just a supposition.

Dan

Article: 14036
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: notjimbob@worldnet.att.net (James Meyer)
Date: 8 Jan 1999 16:16:12 GMT
Links: << >>  << T >>  << A >>
On 8 Jan 1999 03:25:09 GMT, murray@pa.dec.com (Hal Murray) wrote:

>
>> Someone claims to be developing a 100% metastable-proof FF. Hmmm..,
>> since a FF has to make a decision as to whether a signal is above a
>> threshhold or below it and the signal can be exactly on the threshold,
>> this would seem unlikely. 
>
>It's like the second law of thermo.  There is no way to make a
>metastable-proof FF.  Your alarm bells should ring whenever anybody
>even hints in that direction.

	The laws of thermodynamics are true only for closed systems.
Closed systems cannot have any energy added from the outside.

	Flip-flops are *not* closed systems because energy can be
added from outside the flip-flop.  Vcc, remember?

	Flip-flops are not closed systems and that means that they do
not have to conform the the laws of thermodynamics.

	You need to use another analogy.

	Jim

Article: 14037
Subject: Re: fpga socket
From: John Larkin <jjlarkin@worldnet.att.net>
Date: 8 Jan 1999 16:39:39 GMT
Links: << >>  << T >>  << A >>
Brad,

same experience here. We did an Actel design and used a couple of $120
surfmount sockets. They soldered onto the board as huge short-circuited
blobs, and never worked. We subsequently resoldered one chip NINE times,
directly to the same pads. I am in awe of the production people who
managed to do this. We fired the engineer.

John




Brad Taylor wrote:
> 
> Bob Sefton wrote:
> >
> > I used them on a project 5-6 years ago before ISP was built into
> > Altera CPLDs. The sockets were an absolute nightmare. I ended up
> > ripping off the sockets and soldering the 160-pin and 208-pin QFP
> > parts directly to the board. If a part needed to be reprogrammed
> > we had to unsolder it and replace it with a new programmed part.
> > This was expensive, and after a couple of times on the same part
> > you start to lift pads off the board, but it was inifinitely
> > better than dealing with the sockets.
> >
> 
> There is really nothing wrong with occasional desoldering if the pads
> don't lift. As I recall using the better grades of epoxy-fiberglass or
> polyamide will eliminate the lifted pads. You do need to find a good
> experienced re-work shop though.
> 
> -
> Brad
> 
> > Bob S.
> >
> > schaltung@hotmail.com wrote:
> > >
> > > Hi!
> > >
> > > Has anyone had any good or bad experience using a socket for a XILINX 160-PIN
> > > PQFP?
> > >
> > > I think I found one in ALLIED Catalog that could work. any suggestion?
> > >
> > > Antonio Moreno
> > > schaltung@hotmail.com
> > >
> > > -----------== Posted via Deja News, The Discussion Network ==----------
> > > http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own
> 
> --
> 
>     ---------------------------------------------------------------
> 
>                                 Name: blt.vcf
>               Part 1.2          Type: text/x-vcard
>                             Encoding: 7bit
>                          Description: Card for Brad Taylor

-- 

********************************************************************h

John Larkin, President            phone 415 753-5814   fax 753-3301
Highland Technology, Inc
320 Judah Street                          jjlarkin@worldnet.att.net
San Francisco, CA 94122           http://www.highlandtechnology.com

Article: 14038
Subject: 68K synthesizable core
From: Todd Kline <todd@wgate.com>
Date: Fri, 08 Jan 1999 12:55:28 -0500
Links: << >>  << T >>  << A >>
Greetings,

Has anyone in the group come across a 68000 synthesizable core in either
VHDL or Verilog.  Motorola has only hard macros which are no help at
all.

Thanks in advance,
Todd

Article: 14039
Subject: Field Applications Engineers: ASIC/Field Programable Gate Arrays
From: Monica Schnitger <monicaschnitger@earthlink.net>
Date: Fri, 08 Jan 1999 13:30:58 -0500
Links: << >>  << T >>  << A >>
Experienced people are needed in the Boston, Raleigh NC, Trenton NJ,
Ottawa and Toronto Canada.  My client is a world leader in this fast
past world. Excellent product, and futures plus Customer pull has
recently opened these opportunities. My client wants only the
experienced and proven with at least 3+ years . . .  and is willing to
pay for that. If you can provide comprehensive customer technical
support throughout pre-sales, post sales, device and tool selection
through customer circuit evaluation and systems design, coupled with the
ability to do competitive analysis you are on your way. If you can
support both sales and customers in technical presentations, design
reviews, do demos on workstations and PC platforms and train those damn
distributors to be self sufficient you are golden. But first, apart from
just 3+ years experience you will need to have BSEE or better. Love
bleeding edge logic and systems design. Ooooze in application experience
and/or exposure to the leading competitors in this field. Have a very
strong background in CAE design tools, excellent communications and
customers interface skills could put you to work in two weeks if you are
looking for change.

Four week Training BOOT CAMP for those selected.

Please email responses only. Cover letter and CV/Resumes should be sent
to  monica@DevlinSearchGroup.inc

Article: 14040
Subject: NEW ENGINEERING PAGE: Please Visit
From: metad@globalnet.co.uk (Scott Paul Johnston)
Date: Fri, 08 Jan 1999 18:40:36 GMT
Links: << >>  << T >>  << A >>
Please visit and comment on my Electronics and Electrical Engineering
pages located at:

http://www.users.globalnet.co.uk/~metad/eee.htm

Containing:
Introduction to EEE
Resources (over 100 web links)
Employment Statistics and newspaper excerpts
Engineering Poems, Quotations and Jokes
EEE at Glasgow University

In addition my homepage (http://www.users.globalnet.co.uk/~metad/)
contains:

A section about me
My CV
A James Bond Section
A guestbook
Humour
500+ cool links in the "new look" bookpage
Cool background MIDI and graphics
Literary quotations
Photo Album
Student Resources
Awards Page
Poems...

Basically, something for everyone!

PLEASE VISIT VIA MY MAIN HOMEPAGE ADDRESS!

Please send you comments via the guestbook or by Email (containing
your full name and Email and webpage addresses) and visit via
http://www.users.globalnet.co.uk/~metad/.

Thanks
Scott Johnston
metad@globalnet.co.uk   

Article: 14041
Subject: Re: Field Applications Engineers: ASIC/Field Programable Gate Arrays
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 08 Jan 1999 12:07:25 -0800
Links: << >>  << T >>  << A >>
Monica Schnitger wrote:

> <snip>  My client is a world leader in this fast
> past world.

Who wants to work for the leader in the "past world" ?I
rather work for the leader in the future world...

Peter Alfke, speaking for himself

Article: 14042
Subject: Re: Field Applications Engineers: ASIC/Field Programable Gate Arrays
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 08 Jan 1999 21:38:17 +0100
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> writes:

> Monica Schnitger wrote:
> 
> > <snip>  My client is a world leader in this fast
> > past world.
> 
> Who wants to work for the leader in the "past world" ?I
> rather work for the leader in the future world...

Me too! :-) Maybe she meant "paced"?

Homann
-- 
   Magnus Homann  Email: d0asta@dtek.chalmers.se
                  URL  : http://www.dtek.chalmers.se/DCIG/d0asta.html
  The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html

Article: 14043
Subject: Anyone have an Altera LP6 interface card FS?
From: Randall Logan <drlogan@netcom.ca>
Date: Fri, 08 Jan 1999 13:03:46 -0800
Links: << >>  << T >>  << A >>
I recently purchased an Altera MPU PLAD3-12 device program adaptor but
it came without the LP6 PC interface card..... anyone out there have an
LP6 card they can part with?  Let me know your asking price.

Thanks.

Randall Logan
drlogan@netcom.ca

Article: 14044
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 9 Jan 1999 00:21:03 GMT
Links: << >>  << T >>  << A >>
z80@ds2.com (Peter) writes:
>Why would adding noise increase the chance of it happening? I am
>talking about noise whose spectrum is *below* that of the frequency
>response of the feedback loop of the latch in question.

>I think adding noise will **not change** the MS behaviour, and
>depending on how the noise is made up it might even put an upper limit
>on it, e.g. a square wave at 100MHz, injected into the feedback loop,
>ought to set an upper limit on the metastable condition of 5ns.

This was explained to me once in the context of balancing a pencil on
its point.  The best way was to have it slightly off balance, and let the
first fluctuation (probably Brownian motion from air) balance it.

I agree, it is not obvious.

-- glen

Article: 14045
Subject: I2C core
From: "saffary" <saffary@club-internet.fr>
Date: Sat, 9 Jan 1999 01:46:20 +0100
Links: << >>  << T >>  << A >>
Anyone know where I can find i2c VHDL core.

thank.


Article: 14046
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: z80@ds2.com (Peter)
Date: Sat, 09 Jan 1999 07:44:05 GMT
Links: << >>  << T >>  << A >>

I fully agree that an externally injected sginal will not avoid the
*onset* of metastability, but I cannot see why it could not be used to
set an upper limit on the duration.

Say you inject a 100MHz square wave into the feedback loop, of
sufficient amplitude. How can this possibly *not* flip the latch out
of the MS state, within 5ns?

>>I think adding noise will **not change** the MS behaviour, and
>>depending on how the noise is made up it might even put an upper limit
>>on it, e.g. a square wave at 100MHz, injected into the feedback loop,
>>ought to set an upper limit on the metastable condition of 5ns.
>
>This was explained to me once in the context of balancing a pencil on
>its point.  The best way was to have it slightly off balance, and let the
>first fluctuation (probably Brownian motion from air) balance it.
>
>I agree, it is not obvious.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.

Article: 14047
Subject: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: John Woodgate <jmw@jmwa.demon.co.uk>
Date: Sat, 9 Jan 1999 13:43:47 +0000
Links: << >>  << T >>  << A >>
<369624E4.77DF2D7D@email.mot.com>, Dan Prysby <dprysby1@email.mot.com>
wrote, having noted that I prefer NOT to receive an e-mail copy:
>Brad Taylor wrote:
>> 
>> Someone claims to be developing a 100% metastable-proof FF. Hmmm..,
>> since a FF has to make a decision as to whether a signal is above a
>> threshhold or below it and the signal can be exactly on the threshold,
>> this would seem unlikely.
>
>So if a combination of 3 FFs sample 1 signal close enough in time
>and each has a different threshold by design, then only 1 will go
>metastable. Just a supposition.
>
>Dan

There is a very interesting article in 'New Scientist' this week (issue
2168: go to http://www.newscientist.com), headed 'Glorious noise'. The
article has been 'dumbed down' rather too much, but basically, it
recounts recent discoveries about the effects of noise on non-linear
systems, and indicates that under some circumstances noise *can*
differentially influence the behaviour of bistable systems.
Superficially, it does seem to suggest that the addition of noise to a
system could eliminate metastable states.
-- 
Regards, John Woodgate, Phone +44 (0)1268 747839 Fax +44 (0)1268 777124. 
OOO - Own Opinions Only. ERROR! OUT OF CORNFLAKES. Please check cereal port 
configuration.

Article: 14048
Subject: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 09 Jan 1999 16:31:02 +0100
Links: << >>  << T >>  << A >>
z80@ds2.com (Peter) writes:

> I fully agree that an externally injected sginal will not avoid the
> *onset* of metastability, but I cannot see why it could not be used to
> set an upper limit on the duration.
> 
> Say you inject a 100MHz square wave into the feedback loop, of
> sufficient amplitude. How can this possibly *not* flip the latch out
> of the MS state, within 5ns?

It it was in exactly a metastable position. What if it was on its way
to one of the stable states, but then got pushed back to MS state?

At least, that's my theory... :-)

Homann
-- 
   Magnus Homann  Email: d0asta@dtek.chalmers.se
                  URL  : http://www.dtek.chalmers.se/DCIG/d0asta.html
  The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html

Article: 14049
Subject: FPGA Eng WANTED : excellent opportunity
From: mdelaney@servtech.com (Mike DeLaney )
Date: Sat, 09 Jan 1999 11:51:38 -0500
Links: << >>  << T >>  << A >>
TITLE: FPGA Eng
   
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