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Messages from 14100

Article: 14100
Subject: Orcad Express Plus vs Foundation Express
From: "Pawel Michocki" <pawelm@sim.com.pl>
Date: Wed, 13 Jan 1999 15:36:13 GMT
Links: << >>  << T >>  << A >>
Does anyone use Orcad Express Plus v9.0 ?
Now I use Orcad Express 7.20 with Xilinx Aliance 1.5, but Orcad won't
provide
support for virtex in Express (only in Express Plus). Is it worth to upgrade
to Plus
version or simply buy Foundation from Xilinx ?
Any other suggestion ?

Regards,
Pawel Michocki, SIM POLAND


PS
Any satisfied Orcad user ? (not from USA)


Article: 14101
Subject: Re: Orcad Express Plus vs Foundation Express
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 13 Jan 1999 11:23:57 -0500
Links: << >>  << T >>  << A >>
Pawel Michocki wrote:
> 
> Does anyone use Orcad Express Plus v9.0 ?
> Now I use Orcad Express 7.20 with Xilinx Aliance 1.5, but Orcad won't
> provide
> support for virtex in Express (only in Express Plus). Is it worth to upgrade
> to Plus
> version or simply buy Foundation from Xilinx ?
> Any other suggestion ?
> 
> Regards,
> Pawel Michocki, SIM POLAND
> 
> PS
> Any satisfied Orcad user ? (not from USA)

Hi Pawel,

I started a project last year using Orcad Express 7.2. I don't think
they had a "Plus" version back then. After taking the 5 day training
course I convinced myself that I should try using VHDL for my design. I
did some work is a small section of the design and decided to proceed
with VHDL. Once I had much of my design entered and implemented, the
VHDL tools started behaving badly. I had numerous problems with crashes
(due to constructs in my code that the compiler or simulator didn't
like). The support was not adequate. I finally abandoned Orcad for
Xilinx Foundation. I get much better support and although the Foundation
Express compiler has its problems, I always seem to be able to get my
work done. 

I have received my copy of Orcad Express Plus v9.0, but have not even
put it on my machine. After posting my story a few times in this
newsgroup I even received an email from someone at Orcad asking me to
give the new version a try. But when I wrote back asking for specifics
about which problems had been fixed, I never received a reply. So the
Orcad box still sits on my shelf (or is it on the floor beside the trash
can?). Unfortunately I can't, at this point, fully evaluate the SW if I
wanted to. We converted our Alliance license to a Foundation license and
I no longer have the libraries for Orcad (??unless they come on the
Orcad CD??). 

If you are using VHDL for your design, I would say to drop Orcad like a
hot potato(e). If you have had different results, please let me know. 

P.S. I once asked through this newsgroup, for anyone using Orcad doing
FPGA work to let me know of their success. I got no replies. I repeat
the request. 

***************************************************************************************** 
If anyone out there is using Orcad successfully for FPGA design, please
post your results.
***************************************************************************************** 


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Article: 14102
Subject: EDTN Tech Note
From: "mdisman" <mdisman@ix.netcom.com>
Date: 13 Jan 1999 16:43:44 GMT
Links: << >>  << T >>  << A >>
The latest Tech Note posted on EDTN's PLD Design Center discusses how
reconfigurable computing can be used to accelerate Adobe's desk-top
publishing software.  Check under Tech Notes at
http://www.edtn.com/pld

Murray Disman
Editor
PLD Design Center 

Article: 14103
Subject: Re: Problems with processes
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Wed, 13 Jan 1999 10:08:43 -0700
Links: << >>  << T >>  << A >>
Jim King wrote in message <77hrrt$gvu$1@trog.dra.hmg.gb>...
>
>Jeffrey L. Madden wrote in message <369B642A.843BCDF1@iupui.edu>...
>>I am using FPGA Express with Foundation Series 1.4 to implement VHDL
>>code. I have been coming accross problems when using processes in my
>>code and I usually receive a warning that the output of the cell is
>>constant. This causes the cell to be eliminated when it is optimized. I
>>am using the student edition of this software if it makes any
>>difference. Here is a simple VHDL program that this error occurs with...
>>
>>*****************************************
>>library IEEE;
>>use IEEE.std_logic_1164.all;
>>entity dff is
>>    port(D:in std_logic;
>>        CLK:in std_logic;
>>        CLEAR:in std_logic;
>>        Q:out std_logic);
>>end dff;
>>
>>architecture dff1 of dff is
>>    signal V: std_logic;
>>begin
>>    process(CLK, CLEAR)
>>    begin
>>        if CLEAR = '1' then
>>            V <= '0';
>>        elsif (CLK = '1' and CLK'event) then
>>            V <= D;
>>        end if;
>>    end process;
>>    Q <= V;
>>end dff1;
>>**************************************************


>I think it might have to do with the way you test for the clock edge.  I
use
>Express as well, and it is a bit picky about how the async clear and the
>clock edge are tested for.  Try this:
>
>process (clk, clear)
>begin
>if clear = '1' then
>    V <= '0';
>else
>    if (clk = '1' and clk'event) then
>        V <= D;
>    end if;
>end if;
>end process;


Actually, Jeffery's code (the original version above) is the "correct" way
to implement a FF with an async clear.  I've never tried it the other way.
I'm sure it would simulate correctly but I don't know what Synopsys will do
with it.

>Something else:  is there a particular reason that you have the signal V?
>Can't you simply assign D to Q within the process?


That's the better question!  The intermediate signal V is not needed.

--
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

"In the beginning, there was darkness.  And it was without form, and void.
And there was also me!"
-- Bomb #20, John Carpenter's "Dark Star"



Article: 14104
Subject: System reset
From: "Phichai Liangtong" <phichai@loxinfo.co.th>
Date: Thu, 14 Jan 1999 01:06:46 +0700
Links: << >>  << T >>  << A >>
I designed a microprocessor and it finished.
I test it by connect interface to computer (use PC as
a I/O and memory) and it work but it has some problem.
when it running (my microprocessor), the system will
reset itself (FPGA) and the program is re-run from startup
again. This reset signal didn't occur by my reset signal
and this signal occur sometime.

I don't understand and how to solve it.


Article: 14105
Subject: Re: Orcad Express Plus vs Foundation Express
From: "Steve" <reply.through.newsgroup@paranoid.com>
Date: Wed, 13 Jan 1999 18:44:55 GMT
Links: << >>  << T >>  << A >>
I used Express up to 7.20, but only for simulation.  The synthesis
had too many problems.  I use Foundation for synthesis, and it
works fine.  It's a great deal if you can get by with the
Base-VHDL version.  (Limited size and no constraints editor.)

The FPGA Express version always lags the latest available
from Synopsis, but I can live with that for the price.


Steve

Pawel Michocki wrote in message ...
>Does anyone use Orcad Express Plus v9.0 ?
>Now I use Orcad Express 7.20 with Xilinx Aliance 1.5, but Orcad won't
>provide
>support for virtex in Express (only in Express Plus). Is it worth to
upgrade
>to Plus
>version or simply buy Foundation from Xilinx ?
>Any other suggestion ?
>
>Regards,
>Pawel Michocki, SIM POLAND
>
>
>PS
>Any satisfied Orcad user ? (not from USA)
>
>


Article: 14106
Subject: Re: Orcad Express Plus vs Foundation Express
From: "pawelm" <pawelm@sim.com.pl>
Date: Wed, 13 Jan 1999 22:15:46 +0100
Links: << >>  << T >>  << A >>
>Pawel Michocki wrote:
>>
>> Does anyone use Orcad Express Plus v9.0 ?
>> Now I use Orcad Express 7.20 with Xilinx Aliance 1.5, but Orcad won't
>> provide
>> support for virtex in Express (only in Express Plus). Is it worth to
upgrade
>> to Plus
>> version or simply buy Foundation from Xilinx ?
>> Any other suggestion ?
>>
>> Regards,
>> Pawel Michocki, SIM POLAND
>>
>> PS
>> Any satisfied Orcad user ? (not from USA)
>
>Hi Pawel,
>
>I started a project last year using Orcad Express 7.2. I don't think
>they had a "Plus" version back then. After taking the 5 day training
>course I convinced myself that I should try using VHDL for my design. I
>did some work is a small section of the design and decided to proceed
>with VHDL. Once I had much of my design entered and implemented, the
>VHDL tools started behaving badly. I had numerous problems with crashes
>(due to constructs in my code that the compiler or simulator didn't
>like). The support was not adequate. I finally abandoned Orcad for
>Xilinx Foundation. I get much better support and although the Foundation
>Express compiler has its problems, I always seem to be able to get my
>work done.
>
>I have received my copy of Orcad Express Plus v9.0, but have not even
>put it on my machine. After posting my story a few times in this
>newsgroup I even received an email from someone at Orcad asking me to
>give the new version a try. But when I wrote back asking for specifics
>about which problems had been fixed, I never received a reply. So the
>Orcad box still sits on my shelf (or is it on the floor beside the trash
>can?). Unfortunately I can't, at this point, fully evaluate the SW if I
>wanted to. We converted our Alliance license to a Foundation license and
>I no longer have the libraries for Orcad (??unless they come on the
>Orcad CD??).
>
>If you are using VHDL for your design, I would say to drop Orcad like a
>hot potato(e). If you have had different results, please let me know.
>
>P.S. I once asked through this newsgroup, for anyone using Orcad doing
>FPGA work to let me know of their success. I got no replies. I repeat
>the request.
>
>***************************************************************************
**************
>If anyone out there is using Orcad successfully for FPGA design, please
>post your results.
>***************************************************************************
**************
>
>
>--
>
>Rick Collins
>
>redsp@XYusa.net
>
>remove the XY to email me.

Hi,

I'm still hesitating - all my projects were made using Orcad software, but
I'm really tired of their "support". As "non USA customer" I can't
access  ODN, thay never have valid registered numbers database - so because
of stupid "support machine" I was able to use it maybe 2 or 3 times during
last 2 years (only their local dealer is o.k. :)  ).
But as I can see it isn't only my problem.
About "using Orcad doing FPGA work":
Most of my projects  (9500,3x00, 5200, 4000E and Spartan) are
schematic-based. I started to use VHDL after problems with transfering net
properties from schematic to edif. Yes, I had problems
with VHDL too - Orcad should work on error reports - but I managed to
resolve my problems myself (I had to - because of their "support").
The problem is I really know this software now and it's difficult to change
it. Is it worth ?

Regards,
Pawel

PS
I have Foundation Base M1.4, but I've never tried to use it. Are any
significant differences between 1.4 and 1.5  ?


Article: 14107
Subject: Programmng ALTERA EPROMS
From: "Jason Pattison" <jason.pattison@xtra.co.nz>
Date: Thu, 14 Jan 1999 10:18:53 +1300
Links: << >>  << T >>  << A >>
Does anyone know how to program the ALTERA FLEX configuration EPROMS via the
byte blaster cable without purchasing the proper programming hardware????

Schematics or programming voltage levels / timing diagrams would be helpful.

Thanks in advance
JASON


Article: 14108
Subject: Re: Orcad Express Plus vs Foundation Express
From: "Gregory C. Read" <xxxgread@voicenet.com>
Date: Wed, 13 Jan 1999 17:13:16 -0500
Links: << >>  << T >>  << A >>
I have used Orcad Express for several Actel designs and have been quite
happy. However, they were all schematic based with no VHDL.

--
Greg
xxxgread@voicenet.com
(Remove the 'xxx' to send Email)


Rickman wrote in message <369CC89D.191C7613@yahoo.com>...
>P.S. I once asked through this newsgroup, for anyone using Orcad doing
>FPGA work to let me know of their success. I got no replies. I repeat
>the request.
>
>***************************************************************************
**************
>If anyone out there is using Orcad successfully for FPGA design, please
>post your results.
>***************************************************************************
**************
>
>
>--
>
>Rick Collins
>
>redsp@XYusa.net
>
>remove the XY to email me.


Article: 14109
Subject: ASIC/FPGA H/W ENGINEERS ASAP!!!!
From: "Donna Vance" <dmvance@ix.netcom.com>
Date: Wed, 13 Jan 1999 14:45:10 -0800
Links: << >>  << T >>  << A >>
Please contact and send resume to:
Donna Vance
donna@ki-tech.com
650-372-0858

Hardware Engineer
REQ. 1216
San Jose, CA
Responsibilities:
FPGA/ board/ system architecture and design.
Simulation of high - speed digital signals.
System clock distribution, system power distribution and engineering test
development.
Interfacing to customerís circuitry.
New technology evaluation.
Requirements:
BSEE or MSEE with 6 months to 3 years of related experience.
Excel in logic design.
Enjoy hands-on work in the lab.
Strong oral and written communication skills.
Desire to learn how to design large, complex real-time systems.
FPGA, JTAG, SPICE and embedded systems experience are a plus.

Hardware Engineer
REQ. 1750
San Jose, CA
Responsibilities:
FPGA/ board/ system architecture and design.
Simulation of high - speed digital signals.
System clock distribution, system power distribution and engineering test
development.
Interfacing to customer's circuitry.
New technology evaluation.
Requirements:
BSEE or MSEE with 6 months to 3 years of related experience.
Excel in logic design.
Enjoy hands-on work in the lab.
Strong oral and written communication skills.
Desire to learn how to design large, complex real-time systems.
FPGA, JTAG, SPICE and embedded systems experience are a plus.

NORTHERN CALIFORNIA
SENIOR DESIGN VERIFICATION ENGINEER
Requisition #SC001
Location of position Santa Clara California
Responsibilities:
Write tests and test automation tools to verify microprocessor design logic
functionality.
Requirements:
BS/MS/Ph.D. in Electrical Engineering or Computer Science with 2+ years of
relevant experience.  Should have high level programming expertise using
C/C++ and shell scripts (Perl/ UNIX Shell).  Should be familiar with
assembly language programming and have knowledge of microprocessor
architecture and RISC principles.

DESIGN VERIFICATION ENGINEER
Requisition #SC002
Location of position Santa Clara California
Responsibilities:
Write tests and test automation tools to verify microprocessor design logic
functionality. Requirements:
BS/MS/Ph.D. in Electrical Engineering or Computer Science.
Should have high level programming expertise using C/C++ and shell scripts
(Perl/ UNIX Shell).  Should be familiar with assembly language programming.
2+ years of relevant experience is a definite plus.

CIRCUIT DESIGN ENGINEER
Requisition #SC003
Location of position Santa Clara California
Responsibilities:
Circuit design of high performance, embedded microprocessor blocks.
Requirements:
BS/MS/Ph.D. in Electrical Engineering or Computer Science and 3+ years
microprocessor design experience.  Experience with major functional blocks,
such as integer, register files, floating point, TLB or cache is preferred.
Must have worked with designs from start to finish. Requires an
understanding of sub-micron CMOS process technology and high-frequency
design techniques and the ability to make cost/speed/power optimization
trade-off decisions.

LOGIC DESIGN ENGINEER
Requisition #SC004
Location of position Santa Clara California
Responsibilities:
Will perform logic design tasks, to include micro-architecture definition,
RTL descriptions, simulation, timing analysis and synthesis of advanced
microprocessor designs. Use Verilog, Synopsys and full custom design flows.
Interface with custom circuit designers.
Requirements:
BS/MSEE and 2+ or 5+ years microprocessor design experience. Experience with
designs from start to finish is desired.  Prefer experience with Verilog,
Synopsys and related industry design  tools.

SENIOR CAD ENGINEERS
Requisition #SC005
Location of position Santa Clara California
Responsibilities:
As a visionary CAD Engineer, you will assume a leadership position for
developing new front-end and back-end CAD flows and tools for porting
silicon intellectual properties to various processes.
Requirements:
MS/Ph.D. EE or CS with 3+ years front-end and back-end experience with block
place and route tools, automatic layout generation and process migration,
GDT, CASCADE, IC Station (or any silicon compiler), module generation tools
or symbolic layout and compaction.

SENIOR CAD ENGINEER - Place and Route
Requisition #SC006
Location of position Santa Clara California
Responsibilities:
Will develop and support CAD flows for the next generation of high
performance MIPS microprocessors.  As a visionary CAD Engineer, you will
assume a leadership position for developing new CAD flows and tools for
porting silicon intellectual properties to various processes.
Requirements:
MS/Ph.D. EE or CS with 3+ years VLSI full custom design experience with
block place and route tools (SILICON ENSEMBLE, AVANT!/APOLLO).  Also
requires experience with SKILL, PERL, SHELL, and C.

FRONT-END CAD ENGINEER
Requisition #SC007
Location of position Santa Clara California
Responsibilities:
Front-End CAD Engineer, developing and supporting CAD flows for the next
generation of high performance MIPS microprocessors.  Will be responsible
for one or many of these areas: Logic simulation, Spice simulation,
schematic capture, netlisting, synthesis, timing, design for test, place and
route.
Requirements:
BS/MSCS or EE and 3+ yearís relevant experience.  Familiarity with VLSI full
and semi custom design flows. Programming proficiency: desire Perl or
equivalent, Cadence Skill language, Verilog. C and C++ are optional.
Experience in CAD flows development and scripting.  A working knowledge in
many of the following areas:
Schematic capture environment
 - Cadence Composer & DFII frame work Logic simulation
- Verilog ,VCS preferably Synthesis
- Synopsys DC-Expert preferably Spice simulation
- Hspice and ADM preferably Static timing analyzer
- Pearl or equivalent Design for test, fault grading
- Sunrise or equivalent  Place and Route
- Cadence Silicon Ensemble or Avanti Apollo
The individual should be self-motivated, independent and detail oriented.

SENIOR LAYOUT DESIGNER
Requisition #SC008
Location of position Santa Clara California
Responsibilities:
Support layout of complex designs for next-generation 64-bit
RISC microprocessors using Cadence tools.
Requirements:
Layout school graduate with 5+ years layout experience or 2 - 3+ years
layout experience with microprocessor chips, using multiple metal layers on
submicron process.  Must have the ability to interpret complex logic and
translate to physical layout and to run, evaluate and correct DRC/ERC and
LVS.  Must posses good organization skills and have the ability to work as a
team member.  Cadence Opus/Virtuoso experience is desirable. AA graduate
with some basic electronics knowledge/skills is an added plus.

LAYOUT DESIGNER
Requisition #SC009
Location of position Santa Clara California
Responsibilities:
Support layout of complex designs for next-generation 64-bit RISC
microprocessors.
Requirements:
Layout school graduate with at least 2+ years of layout experience or 1 - 2+
years layout experience with microprocessor chips using a graphics computer.
Must be able to convert logic/schematics to physical layout. Must have
strong communication and organization skills, a team player attitude and a
strong desire to learn new skills.
---
Software Engineers - Tool Development
Req. #772
San Jose
Midwest-based software tools development company has established a West
Coast development office, and will be hiring 17 software engineers,
intermediate to senior levels, to staff this Silicon Valley division,
including experience directing others and/or leadership in architectural
issues.

Development will be focused in the areas of graphical debugging, functional
simulation tools, and target interfaces.  Responsibilities inherent in these
positions are the following: define, design, implement, validate, and
support extensions to the company's family of graphical debugging and
simulation products and library of target interfaces for these products;
collaborate with key customers and management; provide technical leadership
to other development team members; coordinate the integration of product
extensions with product changes and extensions developed at other locations.

General qualifications for all positions are 3-10 years experience in the
development of software tools (debuggers, compilers, emulators, assemblies,
utilities, etc.), fluency in C/C++, knowledge of one or more Assembly
languages, Microsoft Windows 3.X/95/NT and UNIX (Sun, Solaris, SunOS, HPUX).
A technical degree, architectural-level design, and/or experience as a Team
or Group Lead is desired.

Specific experience for the graphical debugger positions include experience
developing graphical debuggers for C and C++ with some or all of the
following features: on-chip control and configuration knowledge; target
abstraction; high-performance, format-independent symbol table
architectures; presentation of target execution trace and profiling
information. Pluses include MFC experience, familiarity with Pure Atria's
Clearcase development environment, and familiarity with component object
model architectures.

Background experience for the functional simulator positions involve
experience developing functional simulators for CISC or RISC microprocessors
with some or all of the following features: very high simulation speed;
accurate simulation of memory cache and peripheral behavior; precise
reporting of elapsed clock cycles; integration with other hardware and
software modeling facilities. Pluses include MFC experience, familiarity
with Pure Atria's Clearcase development environment.

Target interface positions' requirements encompass experience developing
debug targets interfaces with some or all of thefollowing: serial, parallel,
and Ethernet connections; multiple communication and chip control protocols
including JTAG and BDM; advanced features like data compression and "hot"
target connection; Windows95/NT devices drivers and VXDS.
Pluses include interface hardware design experience, familiarity with Pure
Atria's Clearcase development environment,familiarity with component object
model architectures.




Article: 14110
Subject: Re: 1-wire
From: Ray Andraka <randraka@ids.net>
Date: Wed, 13 Jan 1999 20:25:59 -0500
Links: << >>  << T >>  << A >>
Dallas used to have an assembly language snippet in their data book, I
think it was in the digital serial number device (DS2400?) data sheet.
A state machine to read the serial number is fairly trivial to implement
as well.  I did one several years ago in the corner of an XC3042.  As I
recall it only took up a couple CLBs.

G Henry Yogendran wrote:

> Can anybody tell me where I can get 1-wire interface code for
> Dallas parts.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 14111
Subject: Re: 1-wire
From: tcoonan@mindspring.com (Thomas A. Coonan)
Date: Thu, 14 Jan 1999 01:27:11 GMT
Links: << >>  << T >>  << A >>
Don't they have 8051 code eˇamples in their app notes?  I think
I remember seeing their code.
>Hi:
>
>Can anybody tell me where I can get 1-wire interface code for
>Dallas parts.
>
>
>Henry
>--
>------------------------------------
>
>

Article: 14112
Subject: Foundation Express Problem
From: Dominic Reitman <drreitma@iupui.edu>
Date: Wed, 13 Jan 1999 21:31:27 -0500
Links: << >>  << T >>  << A >>
I'm having problems when implementing vhdl code that contain processes.
I downloaded a sample vhdl file (a D register) from the xilinx homepage
to check the software with. When I use Foundation express to implement
the design it gives me a warning that the output is constant. I went
ahead and sythesized the design and worked like a single wire (i.e. the
Q output followed the D input without waiting for the clock's edge.)
Here is the file and warnings I received:

****************************
--------------------------------------------
-- D_REGISTER.VHD Version 1.0             --
-- Example of a behavioral description of --
-- a D register.                          --
-- HDL Synthesis Design Guide for FPGAs   --
-- May 1997                               --
--------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity d_register is
    port (CLK, DATA: in STD_LOGIC;
   Q: out STD_LOGIC);
end d_register;

architecture BEHAV of d_register is
begin
My_D_Reg: process (CLK, DATA)
    begin
        if (CLK'event and CLK='1') then
        Q <= DATA;
 end if;
    end process; -- End My_D_Reg
end BEHAV;

****************************************
Messages for d_register

Warnings
========

Warning: The output of the cell '/d_register/Logic1' is constant.
(FE-CHECK-3)

Messages
========

 Inferred memory devices in process 'My_D_Reg'
 in routine d_register line 19
         in file 'D:/My Designs/xilinx/D_register/VHDL/d_register.vhd'.
===============================================================================

|      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS
| ST |
===============================================================================

|          Q_reg           | Flip-flop |   1   |  -  | N  | N  | N  | N
| N  |
===============================================================================

Q_reg
-----
    set/reset/toggle: none

Writing to hnl file 'D:\My
Designs\xilinx\D_register/express/workdirs/WORK/d_register.hnl'
*******************************************
Messages for d_register-Optimized

Warnings
========

Warning: No global set / reset (GSR) net could be used in the design
because there is not a unique net that sets or resets all  the
sequential cells.  (FE-GSRMAP-5)

Messages
========

 Design has no net that can be used as a global set / reset (GSR) net.
 Inserted pad cell 'C3(IBUF)' at port 'CLK'.
 Inserted pad cell 'Q_reg(INFF_GC)' at port 'DATA'.
 Inserted pad cell 'C7(OBUF)' at port 'Q'.
 libpack: reading file `d:\FNDTN\SYNTH/lib/XC4000E/BUFG.dsn'
 Buffer allocation has inserted a buffer of type 'BUFG' at net
'/d_register-Optimized/N3'.
 libpack: reading file `d:\FNDTN\SYNTH/lib/XC4000E/CY4.dsn'
*******************************************************************

Any help in this matter would be appreciated, I'm using the Foundation
Series 1.4



Article: 14113
Subject: Re: Orcad Express Plus vs Foundation Express
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 13 Jan 1999 22:21:58 -0500
Links: << >>  << T >>  << A >>
pawelm wrote:
> I'm still hesitating - all my projects were made using Orcad software, but
> I'm really tired of their "support". As "non USA customer" I can't
> access  ODN, thay never have valid registered numbers database - so because
> of stupid "support machine" I was able to use it maybe 2 or 3 times during
> last 2 years (only their local dealer is o.k. :)  ).
> But as I can see it isn't only my problem.
> About "using Orcad doing FPGA work":
> Most of my projects  (9500,3x00, 5200, 4000E and Spartan) are
> schematic-based. I started to use VHDL after problems with transfering net
> properties from schematic to edif. Yes, I had problems
> with VHDL too - Orcad should work on error reports - but I managed to
> resolve my problems myself (I had to - because of their "support").
> The problem is I really know this software now and it's difficult to change
> it. Is it worth ?
> 
> Regards,
> Pawel
> 
> PS
> I have Foundation Base M1.4, but I've never tried to use it. Are any
> significant differences between 1.4 and 1.5  ?

I would believe that the schematic based FPGA design works OK. They are
widely used for board level schematic capture. 

I know that a lot of bugs were fixed. That is why I finally converted. I
was in the middle of my design and didn't want to change horses in
mid-stream. But evey time I called Xilinx with a problem I was told that
either "that is fixed in 1.5" or "they won't be fixing any more bugs in
1.4". The transition was a real pain because of the VHDL. They switched
compilers from Metamor to Express. The Express compiler likes to see
very different constructs from what the Metamor compiler will accept.
The Express compiler also has a tendency to produce some very weird
logic when you work with state machines. I had to relearn how to write
good VHDL code. 

I know that you won't like the Foundation schematic capture. It is far
below Orcad. The way they handle busses is almost bizarre. I belive they
fixed some of the more annoying "features" in 1.5, at least they told me
they were fixing them. But I haven't used schematics enough since I
converted to 1.5. 

Good luck with whatever you choose. 

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Article: 14114
Subject: Re: Foundation Express Problem
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 13 Jan 1999 22:50:44 -0500
Links: << >>  << T >>  << A >>
Dominic Reitman wrote:
> Messages
> ========
> 
>  Design has no net that can be used as a global set / reset (GSR) net.
>  Inserted pad cell 'C3(IBUF)' at port 'CLK'.
>  Inserted pad cell 'Q_reg(INFF_GC)' at port 'DATA'.
>  Inserted pad cell 'C7(OBUF)' at port 'Q'.
>  libpack: reading file `d:\FNDTN\SYNTH/lib/XC4000E/BUFG.dsn'
>  Buffer allocation has inserted a buffer of type 'BUFG' at net
> '/d_register-Optimized/N3'.
>  libpack: reading file `d:\FNDTN\SYNTH/lib/XC4000E/CY4.dsn'
> *******************************************************************
> 
> Any help in this matter would be appreciated, I'm using the Foundation
> Series 1.4

Here is my guess as to what is happening. I think your circuit is being
synthesized correctly. But the FF is being pushed into the IOB of the
input port. The messages above indicate this. The warning may be from
the fact that the input and output IOB are now connected by a wire. 

If you go to the project manager and select "Implementation" and
"Implementation Option" you will get the options dialog box. On the line
that says "Implementation" click the "Edit Template" button and a new
dialog box will come up. Find the "Pack I/O Registers/Latches into IOBs
for:" control. Select "OFF". Now click OK and OK again. Now redo your
Implementation. and you should get a good result. 

When you say that the output follows the input without waiting for the
clock, are you running a simulation, or testing a chip? If a simulation,
is it a functional simulation or timing (after place and route)?


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 14115
Subject: Ratings for Synplicity Synplify
From: "Jim King" <j_e_king@snotmail.com>
Date: Thu, 14 Jan 1999 13:56:29 -0000
Links: << >>  << T >>  << A >>
Has anybody experience of using Synplify with Xilinx devices?  We are
looking at getting a better synthesis tool than the one with Viewlogic's
Workview Office, and this is one we have come across.  Also it seems that
Synplicity and Xilinx have announced some sort of link-up to "provide their
joint customers with a world-class, high-density HDL design solution."

The tools we have looked at so far are Synopsis' FPGA Express and Exemplar
Leonardo Spectrum.  Our designs are small (usually less than 15-20% usage of
a 4020E), but have potential to grow.  What we do need is reliable and
repeatable timing, so we need a fair amount of control over the synthesis.
We use Xilinx 4000 devices.

Can anybody comment on the relative merits of these tools for the sort of
designs I have outlined?  Have you use these tools with other FPGAs?  I am
assuming that if a tool is good with one company's device, it will be
roughly the same with another's.  Or is this incorrect?

Regards
Jim King

Defence Evaluation and Research Agency
Defford
Worcestershire
WR8 9DU
U.K.
j_e_king@hotmail.com


Article: 14116
Subject: We need a Mentor Expert!
From: Monica Schnitger <monicaschnitger@earthlink.net>
Date: Thu, 14 Jan 1999 09:44:49 -0500
Links: << >>  << T >>  << A >>
Are you a Hardware Tools Developer with Mentor Graphics experience? 
Looking to make a change?  Read on ... Our client has developed a
reputation as one of the foremost suppliers of specialized
communications solutions, distinguished by modularity, flexibility,
interoperability and technological innovation.

Our client is seeking a Hardware Tools Developer.  The successful
candidate will have an outstanding knowledge of Mentor Graphics, with a
minimum of five years experience in a hardware development environment. 
Experience with UNIX Shell Scripts, FPGA and VHDL are all plusses.  This
position is located in the New York area.  Relocation assistance is
available.  Please email resumes in confidence to:
monica@devlinsearchgroup.com.

Article: 14117
Subject: Problem with reducing bus width / Foundation Series v1.5
From: "Stefan Klanke" <klanke@usa.net>
Date: Thu, 14 Jan 1999 16:17:24 +0100
Links: << >>  << T >>  << A >>
I'm trying to reduce a bus from 11 to 8 bit by just cutting off the three
highest bits. I wrote a little piece of vhdl-code to manage this. The code
was intended to shorten to busses with 11 bit width to 8 bit each and then
to combine them to one 16 bit bus. (hope everybody can understand me ;-) )
Here is it:

[---Begin VHDL-Code---]
library IEEE;
use IEEE.std_logic_1164.all;

entity combine is
    generic (N: NATURAL := 1);
    port (IH: in STD_LOGIC_VECTOR (10 downto 0);
          IL: in STD_LOGIC_VECTOR (10 downto 0);
          O: out STD_LOGIC_VECTOR (15 downto 0) );
end combine;

architecture combin_arch of combine is
  signal buf: UX01;
begin
  buf <= IH(10) AND IH(9) AND IH(8);
  buf <= IL(10) AND IL(9) AND IL(8);
  process (IL,IH)
  begin
    O <= "0000000000000000";
    O (7 downto 0) <= IL (7 downto 0);
    O (15 downto 8) <= IH (7 downto 0);
  end process;

end combin_arch;
[---End VHDL-Code---]

Synthesizing this macro is no problem, but when I try to implement it I get
the following error message:

[---Bedin error message---]
Loading design module
"Z:\studiena\xilinx\projects\add11vhd\xproj\ver2\COMBINE.ngo"...
ERROR:basnb:79 - File
   "Z:\studiena\xilinx\projects\add11vhd\xproj\ver2\COMBINE.ngo" cannot be
   merged into block "U16" (TYPE="COMBINE") because one or more pins on the
   block, including pin "IL<9>", were not found in the file.  Please make
sure
   that all pins on the instantiated component match pins in the lower-level
   design block (irrespective of case).  If there are bussed pins on this
block,
   make sure that the upper-level and lower-level netlists use the same
   bus-naming convention.
[---End error message---]

O.K. it's right, I just don't use three pins of each Input in the design,
but this is what I want.
So do you know any possibility to manage the problem?

Thanks in advance...
...Stefan.


Article: 14118
Subject: Unused port signals
From: Alexander Sherstuk <Sherstuk@amsd.com>
Date: Thu, 14 Jan 1999 18:39:44 +0300
Links: << >>  << T >>  << A >>
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------_=_NextPart_001_01BE3FD4.1C1EED6D
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	charset="koi8-r"

Hi Stefan,

   The problem you describe is well known - SYNOPSYS VHDL synthesizer
does not include unused port signals into the XSF file. So, there is no
way for the XILINX Implementation Tools to be aware of that "optimized
out" signals.
I am using the following workaround for that problem:
1)	Add some senseless additional output to your VHDL macro, e.g. 
	                       DUMMY0: out STD_LOGIC(10 downto 0);
2)	Add some sort of DUMMY0 assignment to your VHDL code
	                      DUMMY0 <= not IL;
3)	Do not use DUMMY0 output in your design as an input for an other
block.
4)	Now you've fooled around SYNOPSYS optimizer: it will think, that
all IL bus signals are necessary and will not optimize them out
5)	But XILINX Implementation Tools are clever enough to understand,
that DUMMY0 is not used by anybody. So, this additional bus - DUMMY0 -
will have no effect on your design. No additional FPGA resources will be
occupied.

Regards,
   Alex Sherstuk

	-----Original Message-----
	From:	Stefan Klanke [mailto:klanke@usa.net]
	Posted At:	Thursday, January 14, 1999 6:17 PM
	Posted To:	comp.arch.fpga
	Conversation:	Problem with reducing bus width / Foundation
Series v1.5
	Subject:	Problem with reducing bus width / Foundation
Series v1.5

	I'm trying to reduce a bus from 11 to 8 bit by just cutting off
the three
	highest bits. I wrote a little piece of vhdl-code to manage
this. The code
	was intended to shorten to busses with 11 bit width to 8 bit
each and then
	to combine them to one 16 bit bus. (hope everybody can
understand me ;-) )
	Here is it:

	[---Begin VHDL-Code---]
	library IEEE;
	use IEEE.std_logic_1164.all;

	entity combine is
	    generic (N: NATURAL := 1);
	    port (IH: in STD_LOGIC_VECTOR (10 downto 0);
	          IL: in STD_LOGIC_VECTOR (10 downto 0);
	          O: out STD_LOGIC_VECTOR (15 downto 0) );
	end combine;

	architecture combin_arch of combine is
	  signal buf: UX01;
	begin
	  buf <= IH(10) AND IH(9) AND IH(8);
	  buf <= IL(10) AND IL(9) AND IL(8);
	  process (IL,IH)
	  begin
	    O <= "0000000000000000";
	    O (7 downto 0) <= IL (7 downto 0);
	    O (15 downto 8) <= IH (7 downto 0);
	  end process;

	end combin_arch;
	[---End VHDL-Code---]

	Synthesizing this macro is no problem, but when I try to
implement it I get
	the following error message:

	[---Bedin error message---]
	Loading design module
	"Z:\studiena\xilinx\projects\add11vhd\xproj\ver2\COMBINE.ngo"...
	ERROR:basnb:79 - File
	   "Z:\studiena\xilinx\projects\add11vhd\xproj\ver2\COMBINE.ngo"
cannot be
	   merged into block "U16" (TYPE="COMBINE") because one or more
pins on the
	   block, including pin "IL<9>", were not found in the file.
Please make
	sure
	   that all pins on the instantiated component match pins in the
lower-level
	   design block (irrespective of case).  If there are bussed
pins on this
	block,
	   make sure that the upper-level and lower-level netlists use
the same
	   bus-naming convention.
	[---End error message---]

	O.K. it's right, I just don't use three pins of each Input in
the design,
	but this is what I want.
	So do you know any possibility to manage the problem?

	Thanks in advance...
	...Stefan.
	

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dkoi8-r">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2232.0">
<TITLE>Unused port signals</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2 FACE=3D"Arial">Hi Stefan,</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp; The problem you describe =
is well known - SYNOPSYS VHDL synthesizer does not include unused port =
signals into the XSF file. So, there is no way for the XILINX =
Implementation Tools to be aware of that "optimized out" =
signals.</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">I am using the following workaround =
for that problem:</FONT>

<OL TYPE=3D1><LI><FONT SIZE=3D2 FACE=3D"Arial">Add some senseless =
additional output to your VHDL macro, e.g. </FONT></LI>

<P><FONT SIZE=3D2 =
FACE=3D"Arial">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp; DUMMY0: out STD_LOGIC(10 downto 0);</FONT>
<LI><FONT SIZE=3D2 FACE=3D"Arial">Add some sort of DUMMY0 assignment to =
your VHDL code</FONT></LI>

<P><FONT SIZE=3D2 =
FACE=3D"Arial">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
DUMMY0 &lt;=3D not IL;</FONT>
<LI><FONT SIZE=3D2 FACE=3D"Arial">Do not use DUMMY0 output in your =
design as an input for an other block.</FONT></LI>
<LI><FONT SIZE=3D2 FACE=3D"Arial">Now you've fooled around SYNOPSYS =
optimizer: it will think, that all IL bus signals are necessary and =
will not optimize them out</FONT></LI>
<LI><FONT SIZE=3D2 FACE=3D"Arial">But XILINX Implementation Tools are =
clever enough to understand, that DUMMY0 is not used by anybody. So, =
this additional bus - DUMMY0 - will have no effect on your design. No =
additional FPGA resources will be occupied.</FONT></LI>
<BR>
</OL>
<P><FONT SIZE=3D2 FACE=3D"Arial">Regards,</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp; Alex Sherstuk</FONT>
</P>
<UL>
<P><A NAME=3D"_MailData"><FONT SIZE=3D2 FACE=3D"Arial">-----Original =
Message-----</FONT></A>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">From:&nbsp;&nbsp; Stefan Klanke =
[<A =
HREF=3D"mailto:klanke@usa.net">mailto:klanke@usa.net</A>]</FONT></B>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">Posted =
At:</FONT></B>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">Thursday, January 14, 1999 6:17 PM</FONT>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">Posted =
To:</FONT></B>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">comp.arch.fpga</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">Conversation:&nbsp;&nbsp;</FONT></B> <FONT SIZE=3D2 =
FACE=3D"Arial">Problem with reducing bus width / Foundation Series =
v1.5</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT>=
</B> <FONT SIZE=3D2 FACE=3D"Arial">Problem with reducing bus width / =
Foundation Series v1.5</FONT>
</P>

<P><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">I'm trying to reduce =
a bus from 11 to 8 bit by just cutting off the three</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">highest bits. I =
wrote a little piece of vhdl-code to manage this. The code</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">was intended to =
shorten to busses with 11 bit width to 8 bit each and then</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">to combine them to =
one 16 bit bus. (hope everybody can understand me ;-) )</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">Here is it:</FONT>
</P>

<P><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">[---Begin =
VHDL-Code---]</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">library =
IEEE;</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">use =
IEEE.std_logic_1164.all;</FONT>
</P>

<P><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">entity combine =
is</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp;&nbsp; =
generic (N: NATURAL :=3D 1);</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp;&nbsp; =
port (IH: in STD_LOGIC_VECTOR (10 downto 0);</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 =
FACE=3D"Arial">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
IL: in STD_LOGIC_VECTOR (10 downto 0);</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 =
FACE=3D"Arial">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
O: out STD_LOGIC_VECTOR (15 downto 0) );</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">end combine;</FONT>
</P>

<P><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">architecture =
combin_arch of combine is</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp; signal buf: =
UX01;</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">begin</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp; buf &lt;=3D =
IH(10) AND IH(9) AND IH(8);</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp; buf &lt;=3D =
IL(10) AND IL(9) AND IL(8);</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp; process =
(IL,IH)</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp; begin</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp;&nbsp; =
O &lt;=3D &quot;0000000000000000&quot;;</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp;&nbsp; =
O (7 downto 0) &lt;=3D IL (7 downto 0);</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp;&nbsp; =
O (15 downto 8) &lt;=3D IH (7 downto 0);</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp; end =
process;</FONT>
</P>

<P><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">end =
combin_arch;</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">[---End =
VHDL-Code---]</FONT>
</P>

<P><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">Synthesizing this =
macro is no problem, but when I try to implement it I get</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">the following error =
message:</FONT>
</P>

<P><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">[---Bedin error =
message---]</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">Loading design =
module</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 =
FACE=3D"Arial">&quot;Z:\studiena\xilinx\projects\add11vhd\xproj\ver2\COM=
BINE.ngo&quot;...</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">ERROR:basnb:79 - =
File</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp; =
&quot;Z:\studiena\xilinx\projects\add11vhd\xproj\ver2\COMBINE.ngo&quot; =
cannot be</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp; merged =
into block &quot;U16&quot; (TYPE=3D&quot;COMBINE&quot;) because one or =
more pins on the</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp; block, =
including pin &quot;IL&lt;9&gt;&quot;, were not found in the =
file.&nbsp; Please make</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">sure</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp; that =
all pins on the instantiated component match pins in the =
lower-level</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp; design =
block (irrespective of case).&nbsp; If there are bussed pins on =
this</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">block,</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp; make =
sure that the upper-level and lower-level netlists use the same</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">&nbsp;&nbsp; =
bus-naming convention.</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">[---End error =
message---]</FONT>
</P>

<P><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">O.K. it's right, I =
just don't use three pins of each Input in the design,</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">but this is what I =
want.</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">So do you know any =
possibility to manage the problem?</FONT>
</P>

<P><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">Thanks in =
advance...</FONT>
<BR><FONT COLOR=3D"#000000" SIZE=3D2 FACE=3D"Arial">...Stefan.</FONT>
<BR>
</P>
</UL>
</BODY>
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Article: 14119
Subject: Re: Orcad Express Plus vs Foundation Express
From: "Pawel Michocki" <pawelm@sim.com.pl>
Date: Thu, 14 Jan 1999 15:39:57 GMT
Links: << >>  << T >>  << A >>

>Rickman wrote:

>After posting my story a few times in this
>newsgroup I even received an email from someone at Orcad asking me to
>give the new version a try.

Really ? How many e-mails should I send to receive such offer ? ;))
Or maybe it's only for better, USA customers,  like other benefits: ODN or
"win palmpilot" ;))

Pawel

PS
I think i will use Xilinx Foundation for virtex and Orcad Express + Aliance
for the rest


Article: 14120
Subject: Re: Problem with reducing bus width / Foundation Series v1.5
From: "Jim King" <j_e_king@snotmail.com>
Date: Thu, 14 Jan 1999 15:51:38 -0000
Links: << >>  << T >>  << A >>

Stefan Klanke wrote in message <77l1q1$kdo@nx2.HRZ.Uni-Dortmund.DE>...
>I'm trying to reduce a bus from 11 to 8 bit by just cutting off the three
>highest bits. I wrote a little piece of vhdl-code to manage this. The code
>was intended to shorten to busses with 11 bit width to 8 bit each and then
>to combine them to one 16 bit bus. (hope everybody can understand me ;-) )
>Here is it:


<snip code, not important for my comment>

>Synthesizing this macro is no problem, but when I try to implement it I get
>the following error message:
>
>[---Bedin error message---]
>Loading design module
>"Z:\studiena\xilinx\projects\add11vhd\xproj\ver2\COMBINE.ngo"...
>ERROR:basnb:79 - File
>   "Z:\studiena\xilinx\projects\add11vhd\xproj\ver2\COMBINE.ngo" cannot be
>   merged into block "U16" (TYPE="COMBINE") because one or more pins on the
>   block, including pin "IL<9>", were not found in the file.  Please make
>sure
>   that all pins on the instantiated component match pins in the
lower-level
>   design block (irrespective of case).  If there are bussed pins on this
block,
>   make sure that the upper-level and lower-level netlists use the same
>   bus-naming convention.
>[---End error message---]
>
>O.K. it's right, I just don't use three pins of each Input in the design,
>but this is what I want.
>So do you know any possibility to manage the problem?
>
>Thanks in advance...
>...Stefan.
>

I got this message when I was instantiating a VHDL-based symbol in a
Viewdraw schematic.  I had synthesised the VHDL and exported an XNF netlist
from the synthesis tool.  I created a symbol and linked it to the XNF.  I
would put it in the schematic, and generate an EDIF netlist from the
schematic.  When I ran the EDIF through the Xilinx M1 tools I got the
message above.  What it came down to was that the XNF described busses like
this:
busname<index>
and the EDIF described them like this
busnameindex

I still haven't worked out an elegant solution.
What I do for now label the symbol pins like this
bus<[number : smallernumber]>

the schematic checker brings up warnings about illegal characters, but the
resulting EDIF implements fine.

Hope this helps.  If I turn out to be wildly wrong, don't hold it against
me!


Article: 14121
Subject: Hard porting to FPGA Express
From: "Ido Kleinman" <kleinn@REMOVETHIS.mail.biu.ac.il>
Date: Thu, 14 Jan 1999 20:27:09 +0200
Links: << >>  << T >>  << A >>
Hi!

I've been using Foundation 1.4 with it's Metamor synthesis for a while now,
and I've got a few working designs.
I recently moved to Foundation 1.5 and it's FPGA Express synthesis -
I haven't been able to even successfully compile my previously WORKING
designs:

1. FPGAEXP won't accept:
if (LowerAddressBus > X"01F0") then

LowerAddressBus is just a std_logic_vector(15 downto 0).
it yells about type mismatch between left/right binary operand. The X seems
to be disturbing - it would only accept Binary notation without any prefix
to the " character so I have to write:

if (LowerAddressBus > "0000000111110000") then

I tried using based literals such as 16#01F0# and variations - and it won't
work. Any solution, or I will have to do all my comparisons in Binary?

2. My inhibit_buf attribute on my global Clk signal wasn't accepted! What's
the attribute for inhibiting insertion of IBUFs/OBUFs/etc on FPGAEXP? I
don't want my clock signal buffered with a standard IBUF, that why I usually
instanciate a BUFG/BUFGS for it and inhibit other buffers on the pad in the
code.

3. After I made the annoying adjustments to my code, my previously working
simulation files yielded strange new results in which some output signals
were defined as "????" - what's this? I thought std_logic "only" has 9
states...

4. What about my two-dimensional arrays? I am not trying to synthesize
anything special - just some
better-looking-VHDL multi-bit look-up tables... FPGAEXP won't support it?
Forever?


Anyone who can help me out here - even to some of my problems, would be
blessed.
Sorry for my lame English, it ain't my mother-tounge... :-)
Thanks in advance,

--

Yours,
  -- Ido Kleinman.
  kleinn@REMOVETHIS.mail.biu.ac.il
 ** Please delete the "REMOVETHIS." substring to EMail me.





Article: 14122
Subject: FPGAs in die form
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Date: 14 Jan 1999 10:44:43 -0800
Links: << >>  << T >>  << A >>
Dear all,

we are undertaking a new project involving the 3D stacking of several
FPGAs, memories and a CMOS image sensor to form a very compact system
for real-time image acquisition and processing. We have been trying
to get Xilinx FPGAs in die form but since new Xilinx devices (Virtex,
XV) are not currently available as individual dies, we are looking for
other FPGA vendors.

Any suggestions?

thanks in advance,

-Arrigo
--
Arrigo Benedetti          o         e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93	 < >			phone: (626) 395-3695
Pasadena, CA 91125	 / \			fax:   (626) 795-8649
Article: 14123
Subject: Re: *** FOR STEVE WALZ ONLY - PRIVATE AND PERSONAL - *** Re: FOR JOHN WOODGATE ONLY: ==> Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
From: John Fields <jfields@austininstruments.com>
Date: Thu, 14 Jan 1999 19:57:17 +0000
Links: << >>  << T >>  << A >>
Richard Steven Walz wrote:

> Not only that, John, but this clown NEVER EVER wrote me in
> email!!! Not
> even once!! ;-)

--

I'm not surprised.

He knew he would be in so far over his head that he would have had
to commit hara-kiri just to get to -1.

--

John Fields                    Austin Instruments, Inc.
El Presidente                  Austin, Republic of Texas
"I speak for the company"      http://www.austininstruments.com


Article: 14124
Subject: Re: Hard porting to FPGA Express
From: "Steve" <reply.through.newsgroup@paranoid.com>
Date: Thu, 14 Jan 1999 20:56:06 GMT
Links: << >>  << T >>  << A >>
Ido Kleinman wrote in message <77lek9$5mo$1@news2.inter.net.il>...
>Hi!
>
>I've been using Foundation 1.4 with it's Metamor synthesis for a while now,
>and I've got a few working designs.
>I recently moved to Foundation 1.5 and it's FPGA Express synthesis -
>I haven't been able to even successfully compile my previously WORKING
>designs:
>
>1. FPGAEXP won't accept:
>if (LowerAddressBus > X"01F0") then
>
>LowerAddressBus is just a std_logic_vector(15 downto 0).
>it yells about type mismatch between left/right binary operand. The X seems
>to be disturbing - it would only accept Binary notation without any prefix
>to the " character so I have to write:
>
>if (LowerAddressBus > "0000000111110000") then
>
>I tried using based literals such as 16#01F0# and variations - and it won't
>work. Any solution, or I will have to do all my comparisons in Binary?
>



This is gets even more interesting if you want to simulate the same code
with
a VHDL-93 compliant simulator like Active VHDL.

I generally define my constants at the top, and based on recommendations
from
one of these groups, I have standardized on the following.  It passes both
FPGA
Express and Active-VHDL syntax.

CONSTANT Kx01F0  :STD_LOGIC_VECTOR (15 DOWNTO 0):=
        TO_STDLOGICVECTOR(Bit_Vector'(x"01F0"));

I'll let someone else address the other issues.



Steve






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