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Rolavine writes: > OK, what the world needs is not more tools for the FPGA > preisthood. These corporate types who do the one trick pony. The world > needs easy to use tools for the rest of us, who do an occassional FPGA > or CPLD. I agree absolutely. However there are non-technical reasons why I won't, personally, work on a high level language tool. The tool I am proposing will serve as a back end to whatever high level software you can find, and I assure you, the emphasis will be on easy to use in the same senses that GCC is easy to use. I.e., if you want it to look like Visual Basic, forget it. If you just want to enter a simple circuit and watch it run (or at least, simulate), consider that the focus of the tool. > The last great tool for us was the PLDShell program writen by INTEL to > support their now defunct PLDs and FPGAs. I learned that system and > produced useful applications in less time then it took me to just > install Foundation or Max! Yes well, I hear install times have got better lately. I do remember waiting 1 hour for MaxplusII to install a few months ago. Very tedious. -- JamieArticle: 14176
On Fri, 15 Jan 1999 03:49:46 -0500, Rickman <spamgoeshere4@yahoo.com> wrote: >I would hazzard a guess that everytime a newbie has to write code to do >this, he has to reinvent the wheel. I don't believe Xilinx provides any >code written in a HLL, only 8051 ASM. Anyone out there have some C code >they would like to contribute to the cause? Although the algorithm is >not complex, it is not easy to glean from the data book description. i've also got C code to do all this, through a control register on a PC (as well as a hex file conversion futility). if anyone wants to post it on a website, mail me. on the other hand, i guess i could put it on my own site if there's any interest - anybody else want to mail me code/documentation/whatever to put up? evanArticle: 14177
Brian Drummond <brian@shapes.demon.co.uk> wrote in article <36a0a1f1.3171159@news.demon.co.uk>... > On 15 Jan 1999 14:39:29 GMT, "Austin Franklin" <aus3tin@darkroom.com> > wrote: > > >> The cost of developing an FPGA/core PCI interface system just got a lot > >> cheaper. > >> PLD Consulting Editor Murray Disman gives the scoop on a two team > >> approach in > >> which two companies provide a populated board and netlist for a PCI > >> target for > >> just $695. Compare that to $8,000 for a PCI core. Wow. But there's a > >> catch. > >> > >http://www.edtn.com/shared/redirect?url=http://www.edtn.com/pld/pldp.htm&so u > >rce_code=26 > > > >You forgot to mention this little 'tidbit', which is probably what you mean > >by 'there's a catch': > > > >"The user is free to use the core to develop their system, but must > >negotiate the purchase of the core if the system goes into production. " > > > >What's that going to cost? > > Logically, not more than buying the whole thing from Xilinx. ($8995 last > time I looked.) One would hope you can at least credit the original > purchase against this. > > But deferring the major cost to the production schedule instead of the > development schedule can make all the difference to some projects... I agree. But, with a PCI interface, there are subtle differences in implementation and testing that can make or break a project that far outweigh the initial cost of the 'core'. AND without the source code, and the expertise in PCI, these problems can be difficult to find. I guess I would trust the Xilinx PCI core more than anyone else's (well, except for the ones I did ;-), at least until someone else provided some sort of compliance testing, full timing specs etc. It is one thing to just work in 'a' machine in 'the' lab with one other PCI card, but to actually make the PCI spec, in a fully loaded machine AND with all the PCI host bridge chips out there, is a totally different feat. AustinArticle: 14178
--------------411786DE068EFE14A7E07E8A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Benoit, Please E-Mail your CV to scott.griffith@conexant.com Manager RF Systems - Cordless Products. 4311 Jamboree Rd, M/S P02-218, Newport Beach, California 92660-3008 SG Benoit MICHEL wrote: > Currently a student in fourth year at ESIEE (Ecole Superieure > d'Ingenieurs en Electronique et Electrotechnique), a French five-year > Electrical and Electronic Engineering college leading to a degree > equivalent to a Master of Science in Electrical Engineering and Computer > Science, I am looking for an internship from May to July 1999 as part of > my course. > > I would like to work as an ASIC designer and I think it is very > important for a French engineer to acquire international work > experience. > > Please do not hesitate to contact me if you want to have my CV. > > Benoit Michel > michelb@esiee.fr --------------411786DE068EFE14A7E07E8A Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> Benoit, <P>Please E-Mail your CV to <A HREF="mailto:scott.griffith@conexant.com">scott.griffith@conexant.com</A> Manager RF Systems - Cordless Products. 4311 Jamboree Rd, M/S P02-218, Newport Beach, California 92660-3008 <P>SG <P>Benoit MICHEL wrote: <BLOCKQUOTE TYPE=CITE>Currently a student in fourth year at ESIEE (Ecole Superieure <BR>d'Ingenieurs en Electronique et Electrotechnique), a French five-year <BR>Electrical and Electronic Engineering college leading to a degree <BR>equivalent to a Master of Science in Electrical Engineering and Computer <BR>Science, I am looking for an internship from May to July 1999 as part of <BR>my course. <P> I would like to work as an ASIC designer and I think it is very <BR>important for a French engineer to acquire international work <BR>experience. <P> Please do not hesitate to contact me if you want to have my CV. <P>Benoit Michel <BR>michelb@esiee.fr</BLOCKQUOTE> </HTML> --------------411786DE068EFE14A7E07E8A--Article: 14179
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Mitch Thornton wrote:
> CALL FOR PAPERS
>
> 4th International Workshop on Applications of the Reed-Müller Expansion
> in Circuit Design
> August 20-21, 1999, University of Victoria, Victoria B.C., Canada
>
> Non-Restrictive topic list includes:
> AND-XOR representations, decision diagrams, spectral techniques,
> testability issues
>
> Submission Deadline: April 1, 1999
>
> Submit 5 copies of drafts up to 20 pages in length to:
>
> Michael Miller, Workshop Chair
> Department of Computer Science
> University of Victoria
> Victoria, B.C., Canada V8W 3P6
>
> or email PS, PDF, Latex or MS Word files to:
>
> rm99@csr.uvic.ca
>
> For more information:
>
> http://www.csr.uvic.ca/~mmiller/RM99
Please suggest me of any sites which can give me information on
Reed-Müller circuits.
Thanks
Manish
--
-------------------------------------------------------
-------------------------------------------------------
Manish Shrivastava
HL EZ SIN MD
|P| 65--8400 882
|F| 65--8400 332
|@| Manish.Shrivastava@SIEMENS-SCG.COM / manish@ieee.org
shmanish@ezmsgp.hl.siemens.de
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Mitch Thornton wrote:
<BLOCKQUOTE TYPE=CITE>CALL FOR PAPERS
<P>4th International Workshop on Applications of the Reed-Müller Expansion
<BR>in Circuit Design
<BR>August 20-21, 1999, University of Victoria, Victoria B.C., Canada
<P>Non-Restrictive topic list includes:
<BR>AND-XOR representations, decision diagrams, spectral techniques,
<BR>testability issues
<P>Submission Deadline: April 1, 1999
<P>Submit 5 copies of drafts up to 20 pages in length to:
<P>Michael Miller, Workshop Chair
<BR>Department of Computer Science
<BR>University of Victoria
<BR>Victoria, B.C., Canada V8W 3P6
<P>or email PS, PDF, Latex or MS Word files to:
<P>rm99@csr.uvic.ca
<P>For more information:
<P> <A HREF="http://www.csr.uvic.ca/~mmiller/RM99">http://www.csr.uvic.ca/~mmiller/RM99</A></BLOCKQUOTE>
Please suggest me of any sites which can give me information on Reed-Müller
circuits.
<BR>Thanks
<BR>Manish
<PRE>--
-------------------------------------------------------
-------------------------------------------------------
Manish Shrivastava
HL EZ SIN MD
|P| 65--8400 882
|F| 65--8400 332
|@| Manish.Shrivastava@SIEMENS-SCG.COM / manish@ieee.org
shmanish@ezmsgp.hl.siemens.de
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Article: 14180
Of the two types for the function parameter in vhdl, i.e. constant
and signal, constant parameter cannot be modified within the function
body.
In a function made of purely combinational logic blocks, however,
the function operates on the input parameters and give off the results
immediately, there won't be any functional differences no matter its
parameters are defined constant or signal.
Am I right or wrong? What's the correct approach when I implement
bit permutation or substitute box, etc.?
Article: 14181Hi, I have been thinking of using Atmel's AT40K family together with IDS 6.0 in my next design. I have not done anything yet by playing with the software it seems to me that everything what you need, to design a system is there, and this software is free!!! Why don't you download it and play - you may be like it! Regards Alex denis lachapelle wrote: > Is there many poeple using the AT40K family ? > Which tools do you use? > > Thank you, > > Denis Lachapelle, sysacom@cam.org > Sysacom R&D plus inc. > www.cam.org/~sysacom > tel 450 585-6396, fax 450 582-3231Article: 14182
On 17 Jan 1999 17:31:20 GMT, "Austin Franklin" <aus3tin@darkroom.com> wrote: >Brian Drummond <brian@shapes.demon.co.uk> wrote in article ><36a0a1f1.3171159@news.demon.co.uk>... >> On 15 Jan 1999 14:39:29 GMT, "Austin Franklin" <aus3tin@darkroom.com> >> wrote: >> >> >> The cost of developing an FPGA/core PCI interface system just got a >lot >> >> cheaper. >> >"The user is free to use the core to develop their system, but must >> >negotiate the purchase of the core if the system goes into production. " >> > >> >What's that going to cost? >> >> Logically, not more than buying the whole thing from Xilinx. ($8995 last >> time I looked.) One would hope you can at least credit the original >> purchase against this. >> >> But deferring the major cost to the production schedule instead of the >> development schedule can make all the difference to some projects... > >I agree. But, with a PCI interface, there are subtle differences in >implementation and testing that can make or break a project that far >outweigh the initial cost of the 'core'. AND without the source code, and >the expertise in PCI, these problems can be difficult to find. I guess I >would trust the Xilinx PCI core more than anyone else's (well, except for >the ones I did ;-), at least until someone else provided some sort of >compliance testing, full timing specs etc. I guess I assumed rather a lot... But since the board in question appears to be the very one supplied as part of the Xilinx kit (at least it goes by the same name, from the same supplier, as far as I can see) I wonder if it's such an unreasonable assumption. >It is one thing to just work in 'a' machine in 'the' lab with one other PCI >card, but to actually make the PCI spec, in a fully loaded machine AND with >all the PCI host bridge chips out there, is a totally different feat. Agreed. Since this thread was started by a sales party for the board manufacturer, let's ask him - whose PCI core is in this cut-price deal, and do you get the full set of information? - BrianArticle: 14183
Is there any site from where I can down load a free max+plus ll(ALTEAR COMPANY) simulator and runs on Windows 95 environment. This simulator must handle big projects (up to 10k gates) in timing simulation. If you have them, send them to me then I'm very thanks for you kimteac@hanmail.netArticle: 14184
I need to buy an HDL Synthesis tool with the back-end Target = Xilinx. I've got it down to a choice of either Leonardo [Exemplar] or Synplify [Synplicity]. Anybody have a comments +or - on this chain Verilog-> <TOOL>-> Xilinx Spartan-XL/XC4K-XL/Virtex. One thing I have discovered is that the Xilinx place&route tools take a lot longer to run with the Synplify output than with the Spectrum - esp. the placer. In both cases the design was unconstrained. Of course I might be doing something wrong to the Synplify tool !Article: 14185
This is a multi-part message in MIME format. --------------672FFA504FA9C0987F73E244 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Jason Pattison wrote: > Does anyone know how to program the ALTERA FLEX configuration EPROMS via the > byte blaster cable without purchasing the proper programming hardware???? > > Schematics or programming voltage levels / timing diagrams would be helpful. > > Thanks in advance > JASON Hi, First of all, these devices are (one-time programmable) PROM's, so no E(E)PROM's. I am pretty sure you can't programm them with the byte blaster, either off-line or in-system. Check out http://www.altera.com and look for the (new) EPC2 devices. These are in-system (re)programmable through its JTAG pins. Of course, you can also use JTAG for board-level (production) test, since this is why JTAG was "invented" in the first place..... The EPC2 devices can also be programmed using the bit/byte blaster. Good luck, Jaap Mol. --------------672FFA504FA9C0987F73E244 Content-Type: text/x-vcard; charset=us-ascii; name="jh_mol.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Jaap H. Mol Content-Disposition: attachment; filename="jh_mol.vcf" begin:vcard n:Jennita;Jaap en tel;fax:(+31)-74-2484056 tel;home:(+31)-74-2429714 tel;work:(+31)-74-2483999 x-mozilla-html:TRUE version:2.1 email;internet:jh_mol@wxs.nl adr;quoted-printable:;;Robert Kochstraat 59=0D=0A;Hengelo;;7555 AN;Netherlands fn:Jaap en Jennita end:vcard --------------672FFA504FA9C0987F73E244--Article: 14186
John Larkin wrote: > > > Anyone out there have some C code > > they would like to contribute to the cause? Although the algorithm is > > not complex, it is not easy to glean from the data book description. > > > > -- > > > > Rick Collins > > Rick, > > I have Motorola 68000 assembly-language code that loads two 4010's from > config tables built into the microprocessor eprom image. We also wrote a > DOS (PowerBasic) program that builds the eprom image from the Motorola > hex-format uP code and two Xilinx .RBT files. The source code has lots > of painfully-discovered timing and sequencing notes. > > Yes, it's silly for everybody to keep re-inventing this stuff, > especially based on the sparsely-scattered collection of vague hints > that comprises most FPGA documentation. One or two solid appnotes could > save customers literally hundreds of thousands of hours of reinvention. > > John > > -- > > ********************************************************************h > > John Larkin, President phone 415 753-5814 fax 753-3301 > Highland Technology, Inc > 320 Judah Street jjlarkin@worldnet.att.net > San Francisco, CA 94122 http://www.highlandtechnology.com If you would like to contribute your code, I will make it available on my web site. Or Evan has offered to create a page on his web site. I will make another offer. If anyone wants to send me some good, clean C code (or Pascal for those who use it), I will take some time to write a "solid appnote" and offer it to Xilinx to put on their web site. Isn't that the most logical place for it? -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 14187
Rickman wrote: > I will make another offer. If anyone wants to send me some > good, clean C > code (or Pascal for those who use it), I will take some > time to write a > "solid appnote" and offer it to Xilinx to put on their web > site. Isn't > that the most logical place for it? > > -- > > Rick Collins > > redsp@usa.net Good idea, and I have already promised John Larkin that I will support this.But I personally am just not the right guy to write it. Let's do it together, somehow. We all see the benefit for everybody, Xilinx included. Peter Alfke, Xilinx ApplicationsArticle: 14188
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Article: 14189Ido Kleinman Perhaps I don't quite understand your problem, it seems to be the FPGA Express's limitation. I used to synthesize the VHDL design with ViewLogic's Aurora. However, in ViewLogic 7.5, it is with FPGA Express. I am now using it and find that it doesn't quite work well with other ViewLogic's product like ViewDraw, ViewSim. Maybe Synopsis should positively see his problem. Best regards YM Yip 5/F Yip Yiu Man, Leslie leslie.yip@asmpt.com In article <77lek9$5mo$1@news2.inter.net.il>, "Ido Kleinman" <kleinn@REMOVETHIS.mail.biu.ac.il> wrote: > Hi! > > I've been using Foundation 1.4 with it's Metamor synthesis for a while now, > and I've got a few working designs. > I recently moved to Foundation 1.5 and it's FPGA Express synthesis - > I haven't been able to even successfully compile my previously WORKING > designs: > > 1. FPGAEXP won't accept: > if (LowerAddressBus > X"01F0") then > > LowerAddressBus is just a std_logic_vector(15 downto 0). > it yells about type mismatch between left/right binary operand. The X seems > to be disturbing - it would only accept Binary notation without any prefix > to the " character so I have to write: > > if (LowerAddressBus > "0000000111110000") then > > I tried using based literals such as 16#01F0# and variations - and it won't > work. Any solution, or I will have to do all my comparisons in Binary? > > 2. My inhibit_buf attribute on my global Clk signal wasn't accepted! What's > the attribute for inhibiting insertion of IBUFs/OBUFs/etc on FPGAEXP? I > don't want my clock signal buffered with a standard IBUF, that why I usually > instanciate a BUFG/BUFGS for it and inhibit other buffers on the pad in the > code. > > 3. After I made the annoying adjustments to my code, my previously working > simulation files yielded strange new results in which some output signals > were defined as "????" - what's this? I thought std_logic "only" has 9 > states... > > 4. What about my two-dimensional arrays? I am not trying to synthesize > anything special - just some > better-looking-VHDL multi-bit look-up tables... FPGAEXP won't support it? > Forever? > > Anyone who can help me out here - even to some of my problems, would be > blessed. > Sorry for my lame English, it ain't my mother-tounge... :-) > Thanks in advance, > > -- > > Yours, > -- Ido Kleinman. > kleinn@REMOVETHIS.mail.biu.ac.il > ** Please delete the "REMOVETHIS." substring to EMail me. > > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14190
NNTP-Posting-Date: Mon, 18 Jan 1999 23:09:10 PDT Jim, I realize you asked about Synplicity use with Xilinx, which I haven't done, but I used both it and Viewlogic in designing a custom processor using 2 Actel 1280s (about 12K Actel FPGA gates). The design was 80+ pages of VHDL in over 30 files. I found the Synplify tool to be excellent, and the Viewlogic tool to be horrible. What the Viewlogic tool took 2+ hrs to badly synthesize, the Synplify tool took < 10 minutes with very good results. The Actel mux structure is a bitch to synthesize, but Synplify handled it very well. Additionally, their l RTL and technology view (Post synth. target schematic) were great helps in finding long prop. delay problems. I dropped using Viewsynth completely, and the company bought the Synplify tool even though we already owned the Viewlogic tool (with maint that included aurora).The only pain about the Synplify product is that it's a bit pricey with the viewers. I can provide more details if you're interested. Mark Adams markadams@icnt.net Jim King wrote in message <77kt2c$64m$1@trog.dra.hmg.gb>... >Has anybody experience of using Synplify with Xilinx devices? We are >looking at getting a better synthesis tool than the one with Viewlogic's >roughly the same with another's. Or is this incorrect? ----------------------------------SNIP-------------------------------------- ---------------- > >Regards >Jim King > >Defence Evaluation and Research Agency >Defford >Worcestershire >WR8 9DU >U.K. >j_e_king@hotmail.com > >Article: 14191
Xilinx offers the foundation package, where the Synopsys FPGA Express is included. Depending on which package you choose you will have support for all XILINX devices or only a subset. Take a look at there wesite. Best Regards Ansgar Bambynek P.S.: Please remove the xxx from my email address. Rick Filipkiewicz wrote: > I need to buy an HDL Synthesis tool with the back-end Target = Xilinx. > I've got it down to a choice of > either Leonardo [Exemplar] or Synplify [Synplicity]. Anybody have a > comments +or - on this chain > Verilog-> <TOOL>-> Xilinx Spartan-XL/XC4K-XL/Virtex. > > One thing I have discovered is that the Xilinx place&route tools take a > lot longer to run with the Synplify > output than with the Spectrum - esp. the placer. In both cases the > design was unconstrained. Of course I might be doing something wrong to > the Synplify tool !Article: 14192
>One thing I have discovered is that the Xilinx place&route tools take a >lot longer to run with the Synplify >output than with the Spectrum - esp. the placer. In both cases the >design was unconstrained. Of course I might be doing something wrong to >the Synplify tool ! Does Spectrum preserve the hierarchy in the ouput netlist? I think that Synplify default does not preserve the hierarchy by default. That might be a reason why the Spectrum ouput has faster PAR runtimes. This because the placer don't know about the hierarchy and the placer has to do more work. As you know the placer is not that good... Check the release notes for Synplify 5.08 http://www.synplicity.com/support/rel508_notes.html I think there is a way to force Synplify to keep the hiearchy, well at least it _should_ be possible. / Jonas ThorArticle: 14193
Have you considered configuring the device at hte factory and making use of the
device "shutdown/powerdown" etc. and using a battery backup, that waay there is no
need for a configurator/eeprom. There are problems with this approach, but it is just
an idea.
Cheers,
Cameron Watt
Tom Kean wrote:
> It is possible for a hacker to copy your design if you use a RAM programmed FPGA
> assuming he can readout the serial EPROM or monitor the bitstream going into the
> FPGA. If you want to avoid this problem you need to use a device which gets
> programmed
> in the factory like an Actel part or a FLASH or EPROM based PLD. Antifuse FPGA's
>
> such as Actel's appear to be more resistant to bitstream copying than the other
> technologies.
> There are various tricks you can play to make SRAM FPGA's resistant to bitstream
> copying
> but they all increase cost or reduce reliability in some way.
>
> Copying the bitstream does not tell the hacker how the design works or give him
> it in a
> format which is easy to change or improve. A lot of information is lost between
> the HDL
> and the bitstream: the situation is worse for a hacker than trying to reverse
> compile
> a C program from machine code. Chances are, unless you have done something very
> smart
> in your design, reverse engineering it from the bitstream is harder work than
> redesigning it
> from scratch.
>
> So having your design copied is a real threat but having it reverse engineered is
> probably
> only a theoretical risk. Most people forget about it and concentrate on getting
> the product to market
> fast with the FPGA's with the best price/performance.
>
> Tom Kean.
>
> schaltung@hotmail.com wrote:
>
> > I'm currently designing a fpga-based system for a wide consumer market. Since
> > this is my first design to go on production, I'm concerned about the
> > intellectual property of the hardware implemented in the FPGA.
> >
> > Nobody likes to spend months of effort in the lab, while some hacker in the
> > other side of the world reads out the eeprom with the programming bitstream
> > and somehow gets my code (not funny at all).
> >
> > Is it possible to obtain the hdl code or any revealing information by doing
> > reverse engineering? I use both Altera's and Xilinx's FPGAs
> >
> > How do you guys deal with intellectual property?
> >
> > Cya.
> > Antonio Moreno
> > schaltung@hotmail.com
> >
> > -----------== Posted via Deja News, The Discussion Network ==----------
> > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
>
> ------------------------------------------------------------------------
>
> Tom Kean <tom@algotronix.com>
> Director
> Algotronix Ltd.
>
> Tom Kean
> Director <tom@algotronix.com>
> Algotronix Ltd. HTML Mail
> P.O. Box 23116 Fax: UK +44 131 556 9247
> Edinburgh Work: UK +44 131 556 9242
> EH8 8YB Netscape Conference Address
> Scotland
> Web Site: www.algotronix.com
> Additional Information:
> Last Name Kean
> First Name Tom
> Version 2.1
Article: 14194Send your CV and details to jobs@arbour.co.uk All positions are permanent and based in the United Kingdom.Article: 14195
Hi to everyone! I'm using Xilinx M1.4 (Alliance) on a workstation (HP) and the Xchecker-cable for downloading the generated *.bit-file on a XC4010E. My problem is that the downloaded design doesn't do what the simulation makes me expecting it to do. Some parts of my design are working fine what makes me sure that I did the implementation correctly. But some parts don't work at all and the report files don't show any warnings/errors that seem to be the cause for this problem. I know there is a posibility for a hardware debugging but I don't know how to get there. When implementing the design the check-box "Enable Bitstream Verification and In-Circuit Hardware Dedugging" is checked in the XC4000 Configuraion Options and the Readback Clock is set to CCLK. But when I call the Hardware Debugger it tells me that the "design does not have a readback block connected". The the xchecker-program run from the command line detects a cable "serial-readback". Does this just mean that the cable supports readback-mode if the design does too? And what exactly is the "Readback Block"? Do I have to add some functions to my design? Or do I have just to change some settings for the implementation? What do I have to do to run the Hardware Debugger??? Bye, GerdArticle: 14196
kim tae-chang wrote: > > Is there any site from where I can down load a free max+plus ll(ALTEAR > COMPANY) simulator and runs on Windows 95 environment. > This simulator must handle big projects (up to 10k gates) in timing > simulation. There is only one _free_ MAX+plus II software. It's available at http://www.altera.com For big projects and with timing, the software is $$$. ArminArticle: 14197
Gerd Beil wrote: <36A4B9EF.C3E3F6B@rzws.fh-aalen.de>... >Hi to everyone! > >I'm using Xilinx M1.4 (Alliance) on a workstation (HP) and the >Xchecker-cable for downloading the generated *.bit-file on a XC4010E. My >problem is that the downloaded design doesn't do what the simulation >makes me expecting it to do. Some parts of my design are working fine >what makes me sure that I did the implementation correctly. But some >parts don't work at all and the report files don't show any >warnings/errors that seem to be the cause for this problem. I know there >is a posibility for a hardware debugging but I don't know how to get >there. >When implementing the design the check-box "Enable Bitstream >Verification and In-Circuit Hardware Dedugging" is checked in the XC4000 >Configuraion Options and the Readback Clock is set to CCLK. But when I >call the Hardware Debugger it tells me that the "design does not have a >readback block connected". The the xchecker-program run from the command >line detects a cable "serial-readback". Does this just mean that the >cable supports readback-mode if the design does too? And what exactly is >the "Readback Block"? Do I have to add some functions to my design? Or >do I have just to change some settings for the implementation? What do I >have to do to run the Hardware Debugger??? > >Bye, > >Gerd You have to have :"Readback Block" in your design and in design manager in "configuration options" you must "Enable Bitstream Verification and In-Circuit Hardware Debugging". Regards, PawelArticle: 14198
Duck Foot <duckfoot11@hotmail.com> wrote: > Of the two types for the function parameter in vhdl, i.e. constant > and signal, constant parameter cannot be modified within the function > body. > In a function made of purely combinational logic blocks, however, > the function operates on the input parameters and give off the results > immediately, there won't be any functional differences no matter its > parameters are defined constant or signal. > Am I right or wrong? What's the correct approach when I implement > bit permutation or substitute box, etc.? Parameters of class signal may be of mode in, in which case they are read only; out, in which case they are write only; on inout, in which case they can be both read and written. There is also a class variable, which can take the same three modes. The only reason to pass something as either a signal or as a variable is if either you need to write through the parameter (in which case a function cannot be used) or if you wish to use signal attributes on the parameter, such as 'event. Hope this helps, Paul -- Paul Menchini | mench@mench.com | "Non si vive se non il OrCAD | www.orcad.com | tempo che si ama." P.O. Box 71767 | 919-479-1670[v] | --Claude Adrien Helvetius Durham, NC 27722-1767 | 919-479-1671[f] |Article: 14199
Has anyone had experience with using the Xilinx designed PCI core on an XC4000XVT series part? How hard was it to interface too? What sort of bandwidth was seen for large and small transfers? Also, does anyone know when a comparable IP core will be available for the Virtex? -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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