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Hal Murray <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote: (snip, I wrote) >>I suppose it makes some sense. The address decoders go to >>enable lines that enable the signal coming out of the bit >>cells onto the sense lines. If, for example, two enable lines >>were active at once then two cells would be enabled onto the >>same sense line. If the address goes metastable, it seems >>that could happen. Presumably this is true for non-FPGA RAMs, too. > Thanks, that's the hint I was fishing for. It's an unbuffered > "output". At that level, the write isn't gated. The write > driver for the sense line just overpowers the driver from the bit > and smashes the bit to the new state. If two read lines > are selected they may fight and one may "write" the other. For an asynchronous static RAM, if one changes the address inputs, there might be a short time that two decoder outputs are enabled. The designer should guarantee that the bits won't change in that time. If the address inputs float or oscillate at a very high frequency, it seems possible that the bits might not survive. That should be in an SRAM data sheet. > That doesn't require any metastability. Just setup/hold can > explain it all. Without metastability, the register outputs should switch at a known speed, and the decoder should be tested for that speed. -- glenArticle: 141926
Gints <reganireland@gmail.com> wrote: > I have an FPGA capturing binarizing an image and want to connect it to > a PC for further analysis etc. What do you think would be the best > protocol to use? The data itself is about 12.8 Mbits/second so was > leaning toward 100Mbps ethernet implemented on the FPGA. Is this > possible (plausible) without a soft processor, ie: just streaming the > images straight from the FPGA RAM? Any links to relevant readings > would be greatly appreciated so I could learn. Depending on your definition of 'soft processor.' You will need a state machine of some kind, which may or may not be considered a processor. -- glenArticle: 141927
Dear All I need your help how can i calculate log likelihood ratio (AWGN noise ) for belief propagation decoder? Thanks for youArticle: 141928
smiling as I write, but maybe I should not. a friend contacted me with an simple question: how to make a counter with xilinx coregen for Spartan-3A family. it suprised me. I checked coregen, and well it did not support S3A I did go www.xilinx.com spent 8 seconds found AR about this issue send email with the AR number to my friend case solved. just received response from my friend: he had contacted Xilinx support AND opened webcase as well but Xilinx support and WebCase personel did NOT find this Xilinx AR so, it seems that if there is such thing as "Xilinx Platinium support" then this is me ? but it doesnt make me happy, as in the cases where I need support there will be no-one to help. another thing is that Xilinx support people do get paid, I usually do not (not for finding Xilinx AR numbers when Xilinx support fails with search) hm.. but maybe Xilinx own support people do not get paid? maybe that's why they do not provide support? Antti PS I'm not that arrogant [as i may sound] well my wifes sure says its arrogance squared...Article: 141929
On Jul 16, 11:19=A0pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > >The point is that deep enough is often not a power of two and you > >may not have the block RAM to waste on the unused portion. =A0The > >control circuitry would obviously be the same size since you > >haven't reduced the number of address bits. > > I'd expect the control circuitry to be slightly larger for the > non-power-of-two case. =A0You need to wrap the address counters > at 3/4 or 7/8 rather than just letting them roll over. > > Things may get more complicated if you want signals like > almost-full, almost-empty, and half-full. > > -- > These are my opinions, not necessarily my employer's. =A0I hate spam. If you use pointers that are down counters, not up counters, the logic difference may not be much. At least synplify optimizes away the roll over bit logic that is the same result as a normal roll over (decrement from zero). In other words only the bits that do not become one will need additional logic to make the non power of two rollover work. As long as the fifo size is 2^n - 2^m, there is only one bit that does not rollover with a normal decrement from zero. Come to thinkg of it, you could also do the same thing with up counters, starting at 2^m. When the counter rolls over at 2^n, just stuff the 2^m bit. This might get more tricky with keeping track of AF, AE, HF, etc. AndyArticle: 141930
Gints wrote: > hey guys, > > I have an FPGA capturing binarizing an image and want to connect it to > a PC for further analysis etc. What do you think would be the best > protocol to use? The data itself is about 12.8 Mbits/second so was > leaning toward 100Mbps ethernet implemented on the FPGA. Is this > possible (plausible) without a soft processor, ie: just streaming the > images straight from the FPGA RAM? Any links to relevant readings > would be greatly appreciated so I could learn. > > G This is certainly reasonable if you use UDP. If you only implement ARP and UDP, the interface with a PHY chip is straighforward. There is an example of a 10Mbps aat www.fpga4fun.com. I did a 100Mbps interface without a processor for a data collection system.Article: 141931
"Nemesis" <nemesis@nowhere.invalid> wrote in message news:20090716184149.3460.49994.XPN@orion.invalid... > > I interfaced my DSP code with base code of the board (an ADC board). > I don't want to modify the original code. I think they didn't use the > Xilinx core because the fifo's depth is about 12000, Xilinx core accept > only power of 2 depths if I remember well. I am pretty sure it would be easier and an overall better solution to replace a weird FIFO than to create a weird clocking scheme. The reason they didn't use a Xilinx core could be because they wanted the code to be portable between different FPGA vendors (they might have ADC boards with different FPGAs available), which is still a bad excuse for requiring 2 phases of the same clock. In any case I doubt there's much value in their ADC interface code. You could probably interface to the ADC directly yourself. /MikhailArticle: 141932
On Jul 17, 1:24=A0am, rickman <gnu...@gmail.com> wrote: > I find there are any number of aspects of the VHDL language that I > just do not remember and I am not going to make up flash cards to help > me remember. =A0So I drag a half dozen VHDL books around with me when I > am working on VHDL (or much less frequently, Verilog; one of the books > covers both). > > I am getting tired of heaving the books up into the truck every time I > go to the lake and am starting to wonder if I should invest in some > good e-books on HDL. > > What do the rest of you prefer? =A0Do you have both? =A0Do you still need > to rely on your books or do you pretty well have the language down > pat? > > Is the IEEE VHDL standard available in e-book format? =A0Maybe I need to > invest in the 200x version anyway? > > Rick In my case it really depends. I really like all three things...paper books and e-books I think reading is much better on paper than on a PC monitor. (Here the Kindle sounds interesting, but in Austria it is not available). So I really prefer a book if I'm about to read a whole lot (e.g. book to learn a new programming language). It also has the advantage that you can have the book open, and read there while working on you code (I have two monitors, and most of the time when I'm programming VHDL or C+ + I use both monitors, so having a book is a real advantage) But If I just have to refresh my memory about something (syntax, etc.) I prefer PDFs because of their searchability. I have the few book I use the most in both forms (paper and electronic) and choose depending on mood/what I want to do which to use. AndreasArticle: 141933
AndreasWallner wrote:
> But If I just have to refresh my memory about something (syntax, etc.)
> I prefer PDFs because of their searchability.
A syntax-aware editor that proposes completions
sometimes covers these problems.
-- Mike Treseler
Article: 141934In my case I use lots and lots of books that refer to various standards, (like ATA, SATA, USB, etc). And for that I prefer eBooks. 1) I can search them with ease; 2) I can create my own bookmarks; 3) I can carry a bunch of them on a single USB drive. One important thing I learned the hard way, is to never buy "locked" eBooks. Mindshare comes to mind as one of the worst experiences (ended up buying a hard copy of a book because I could not open the eBook freely when I needed it). During development cycles, I tend to copy and paste important paragraphs from those eBooks, creating my own reference manuals for specific subjects (e.g. everything about control endpoint for USB - that information is spread over 1000+ pages of USB specification). Best Regards, rudiArticle: 141935
> > That doesn't require any metastability. =A0Just setup/hold can > > explain it all. =A0 Not true: Just violating the set-up time specification (without changing inputs during the tiny metastability-inducing window) would just create ambiguity in the decoding of the address, perhaps even a composite mixed-up address. With WE being inactive, this will never contaminate the data. The problem we are discussing here occurs only when you change address bit(s) during the femtosecond timing window that can cause the address register to go metstable, thus generate duplicate decoder outputs, and perhaps cause storage bits to kill each other.Might occur once a month or once a decade. The likelihood is extremely small, but not zero. That's why we published the warning, and the very simple and effective work-around. Peter AlfkeArticle: 141936
Does anyone know if I can run DDR1 type of memory at double the frequency of MPMC4.03 (EDK10.1) main clock? Or is this possible for DDR2 only? I am having difficult time trying to understand this from the datasheet. So, before digging into the MPMC source code I thought I would try asking... Thanks, /MikhailArticle: 141937
On Jul 15, 1:04=A0pm, Fridolin <googlegro...@47110815.com> wrote: > On Jul 14, 10:46=A0pm, AndreasWallner <Andreas.Wallner.et...@fh- > > > > > > joanneum.at> wrote: > > Hi, > > > I have a Problem getting the System ACE Controller to work. > > I try it on a Spartan 3A DSP 1800 Board, to which I connected a > > SystemACE Module from AVNet. > > > If I format the CF Card completly, and do not create any partitions > > (the drive then only contains the FAT16). > > > If I try to create two partitions (with linux fdisk, one 64MB > > Partition, and the second spanning the remaining card), format the > > first one to FAT16 and copy the exact same files to the card the > > System ACE board only displays an error and does not load the design. > > > Are there any special points to take into consideration? > > > Regards, > > Andreas > > Hi Andreas, > > look onhttp://www.xilinx.com/products/boards/ml403/reference_designs.htm > near the end of the page there is a image for the CF card with a DOS > and Linux partition. > (CF Card Image (DOS and Linux Partition)) > You can download it and view it with a Disk Editor or Uedit in binary > mode. > > Maybe you find the diffs to the Linux fdisk tool. > > Have Fun > Florian Hi, I analysed the partition table of both, my self created and the one in the image. The rest of the MBR also looked fine (as fine as a bootloader which is not there can look ;-) ) After not finding a difference (except the size-dependent parts) I copied the partition table from the image onto my CF card, formatted the first partition, and tried that one out. It also did not work. So I tried only creating one partition, which also did not work... The commands I'm using: mkdosfs -F 16 -R 1 -I /dev/sdc (for the whole disk) mkdosfs -F 16 -R 1 /dev/sdc1 (for the partition) If I create the partition table I use linux fdisk, and change the type of the partition to 0x06. I also tried axplicitly specifying different sector-per-cluster sizes, which also did not change anything. (sector-per-cluster size /=3D 1) -> mkdosfs -F 16 -R 1 -s 4 Using dd (which is btw. also available for windows) I wrote the image Fridolin mentioned to the CF card. Then I deleted all files from the card and copied my design onto it. This time it worked, it's a way to start, but I really don't think it's a way to do it all the time... Tomorrow I will try out wheter my VHDL implementation for the MPU bus works or not, if it does I will tell you the current values of the status/error/fatstat registers. But it would be really great if you could tell me how you partition/format you CF card (linux would be fine, but I would also be grateful for a windows way) Thanks AndreasArticle: 141938
On Fri, 17 Jul 2009 14:08:11 -0700, Peter Alfke wrote: >> > That doesn't require any metastability. Just setup/hold can explain >> > it all. > > Not true: > Just violating the set-up time specification (without changing inputs > during the tiny metastability-inducing window) would just create > ambiguity in the decoding of the address, perhaps even a composite > mixed-up address. With WE being inactive, this will never contaminate > the data. > > The problem we are discussing here occurs only when you change address > bit(s) during the femtosecond timing window that can cause the address > register to go metstable, thus generate duplicate decoder outputs, and > perhaps cause storage bits to kill each other.Might occur once a month > or once a decade. > The likelihood is extremely small, but not zero. That's why we published > the warning, and the very simple and effective work-around. > Peter Alfke "Once a month or once a decade" was more like once every few times I toggled the reset input on the DCM, on the particular design I tested. The probability changed from part to part. On some FPGAs, I couldn't make it happen at all. I did have hundreds of BRAMs on that clock though, and a single bit error in any of those RAMs resulted in a test failure. And yes, this was a fully synchronous design. The glitches from the DCM were sufficient to cause the timing violation. Regards, AllanArticle: 141939
On Sat, 18 Jul 2009 03:42:32 +0000, Allan Herriman wrote: > On Fri, 17 Jul 2009 14:08:11 -0700, Peter Alfke wrote: > >>> > That doesn't require any metastability. Just setup/hold can explain >>> > it all. >> >> Not true: >> Just violating the set-up time specification (without changing inputs >> during the tiny metastability-inducing window) would just create >> ambiguity in the decoding of the address, perhaps even a composite >> mixed-up address. With WE being inactive, this will never contaminate >> the data. >> >> The problem we are discussing here occurs only when you change address >> bit(s) during the femtosecond timing window that can cause the address >> register to go metstable, thus generate duplicate decoder outputs, and >> perhaps cause storage bits to kill each other.Might occur once a month >> or once a decade. >> The likelihood is extremely small, but not zero. That's why we >> published the warning, and the very simple and effective work-around. >> Peter Alfke > > "Once a month or once a decade" was more like once every few times I > toggled the reset input on the DCM, on the particular design I tested. > The probability changed from part to part. On some FPGAs, I couldn't > make it happen at all. > > I did have hundreds of BRAMs on that clock though, and a single bit > error in any of those RAMs resulted in a test failure. > > And yes, this was a fully synchronous design. The glitches from the DCM > were sufficient to cause the timing violation. > > Regards, > Allan BTW, this design has since been retired. I had a workaround which involved gating the clock for that product, and it worked ok. Newer products haven't exhibited this type of problem at all, possibly because we know to disable the ram when there is any chance of a glitch on the clock line. Regards, AllanArticle: 141940
MM wrote: > "Nemesis" <nemesis@nowhere.invalid> wrote in message > news:20090716184149.3460.49994.XPN@orion.invalid... >> >> I interfaced my DSP code with base code of the board (an ADC board). >> I don't want to modify the original code. I think they didn't use the >> Xilinx core because the fifo's depth is about 12000, Xilinx core accept >> only power of 2 depths if I remember well. > > I am pretty sure it would be easier and an overall better solution to > replace a weird FIFO than to create a weird clocking scheme. The reason they > didn't use a Xilinx core could be because they wanted the code to be > portable between different FPGA vendors (they might have ADC boards with > different FPGAs available), which is still a bad excuse for requiring 2 > phases of the same clock. > > In any case I doubt there's much value in their ADC interface code. You > could probably interface to the ADC directly yourself. At the end they use (smaller) Xilinx Fifo core to build the large one, I suppose they didn't use directly a 16k fifo core not to waste BRAMs. Anyway I don't want to play with their implementation because it contains also interface code for getting data from the FIFO on the PCI bus or another customized bus. Unfortunately I don't have the time to study their solution and modify it in a reliable way. -- It is better to deserve honors and not have them than to have them and not to deserve them. _ _ _ | \| |___ _ __ ___ __(_)___ | .` / -_) ' \/ -_|_-< (_-< |_|\_\___|_|_|_\___/__/_/__/ http://xpn.altervista.orgArticle: 141941
doug <xx@xx.com> wrote: > Gints wrote: > > hey guys, > > > > I have an FPGA capturing binarizing an image and want to connect it to > > a PC for further analysis etc. What do you think would be the best > > protocol to use? The data itself is about 12.8 Mbits/second so was > > leaning toward 100Mbps ethernet implemented on the FPGA. Is this > > possible (plausible) without a soft processor, ie: just streaming the > > images straight from the FPGA RAM? Any links to relevant readings > > would be greatly appreciated so I could learn. > > > > G > This is certainly reasonable if you use UDP. If you only implement > ARP and UDP, the interface with a PHY chip is straighforward. > There is an example of a 10Mbps aat www.fpga4fun.com. I did a > 100Mbps interface without a processor for a data collection > system. Are you willing to share? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 141942
I run into the same problem. I'm using Fedora 11 with ISE 10.1.03. Please write an email or post it here if you found a solution. Thanks. bitslipper <at> googlemail.comArticle: 141943
On Wed, 15 Jul 2009 21:00:08 +0200, Jan Pech wrote: > Is there any way how to make Xilinx FPGA Editor (and other old Wind/U > based applications) running in Fedora 11, x86_64? > > In RHEL, CentOS, and older versions of Fedora (all x86_64) it is > sufficient to set the $DISPLAY environment variable to :0 and to follow > this http://www.xilinx.com/support/answers/22022.htm answer record. > Unfortunately this does not work in F11/x86_64. > > I get the same error messages as described in the answer record but the > answer itself does not help. According to "ldd -v ..../fpga_editor" I am > not missing any required library. > > Thanks for your help, > Jan The problem is that Fedora uses lesstif instead of motif. The solution is to install a CentOS5.3 VM and run fpga_ed from there. Fedora 11 has KVM built in, if you haven't already done it just install the virtualization tools and then run virt-manager and install CentOS. You should do an NFS export of your working directories on the host machine and then do an NFS mount in the CentOS VM, that will allow you to operate on the same directories in both the F11 host and the CentOS VM. I ssh into my CentOS VM from Xemacs and run fpga editor from the ssh shell so, from a UI standpoint, things that run on the VM are indistinguishable from things that run on the host. Make sure that the NFS directories appear at the same points in the file system on both the host and the client, that way Xemacs can still do auto completion of file names and directories when you are operating from the ssh shell. KVM is the best VM option for F11. The performance of KVM is very very close to native performance with Linux VMs. I've found that Windows VMs are flaky on KVM, hopefully that will get fixed soon. VMware Server doesn't run on .29 kernels, there is a patch but it doesn't work very well. If you want to use VMware, which runs Windows VMs flawlessly and runs Linux VMs just as well as KVM, you will have to stick with Fedora 10 until VMware adds support for .29 kernels. F10 uses the .27 kernel which is fully supported by VMware.Article: 141944
John, Can you give me a few details? Will the new board be the same, or roughly the the same size as the Craignell2? What about Ethernet? We want a 10/100 PHY (best), or MAC/PHY. The reason the PHY is best for us is that I already developed a simplified MAC tuned to our processor core. It doesn't take much space and not much support code. Thanks, Larry Dingle >We have a product coming shortly based on our Craignell2 but a >development board format that might offer an alternative. If you have >a few weeks then wait and see if suits your application. > >John Adair >Enterpoint Ltd. > >On Jul 6, 2:19=A0pm, "AstroLad" <Astro...@cox.net> wrote: >> Does anyone know of anything similar to the Suzaku SZ030/SZ130? It's just >> about a perfect fit for a short production run product I'm helping a frie= >nd >> with. Perfect that is except the price. What we need is an FPGA as good o= >r >> better than a XC3S1000, 1MB or more of RAM (SRAM or SDRAM) and 100MB >> Ethernet. It does not absolutely have to be a Spartan. An Altera Cyclone = >of >> some flavor would do if the price were right. We already have a lot of >> development done using Digilent Spartan boards. We don't need the >> Microblaze as we have a CPU from OpenCores that is adequate. > >Article: 141945
Okay, FPGA Editor is starting now under Fedroa 11. First I had to install the rpm package from www.motifzone.net. Then you have to create a library link: "ln -s libXm.so.4 libXm.so.3". After that i had to install libstdc++-4.4.0-4(x86_64). Finally there was a SELinux issue: SummarySELinux is preventing _fpga_editor from loading /opt/Xilinx/ 10.1/ISE/lib/lin64/libkernel50.so which requires text relocation. Detailed DescriptionThe _fpga_editor application attempted to load / opt/Xilinx/10.1/ISE/lib/lin64/libkernel50.so which requires text relocation. This is a potential security problem. Most libraries do not need this permission. Libraries are sometimes coded incorrectly and request this permission. The SELinux Memory Protection Tests web page explains how to remove this requirement. You can configure SELinux temporarily to allow /opt/Xilinx/10.1/ISE/lib/lin64/ libkernel50.so to use relocation as a workaround, until the library is fixed. Please file a bug report against this package. Allowing AccessIf you trust /opt/Xilinx/10.1/ISE/lib/lin64/libkernel50.so to run correctly, you can change the file context to textrel_shlib_t. "chcon -t textrel_shlib_t '/opt/Xilinx/10.1/ISE/lib/lin64/ libkernel50.so'" You must also change the default file context files on the system in order to preserve them even on a full relabel. "semanage fcontext -a -t textrel_shlib_t '/opt/Xilinx/10.1/ISE/lib/ lin64/libkernel50.so'" After that FPGA Editor starts, but with several error messages: [root@mobile lin64]# fpga_editor /opt/Xilinx/10.1/ISE/bin/lin64/_fpga_editor: Symbol `_XtperDisplayList' causes overflow in R_X86_64_PC32 relocation /opt/Xilinx/10.1/ISE/bin/lin64/_fpga_editor: Symbol `_XtGetPerDisplayInput' causes overflow in R_X86_64_PC32 relocation Wind/U Error (248): Failed to connect to the registry on server mobile Warning!!: XKEYSYMDB environment variable is set to a wrong locationArticle: 141946
On Jul 17, 1:22=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > AndreasWallner wrote: > > But If I just have to refresh my memory about something (syntax, etc.) > > I prefer PDFs because of their searchability. > > A syntax-aware editor that proposes completions > sometimes covers these problems. > > =A0 =A0 -- Mike Treseler Hi, Mike. Any suggestions for an editor that proposes completions? (I'm using vim right now which does syntax highlighting.)Article: 141947
Poojan Wagh wrote: > Hi, Mike. Any suggestions for an editor that proposes completions? > (I'm using vim right now which does syntax highlighting.) I use vhdl-mode. The feature is called template insertion (electrification) For example, if I type "if " I am prompted for a boolean expression, then for a THEN keyword, etc. Press Enter any time to end the interaction. Other key features are: # Port translation (copy/paste) # Design hierarchy browser (speedbar) # Makefile generation # Word/keyword completion details here: http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.gif -- Mike TreselerArticle: 141948
anonymous anonymous <bitslipper@googlemail.com> wrote: (snip) < SummarySELinux is preventing _fpga_editor from loading /opt/Xilinx/ < 10.1/ISE/lib/lin64/libkernel50.so which requires text relocation. < Detailed DescriptionThe _fpga_editor application attempted to load / < opt/Xilinx/10.1/ISE/lib/lin64/libkernel50.so which requires text < relocation. This is a potential security problem. Most libraries do < not need this permission. Libraries are sometimes coded incorrectly < and request this permission. The SELinux Memory Protection Tests web < page explains how to remove this requirement. You can configure < SELinux temporarily to allow /opt/Xilinx/10.1/ISE/lib/lin64/ < libkernel50.so to use relocation as a workaround, until the library is < fixed. Please file a bug report against this package. Allowing < AccessIf you trust /opt/Xilinx/10.1/ISE/lib/lin64/libkernel50.so to < run correctly, you can change the file context to textrel_shlib_t. < "chcon -t textrel_shlib_t '/opt/Xilinx/10.1/ISE/lib/lin64/ < libkernel50.so'" You must also change the default file context files < on the system in order to preserve them even on a full relabel. < "semanage fcontext -a -t textrel_shlib_t '/opt/Xilinx/10.1/ISE/lib/ < lin64/libkernel50.so'" Yes, I found this previously and even sent a note to Xilinx about it. I haven't heard if there is interest in fixing it. -- glenArticle: 141949
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: > Yes, I found this previously and even sent a note to Xilinx > about it. I haven't heard if there is interest in fixing it. I fear that these note normally get lost in the dungle of first, second and higher level support. First level support dooesn't understand _anything_ from the technical things we report and perhaps "translates" the report into some other form, dropping the technical findings. Higher level doesn't understand that translation and drops probably the report or "fixed" it in some strange way, but not the real cause. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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