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Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: > glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >> Yes, I found this previously and even sent a note to Xilinx >> about it. I haven't heard if there is interest in fixing it. > I fear that these note normally get lost in the dungle of first, second and > higher level support. First level support dooesn't understand _anything_ > from the technical things we report and perhaps "translates" the report into > some other form, dropping the technical findings. Higher level doesn't > understand that translation and drops probably the report or "fixed" it in > some strange way, but not the real cause. > Most likely true. I sent it to what I was told was the right person, but maybe not. I did not follow up. At first, I (and some others) believed that it was intentional on Xilinx part not to support webpack on x86_64 machines. In my case, I ended up installing on an IA32 machine and copying the whole directory tree over. The install program won't even start, I believe due to the same effect. When actually running, the selinux message came up, but only after the system actually started running. -- glenArticle: 141951
Uwe Bonnes wrote: > doug <xx@xx.com> wrote: > > > >>Gints wrote: > > >>>hey guys, >>> >>>I have an FPGA capturing binarizing an image and want to connect it to >>>a PC for further analysis etc. What do you think would be the best >>>protocol to use? The data itself is about 12.8 Mbits/second so was >>>leaning toward 100Mbps ethernet implemented on the FPGA. Is this >>>possible (plausible) without a soft processor, ie: just streaming the >>>images straight from the FPGA RAM? Any links to relevant readings >>>would be greatly appreciated so I could learn. >>> >>>G > > >>This is certainly reasonable if you use UDP. If you only implement >>ARP and UDP, the interface with a PHY chip is straighforward. >>There is an example of a 10Mbps aat www.fpga4fun.com. I did a >>100Mbps interface without a processor for a data collection >>system. > > > Are you willing to share? Unfortunately this was done for a customer who does not want it released. But the basic idea is that you need to respond to the ARP so that a switch knows the MAC address that corresponds to the IP the PC is asking for. The phy chip gives the data in 4 bit nibbles so that needs to be made to 8 bit bytes for easier processing. I process the packet as it comes through with an address detector and then a data processor. The replies are a bit of a nuisance since the checksum for the data is in the header and, in a streaming data situation, the data comes out afterwards. There are two solutions to this. One is to put the data in a fifo and calculate the checksum as it comes in and have the packet header stored in a separate block. This way for repeated data, the header only needs to be setup once. The second way to deal with the checksum is to set it to zero, in which case, the PC ignores it. UDP is nice since it is a send and forget protocol. Particularly for local transmission, there is no need for the extra abilities and overhead of a TCP connection. We have run the system all day without losing a packet so the retries are not so important. The biggest nuisance of the whole deal was getting the CRC correct. There are online CRC calculators but troubleshooting that part is a real pain. If the CRC is wrong, the PC will not see anything so you cannot even get to see what it thought the value should be. (The checksum values are reported in Wireshark and tell you what the correct value is if you have made a mistake).Article: 141952
On Jul 16, 8:07=A0pm, Martin Thompson <martin.j.thomp...@trw.com> wrote: > Nauman Mir <m...@hotmail.com> writes: > > hi Good Day! > > =A0 I hope you all are fine. Actually i want to take some technical > > input. I want to build 10,000 floating point multiplier in FPGA > > fabric. So > > That's a lot of multipliers! =A0Unfortunately I have only more questions > for you: > > What are you doing that needs this qty of multipliers? =A0Do you really > need floating point? =A0What word size? =A0What data rate? > > > =A0> Kindly suggest me Is it possible ? > > Not taking your query at face value - a single-precision FP multiplier > from Xilinx Coregen runs to 1000 or so LUTs (IIRC), so that's a 10MLUT > FPGA... (actually, DSP blocks would probably be the limiting factor > anyway, but it's still infeasible!). =A0The largest Virtex 6 looks like > about 450k LUTs... > > Now, if you actually need to do 10,000 multiplies one after the other, > that's very different story... > > > =A0> How we can implement ? (my suggestion is MicroBlaze soft processor= ) > > Only if you want the answer realtively slowly, in which case a normal > processor rather than an FPGA would better suit the problem. =A0That woul= d > also be a sequential solution. > > > =A0> Which Chip_Set is best for this purpose ? > > Insufficient data. =A0sorry! > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.net/electronics.html Thanks for your concern ......... > word size is 8-bit > Definatly i necer lose precession so that i use Floating point > I want to do this maximum in 13Cycles , after pipeline > I want to do this all Concurrently > i use this in image matching algorithm for medical machine development Best Regards Nauman MirArticle: 141953
I am toying with the idea of reimplenting a 2901 based CPU inside a FPGA. As a hobbyproject i would like to keep it as simple as possible , i.e. low pinout count, no BGA packages. What are my options of storing the bitslice microcode ( 2K x 40 bits ) ? External Eproms is simple, but too slow and too expensive in IO count. JosArticle: 141954
On Jul 19, 2:05=A0pm, Jos Dreesen <jos.dree...@bluewin.ch> wrote: > I am toying with the idea of reimplenting a 2901 based CPU inside a FPGA. > As a hobbyproject i would like to keep it as simple as possible , i.e. lo= w pinout count, no BGA packages. > > What are my options of storing the bitslice microcode ( 2K x 40 bits ) ? > External Eproms is simple, but too slow and too expensive in IO count. > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Jos brams, need 3 of them (if xilinx) for 40x 2k AnttiArticle: 141955
http://groups.google.com/group/antti-brain?hl=en uploaded ready to test bit file for spartan3a kit (need put small wire into SMA for antenna) AnttiArticle: 141956
Gints : > hey guys, > I have an FPGA capturing binarizing an image and want to connect it to > a PC for further analysis etc. What do you think would be the best > protocol to use? The data itself is about 12.8 Mbits/second so was > leaning toward 100Mbps ethernet implemented on the FPGA. Is this > possible (plausible) without a soft processor, ie: just streaming the > images straight from the FPGA RAM? Any links to relevant readings > would be greatly appreciated so I could learn. Hi, We do have developed a module doing just this (streaming data both ways through Ethernet). No processor, no SW stack, no external memory, no MAC, no SGDMA, no RTOS... all is included in our very compact IP, including the PC side SW. Note that it is affordable but it's NOT free. 12.8 Mbits is : * clearly out of reach for USB 1.1 like for FTDI Fifo or RS versions (2232 or 4232 OTOH). * Perfect for Fast Ethernet (100M). You just need an external Phy and our module which takes care of everything. We deliver a simple API on the PC side (source code) but you can write your own (simple sockets programming). Demonstrators are available in many FPGA technologies and commercial boards. If you have a budget and need a quick (integration takes usually less than one day) and efficient solution, contact us: info at alse-fr not calm. :-) BertArticle: 141957
Poojan Wagh wrote:
> On Jul 17, 1:22 pm, Mike Treseler <mtrese...@gmail.com> wrote:
>> AndreasWallner wrote:
>>> But If I just have to refresh my memory about something (syntax, etc.)
>>> I prefer PDFs because of their searchability.
>> A syntax-aware editor that proposes completions
>> sometimes covers these problems.
>>
>> -- Mike Treseler
>
> Hi, Mike. Any suggestions for an editor that proposes completions?
> (I'm using vim right now which does syntax highlighting.)
The modern answer, already popular for general programming, is an
intelligent development devironment, typically based on Eclipse.
This is now also available for VHDL. Sigasi HDT is not just syntax-aware,
but fully aware of your ongoing VHDL design. Try it out here:
http://www.sigasi.com/
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com
Article: 141958On Sat, 2009-07-18 at 06:36 -0700, anonymous anonymous wrote: > Okay, FPGA Editor is starting now under Fedroa 11. First I had to > install the rpm package from www.motifzone.net. Then you have to > create a library link: "ln -s libXm.so.4 libXm.so.3". After that i had > to install libstdc++-4.4.0-4(x86_64). Finally there was a SELinux > issue: > > SummarySELinux is preventing _fpga_editor from loading /opt/Xilinx/ > 10.1/ISE/lib/lin64/libkernel50.so which requires text relocation. > Detailed DescriptionThe _fpga_editor application attempted to load / > opt/Xilinx/10.1/ISE/lib/lin64/libkernel50.so which requires text > relocation. This is a potential security problem. Most libraries do > not need this permission. Libraries are sometimes coded incorrectly > and request this permission. The SELinux Memory Protection Tests web > page explains how to remove this requirement. You can configure > SELinux temporarily to allow /opt/Xilinx/10.1/ISE/lib/lin64/ > libkernel50.so to use relocation as a workaround, until the library is > fixed. Please file a bug report against this package. Allowing > AccessIf you trust /opt/Xilinx/10.1/ISE/lib/lin64/libkernel50.so to > run correctly, you can change the file context to textrel_shlib_t. > "chcon -t textrel_shlib_t '/opt/Xilinx/10.1/ISE/lib/lin64/ > libkernel50.so'" You must also change the default file context files > on the system in order to preserve them even on a full relabel. > "semanage fcontext -a -t textrel_shlib_t '/opt/Xilinx/10.1/ISE/lib/ > lin64/libkernel50.so'" > > After that FPGA Editor starts, but with several error messages: > > [root@mobile lin64]# fpga_editor > /opt/Xilinx/10.1/ISE/bin/lin64/_fpga_editor: Symbol > `_XtperDisplayList' causes overflow in R_X86_64_PC32 relocation > /opt/Xilinx/10.1/ISE/bin/lin64/_fpga_editor: Symbol > `_XtGetPerDisplayInput' causes overflow in R_X86_64_PC32 relocation > Wind/U Error (248): Failed to connect to the registry on server mobile > > Warning!!: XKEYSYMDB environment variable is set to a wrong location > I have libstdc++ installed as well as openmotif. The SELinux is disabled in all my desktop installations as it brings more problems than benefits. Still I cannot start the fpga_editor at all. I am getting one more additional error compared to you: Wind/U Error (193): X-Resource: DefaultGUIFontSpec (-*-helvetica-medium-r-normal-*-14-*) does not fully specify a font set for this locale Could that be the problem? JanArticle: 141959
On Sun, 19 Jul 2009 18:39:46 +0200, Bert_Paris <do_not_spam_@me> wrote: >Gints : >> hey guys, >> I have an FPGA capturing binarizing an image and want to connect it to >> a PC for further analysis etc. What do you think would be the best >> protocol to use? The data itself is about 12.8 Mbits/second so was >> leaning toward 100Mbps ethernet implemented on the FPGA. Is this >> possible (plausible) without a soft processor, ie: just streaming the >> images straight from the FPGA RAM? Any links to relevant readings >> would be greatly appreciated so I could learn. > >Hi, > >We do have developed a module doing just this (streaming data both ways >through Ethernet). No processor, no SW stack, no external memory, no >MAC, no SGDMA, no RTOS... all is included in our very compact IP, >including the PC side SW. >Note that it is affordable but it's NOT free. > >12.8 Mbits is : >* clearly out of reach for USB 1.1 like for FTDI Fifo or RS versions >(2232 or 4232 OTOH). FYI I've just been playing with the FT2232H for outputting from the PC to an FPGA, and this will sustain 20MBytes/second one-way. This is in parallel sync mode - the async modes are constrained by the async bus timing.Article: 141960
I'm doing a project in Lattice ISPLever ( which bears uncanny similarities to Xilinx ISE), which may end up having several product variants, and was wondering how people typically handle compile-time build variants for different product functionalities? The sort of thing that if it was C software, you'd do it easily with #includes, #defines and #ifdefs, but for reasons I can't understand, VHDL doesn't have anything like these simple preprocessor functions. Although HDLs are very different from programming languages, a preprocessor would be equally useful & it seems ridiculous that nobody thought to include one in the standard. Is there a simple way to 'add' a C style preprocessor to the build process?Article: 141961
Nauman Mir <mir6@hotmail.com> writes: > > Thanks for your concern ......... > > >> word size is 8-bit >> Definatly i necer lose precession so that i use Floating point If you mean "precision" then floating point doesn't gain you precision. It gains you dynamic range. Image processing is usually better done with fixed-point arithmetic, as the inputs are all such constrained values (ie 0-255 in your case) >> I want to do this maximum in 13Cycles , after pipeline >> I want to do this all Concurrently >> i use this in image matching algorithm for medical machine development > So, you are trying to correlate a 100x100 patch of an image with something that is pre-stored for comparison? There's probably a better way than brute-force correlation, but it will need more details of your application... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 141962
Hi! What I usually do is to write a package that I include with "use" in all my VHDL code files. The package contains constants (for instance natural numbers) that determine the functionality of the model. In the VHDL model itself you then have to write something like label_1: if USE_THIS_FEATURE = 0 generate end generate; label_2: if USE_THIS_FEATURE = 1 generate end generate; and so on. Synthesis and simulation will only include the statements you want. Matthias Mike Harrison schrieb: > I'm doing a project in Lattice ISPLever ( which bears uncanny similarities to Xilinx ISE), which may > end up having several product variants, and was wondering how people typically handle compile-time > build variants for different product functionalities? > > The sort of thing that if it was C software, you'd do it easily with #includes, #defines and > #ifdefs, but for reasons I can't understand, VHDL doesn't have anything like these simple > preprocessor functions. > Although HDLs are very different from programming languages, a preprocessor would be equally useful > & it seems ridiculous that nobody thought to include one in the standard. > > Is there a simple way to 'add' a C style preprocessor to the build process?Article: 141963
"Mike Harrison" <mike@whitewing.co.uk> wrote in message news:2lb865tncrvum6jn7uu24ohop7ruatvaiq@4ax.com... > I'm doing a project in Lattice ISPLever ( which bears uncanny similarities > to Xilinx ISE), which may > end up having several product variants, and was wondering how people > typically handle compile-time > build variants for different product functionalities? > > The sort of thing that if it was C software, you'd do it easily with > #includes, #defines and > #ifdefs, but for reasons I can't understand, VHDL doesn't have anything > like these simple > preprocessor functions. > Although HDLs are very different from programming languages, a > preprocessor would be equally useful > & it seems ridiculous that nobody thought to include one in the standard. > > Is there a simple way to 'add' a C style preprocessor to the build > process? Hi Mike, I think VHDL does have these things, and they're called generics, used along with generate, but I wouldn't claim any expertise in VHDL so you could try asking over on comp.lang.vhdl . I'm sure Jonathan, Mike et al will give you good advice. HTH., Syms.Article: 141964
On Mon, 20 Jul 2009 10:10:01 +0200, Jan Pech wrote: > On Sat, 2009-07-18 at 06:36 -0700, anonymous anonymous wrote: >> Okay, FPGA Editor is starting now under Fedroa 11. First I had to >> install the rpm package from www.motifzone.net. Then you have to create >> a library link: "ln -s libXm.so.4 libXm.so.3". After that i had to >> install libstdc++-4.4.0-4(x86_64). Finally there was a SELinux issue: >> >> SummarySELinux is preventing _fpga_editor from loading /opt/Xilinx/ >> 10.1/ISE/lib/lin64/libkernel50.so which requires text relocation. >> Detailed DescriptionThe _fpga_editor application attempted to load / >> opt/Xilinx/10.1/ISE/lib/lin64/libkernel50.so which requires text >> relocation. This is a potential security problem. Most libraries do not >> need this permission. Libraries are sometimes coded incorrectly and >> request this permission. The SELinux Memory Protection Tests web page >> explains how to remove this requirement. You can configure SELinux >> temporarily to allow /opt/Xilinx/10.1/ISE/lib/lin64/ libkernel50.so to >> use relocation as a workaround, until the library is fixed. Please file >> a bug report against this package. Allowing AccessIf you trust >> /opt/Xilinx/10.1/ISE/lib/lin64/libkernel50.so to run correctly, you can >> change the file context to textrel_shlib_t. "chcon -t textrel_shlib_t >> '/opt/Xilinx/10.1/ISE/lib/lin64/ libkernel50.so'" You must also change >> the default file context files on the system in order to preserve them >> even on a full relabel. "semanage fcontext -a -t textrel_shlib_t >> '/opt/Xilinx/10.1/ISE/lib/ lin64/libkernel50.so'" >> >> After that FPGA Editor starts, but with several error messages: >> >> [root@mobile lin64]# fpga_editor >> /opt/Xilinx/10.1/ISE/bin/lin64/_fpga_editor: Symbol `_XtperDisplayList' >> causes overflow in R_X86_64_PC32 relocation >> /opt/Xilinx/10.1/ISE/bin/lin64/_fpga_editor: Symbol >> `_XtGetPerDisplayInput' causes overflow in R_X86_64_PC32 relocation >> Wind/U Error (248): Failed to connect to the registry on server mobile >> >> Warning!!: XKEYSYMDB environment variable is set to a wrong location >> >> > I have libstdc++ installed as well as openmotif. The SELinux is disabled > in all my desktop installations as it brings more problems than > benefits. Still I cannot start the fpga_editor at all. I am getting one > more additional error compared to you: > > Wind/U Error (193): X-Resource: DefaultGUIFontSpec > (-*-helvetica-medium-r-normal-*-14-*) does not fully specify a font set > for this locale > > Could that be the problem? > > Jan Add the xorg-x11 fonts packages.Article: 141965
On Jul 20, 4:51=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > I'm doing a project in Lattice ISPLever ( which bears uncanny similaritie= s to Xilinx ISE), which may > end up having several product variants, and was wondering how people typi= cally handle compile-time > build variants for different product functionalities? > With generics and constants in packages. > The sort of thing that if it was C software, you'd do it easily with #inc= ludes, #defines and > #ifdefs, but for reasons I can't understand, VHDL doesn't have anything l= ike these simple > preprocessor functions. Because they're not needed. > Although HDLs are very different from programming languages, a preprocess= or would be equally useful > & it seems ridiculous that nobody thought to include one in the standard. > Design parameters are handled quite well without any pre-processor. > Is there a simple way to 'add' a C style preprocessor to the build proces= s? I'm sure there is...but try using the facilities of the language first and then come back with examples of something that can be done only with a pre-processor KJArticle: 141966
Hi, I have a Spartan3AN xc3s1400AN FPGA board. There are externally devices connected to the FPGA on the board. One of the external devices is a TMS320DM6446 TI DSP connected to this FPGA with its EMIF bus interface. Other external devices are memory mapped to this TI DSP. The access to these external devices from the DSP are provided through the FPGA. For this, a simple Verilog framework has been written where interfaces to all these external devices are written and connected to the EMIF bus. In addition to these memory mapped devices, one 16-bit register has also been memory mapped inside the FPGA. The Verilog framework has been tested and verified in simulation. On one of the FPGA boards with exact specs, the same Verilog framework runs with no problem and the DSP can write and read all memory mapped devices with no problem including the 16-bit register inside FPGA. However, when the same Verilog code is programmed on another similar FPGA board (exactly the same), there is one issue. Before describing the issue, I must inform that the board has been thoroughly tested for all voltage levels being provided to the FPGA (core/IO voltages). The EMIF successfully writes and reads external devices. However, it fails to write and read the 16-bit memory mapped register. The register is designed to drive the LEDs with the value written into it. On this FPGA board, the LEDs do not change their state from the default condition for any value written into this register from the DSP. To further investigate, ChipScope Pro cores were inserted to see transactions taking place on EMIF bus. It was observed that valid values were traveling into the FPGA on EMIF pins and proper bus protocol was taking place. In the next phase, CSP cores were hooked up with the 16-bit register and it was observed that the register was not latching the value at its input and does not change from its initial state. In the next phase, the LEDs were removed from the design and synthesized. Now the value written into the register will not drive the LEDs as they are disconnected. When analyzed with CSP, it was observed that the register is latching the value properly. In the next level, the same register output was connected to other set of GPIOs, the problem re-appeared again. It seems as if there is problem whenever this register is connected to GPIO. Here it is important to note that the same code with all changes of CSP cores works perfectly fine on the other FPGA board with same specs. Is the FPGA damaged? Is there any way to find out that? Any suggestions how to fix this problem?Article: 141967
> > I have libstdc++ installed as well as openmotif. The SELinux is disabled > > in all my desktop installations as it brings more problems than > > benefits. Still I cannot start the fpga_editor at all. I am getting one > > more additional error compared to you: > > > > Wind/U Error (193): X-Resource: DefaultGUIFontSpec > > (-*-helvetica-medium-r-normal-*-14-*) does not fully specify a font set > > for this locale > > > > Could that be the problem? > > > > Jan > > Add the xorg-x11 fonts packages. Thank you, this was the problem. The old X11 fonts are not installed in Fedora 11 by default. JanArticle: 141968
On Jul 20, 2:20=A0pm, maverick <sheikh.m.far...@gmail.com> wrote: > Hi, I have a Spartan3AN xc3s1400AN FPGA board. There are externally > devices connected to the FPGA on the board. One of the external > devices is a TMS320DM6446 TI DSP connected to this FPGA with its EMIF > bus interface. Other external devices are memory mapped to this TI > DSP. The access to these external devices from the DSP are provided > through the FPGA. For this, a simple Verilog framework has been > written where interfaces to all these external devices are written and > connected to the EMIF bus. In addition to these memory mapped devices, > one 16-bit register has also been memory mapped inside the FPGA. The > Verilog framework has been tested and verified in simulation. On one > of the FPGA boards with exact specs, the same Verilog framework runs > with no problem and the DSP can write and read all memory mapped > devices with no problem including the 16-bit register inside FPGA. > However, when the same Verilog code is programmed on another similar > FPGA board (exactly the same), there is one issue. Before describing > the issue, I must inform that the board has been thoroughly tested for > all voltage levels being provided to the FPGA (core/IO voltages). > The EMIF successfully writes and reads external devices. However, it > fails to write and read the 16-bit memory mapped register. The > register is designed to drive the LEDs with the value written into it. > On this FPGA board, the LEDs do not change their state from the > default condition for any value written into this register from the > DSP. To further investigate, ChipScope Pro cores were inserted to see > transactions taking place on EMIF bus. It was observed that valid > values were traveling into the FPGA on EMIF pins and proper bus > protocol was taking place. In the next phase, CSP cores were hooked up > with the 16-bit register and it was observed that the register was not > latching the value at its input and does not change from its initial > state. In the next phase, the LEDs were removed from the design and > synthesized. Now the value written into the register will not drive > the LEDs as they are disconnected. When analyzed with CSP, it was > observed that the register is latching the value properly. In the next > level, the same register output was connected to other set of GPIOs, > the problem re-appeared again. It seems as if there is problem > whenever this register is connected to GPIO. Here it is important to > note that the same code with all changes of CSP cores works perfectly > fine on the other FPGA board with same specs. Is the FPGA damaged? Is > there any way to find out that? Any suggestions how to fix this > problem? the useal suspects clock reset but if all signal are the same all vccio and vccint vccaux are the same including NOISE levels on supply !! then well, power supply spikes CAN damage FPGA fabric its very unlikely but can not be excluded fully but if you have only one failing board just place it into trash bin and use the other ones :) cheaper then troubleshooting of course if it comes as systematic error its bad then AnttiArticle: 141969
On Mon, 20 Jul 2009 13:35:52 +0200, Jan Pech wrote: >> > I have libstdc++ installed as well as openmotif. The SELinux is >> > disabled in all my desktop installations as it brings more problems >> > than benefits. Still I cannot start the fpga_editor at all. I am >> > getting one more additional error compared to you: >> > >> > Wind/U Error (193): X-Resource: DefaultGUIFontSpec >> > (-*-helvetica-medium-r-normal-*-14-*) does not fully specify a font >> > set for this locale >> > >> > Could that be the problem? >> > >> > Jan >> >> Add the xorg-x11 fonts packages. > > Thank you, this was the problem. The old X11 fonts are not installed in > Fedora 11 by default. > Jan I ran into that problem with Xemacs. They've added the dependency to the Xemacs package, that might still be in testing.Article: 141970
Mike Harrison schrieb: > I'm doing a project in Lattice ISPLever ( which bears uncanny similarities to Xilinx ISE), which may > end up having several product variants, and was wondering how people typically handle compile-time > build variants for different product functionalities? > Hi Mike, I have had to do this in a number of situations. Typical case: if I do a PCIe design for a customer, I evaluate on the the Lattice PCIe Demo board (ECP2M/50) but the customer often uses a different device (ECP2M/20 or ECP2M/35) I haven't found a way of assigning top-level generics at synthesis time in ispLever (I'm not saying there isn't a way). So I do all the configuration one level below. Each 'variant' has it's own top-level entity and architecture, everything else is common. I generate the project files (*.syn) under Linux (java script) so it's very easy to keep them all in sync if I change the structure a bit during development. Essentially, the *.syn files differ only in the package chosen and in the files read in as top-level entity/architecture. I put the pinning as 'LOC' attributes in the top-level entity btw. The top-level entity/architecture has all busses split into single signals and takes care of any polarity inversion for active-low signals, enables for bidirectionals etc. The only module instanced in the top-level architecture is my 'core' unit. It is essentially the same as the top-level unit except: - input / output polarity is always active high (makes viewing of simulation traces easier - if it's true it's a one) - no bidirectional ports - busses are declared as std_logic_vector, occasionally as records - contains generic ports passed into the design below. I use these to configure things like FIFO sizes, no. of DMA channels, whatever If needed, I have a separate constraint file for each variant. Each variant has it's own script sub-directory (if there are differences). To synthesise, I just copy the project (*.syn), constaint (*.lpf), ispVM (*.xcf) and possibly environment (*.sty) into my ispLever work directory and let it run. Works a treat.Article: 141971
Mike Harrison wrote: > The sort of thing that if it was C software, you'd do it easily with #includes, #defines and > #ifdefs, but for reasons I can't understand, VHDL doesn't have anything like these simple > preprocessor functions. Plain vhdl constants work fine for this. I put them in a package. -- Mike TreselerArticle: 141972
On Jul 20, 10:19=A0am, Mike Treseler <mtrese...@gmail.com> wrote: > Mike Harrison wrote: > > The sort of thing that if it was C software, you'd do it easily with #i= ncludes, #defines and > > #ifdefs, but for reasons I can't understand, VHDL doesn't have anything= like these simple > > preprocessor functions. > > Plain vhdl constants work fine for this. > I put them in a package. > > =A0 -- Mike Treseler I combine a package and generics. Define a record type for the generics I will need in a package. Every entity has one generic of that record type. If I need to add a generic at the top, that only gets used down deep in the hierarchy, I only have to add it to the record, define it at the top, and extract it down where it is needed. No additional plumbing modifications are necessary. The package of constants works almost as well, except the only way to change the value(s) is to edit (or swap) the package file. Generics can be changed by the synthesis or simulation tool. Using a record simplifies the generic "plumbing" almost as well as a package of constants, while keeping the tool-based flexibility of the generics. Depending on the complexity of your project, either a record of generics or a package of constants may work just as well, and be simpler to implement. AndyArticle: 141973
On Jul 20, 6:20=A0pm, maverick <sheikh.m.far...@gmail.com> wrote: > Hi, I have a Spartan3AN xc3s1400AN FPGA board. There are externally ... Sounds like a timing problem. Intermediate failures are usually timing related. Did you verify the timing of write data, internal write enable and clock signals ? Remember that ChipScope might not be of a lot of help with timing errors. It will in most cases hide that type of error. Try a pencil and a piece of paper, draw out what you think it should do and double check against what it is actually doing. Where is the clock coming from, the DSP ? Do you cancel out the clock buffer delay before you use it for the LED register ? Good Luck, rudiArticle: 141974
Larry The size of the board is about 67.5mm x 96.5mm. It is a lot bigger than the related Craignell2 because it has expansion headers, usb, display, accelerometer that make it bigger. The board has our standard dil header arrangement that you can see on several of our boards and we do have a phy module for these headers so you can probably have the configuration you want asumig the size meets the requirement. John Adair Enterpoint Ltd. On 18 July, 14:25, "AstroLad" <Astro...@cox.net> wrote: > John, > > Can you give me a few details? Will the new board be the same, or roughly > the the same size as the Craignell2? What about Ethernet? We want a 10/100 > PHY (best), or MAC/PHY. The reason the PHY is best for us is that I already > developed a simplified MAC tuned to our processor core. It doesn't take > much space and not much support code. > > Thanks, > > Larry Dingle > > > > > > >We have a product coming shortly based on our Craignell2 but a > >development board format that might offer an alternative. If you have > >a few weeks then wait and see if suits your application. > > >John Adair > >Enterpoint Ltd. > > >On Jul 6, 2:19=A0pm, "AstroLad" <Astro...@cox.net> wrote: > >> Does anyone know of anything similar to the Suzaku SZ030/SZ130? It's > just > >> about a perfect fit for a short production run product I'm helping a > frie= > >nd > >> with. Perfect that is except the price. What we need is an FPGA as good > o= > >r > >> better than a XC3S1000, 1MB or more of RAM (SRAM or SDRAM) and 100MB > >> Ethernet. It does not absolutely have to be a Spartan. An Altera > Cyclone = > >of > >> some flavor would do if the price were right. We already have a lot of > >> development done using Digilent Spartan boards. We don't need the > >> Microblaze as we have a CPU from OpenCores that is adequate.- Hide quoted text - > > - Show quoted text -
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