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On Tue, 28 Jul 2009 15:12:35 -0700, "Joel Koltner" <zapwireDASHgroups@yahoo.com> wrote: >> http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif > >Interesting, indeed. > >Cypress had viable products but I'm convinced that management was the problem. >(I also remember they wanted a rather large premium for their CPLDs that were >sometimes only marginally better than the competition's.) > >I don't know what Vantis's problem was, but at least after Lattive bought them >they kept a few of the parts around. > >Intel doesn't have its heart in much of anything but their desktop CPUs -- >they consistently bring out interesting products and then discontinue them >just when they're starting to gain traction. > >You're pretty much a pure Xilinx man these days, aren't you, John? > > Yes, although I occasionally use a 22V10 for glue logic and such. We've used MMI, Gould/AMI, Actel, TI, and Lattice in the past. We've been meaning to start using some CoolRunner type CPLDs for various things, but no compelling application has come up. Where the hell are the Spartan 6's? Nobody will tell me when we can get some. Sales reps fall off the face of the Earth when you ask that question. The best I can get is "available for purchase in September" and nobody knows what that means. JohnArticle: 142201
On Tue, 28 Jul 2009 15:12:35 -0700, "Joel Koltner" <zapwireDASHgroups@yahoo.com> wrote: >> http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif > >Interesting, indeed. > >Cypress had viable products but I'm convinced that management was the problem. >(I also remember they wanted a rather large premium for their CPLDs that were >sometimes only marginally better than the competition's.) Cypress' PSOC-3/5 looks quite interesting. If they had a better DAC I'd probably use it. The Avenet rep is coming tomorrow with feedback from the last meeting with the Cypress engineers, so we'll see. >I don't know what Vantis's problem was, but at least after Lattive bought them >they kept a few of the parts around. > >Intel doesn't have its heart in much of anything but their desktop CPUs -- >they consistently bring out interesting products and then discontinue them >just when they're starting to gain traction. > >You're pretty much a pure Xilinx man these days, aren't you, John? Up until now I've been all Xilinx, but I'm just starting an Altera design. I was on the fence between Altera and Actel, but the support from Altera pushed them over the edge. I may still go to Actel down the road.Article: 142202
On Tue, 28 Jul 2009 19:03:57 -0500, krw <krw@att.bizzzzzzzzzzz> wrote: >On Tue, 28 Jul 2009 15:12:35 -0700, "Joel Koltner" ><zapwireDASHgroups@yahoo.com> wrote: > >>> http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif >> >>Interesting, indeed. >> >>Cypress had viable products but I'm convinced that management was the problem. >>(I also remember they wanted a rather large premium for their CPLDs that were >>sometimes only marginally better than the competition's.) > >Cypress' PSOC-3/5 looks quite interesting. If they had a better DAC >I'd probably use it. The Avenet rep is coming tomorrow with feedback >from the last meeting with the Cypress engineers, so we'll see. > >>I don't know what Vantis's problem was, but at least after Lattive bought them >>they kept a few of the parts around. >> >>Intel doesn't have its heart in much of anything but their desktop CPUs -- >>they consistently bring out interesting products and then discontinue them >>just when they're starting to gain traction. >> >>You're pretty much a pure Xilinx man these days, aren't you, John? > >Up until now I've been all Xilinx, but I'm just starting an Altera >design. I was on the fence between Altera and Actel, but the support >from Altera pushed them over the edge. I may still go to Actel down >the road. I use Xilinx because Peter Alfke told me to! JohnArticle: 142203
"krw" <krw@att.bizzzzzzzzzzz> wrote in message news:f54v659bdn0dpu5gecp9jn6amibvaeaqv0@4ax.com... > I was on the fence between Altera and Actel, but the support > from Altera pushed them over the edge. I may still go to Actel down > the road. I've used small Altera CPLDs without any problems, but not any of the real FPGAs. At work we use Actel FPGAs and they've always worked fine... although our designs aren't at all demanding either (e.g., I/O expanders, sometimes a bit of serial protocol conversion like RS-232 to I2C, etc.). The more demanding stuff does end up in Xilinx...Article: 142204
On Jul 28, 3:12=A0pm, "Joel Koltner" <zapwireDASHgro...@yahoo.com> wrote: > >http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif > > Interesting, indeed. > > Cypress had viable products but I'm convinced that management was the pro= blem. > (I also remember they wanted a rather large premium for their CPLDs that = were > sometimes only marginally better than the competition's.) I really liked the 37Cxxx series. They appeared fit a lot more per flipflop than the other brands. I designed them into something so naturally Cypress went out the business. I am still batting 1000 on every CPLD I design in going away after the ink is dry.Article: 142205
On Jul 29, 9:52=A0am, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif As a PLD history goes, someone was a tad lazy there.... * No mention of Triscend. * TI did not get out of PLD's in '92 - they still show 82 PLD devices on their web site in 2009! * ICT steps are missing from the time line (Gould -> ICT-> Anachip- >DiodesInc -> EOL? ) * Some timelines were renames, so (eg) vantis are not really a 'startup' * WSI devices live on under ST's PSDxx families. Atmel's FPGA (&FPSLIC) business may be in run-out mode, but their SPLD/ CPLD line is still (just?) viable (helped by others closing..), and the new CAP series Arms fill a safe niche. http://en.wikipedia.org/wiki/Programmable_Array_LogicArticle: 142206
It seems that most designers are strongly polarized with respect to which programmable logic company should be used for designs. Altera, Xilinx and Lattice are supposedly the "Big Three" companies. For example, JVC uses Xilinx in professional video products: http://www.xilinx.com/prs_rls/design_win/06123jvc.htm Alternately, Panasonic uses Altera: http://www.altera.com/corporate/news_room/releases/2009/products/nr-panasonic_nab.html I would wonder which is better to use for designs, and if the history of design has a role to play in selection. Note that the chart shows that most programmable logic companies started up around the same time.Article: 142207
On Tue, 28 Jul 2009 17:30:50 -0700, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On Tue, 28 Jul 2009 19:03:57 -0500, krw <krw@att.bizzzzzzzzzzz> wrote: > >>On Tue, 28 Jul 2009 15:12:35 -0700, "Joel Koltner" >><zapwireDASHgroups@yahoo.com> wrote: >> >>>> http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif >>> >>>Interesting, indeed. >>> >>>Cypress had viable products but I'm convinced that management was the problem. >>>(I also remember they wanted a rather large premium for their CPLDs that were >>>sometimes only marginally better than the competition's.) >> >>Cypress' PSOC-3/5 looks quite interesting. If they had a better DAC >>I'd probably use it. The Avenet rep is coming tomorrow with feedback >>from the last meeting with the Cypress engineers, so we'll see. >> >>>I don't know what Vantis's problem was, but at least after Lattive bought them >>>they kept a few of the parts around. >>> >>>Intel doesn't have its heart in much of anything but their desktop CPUs -- >>>they consistently bring out interesting products and then discontinue them >>>just when they're starting to gain traction. >>> >>>You're pretty much a pure Xilinx man these days, aren't you, John? >> >>Up until now I've been all Xilinx, but I'm just starting an Altera >>design. I was on the fence between Altera and Actel, but the support >>from Altera pushed them over the edge. I may still go to Actel down >>the road. > > >I use Xilinx because Peter Alfke told me to! Actually, that's not a bad reason. In my case the Altera FAE is hungrier. Any of the cheap FPGAs will do the job.Article: 142208
On Tue, 28 Jul 2009 17:36:52 -0700, "Joel Koltner" <zapwireDASHgroups@yahoo.com> wrote: >"krw" <krw@att.bizzzzzzzzzzz> wrote in message >news:f54v659bdn0dpu5gecp9jn6amibvaeaqv0@4ax.com... >> I was on the fence between Altera and Actel, but the support >> from Altera pushed them over the edge. I may still go to Actel down >> the road. > >I've used small Altera CPLDs without any problems, but not any of the real >FPGAs. > >At work we use Actel FPGAs and they've always worked fine... although our >designs aren't at all demanding either (e.g., I/O expanders, sometimes a bit >of serial protocol conversion like RS-232 to I2C, etc.). That's the sort of stuff I'll be doing, mostly. >The more demanding stuff does end up in Xilinx... From what I read, Altera and Xilinx are pretty competitive at the top end too. That said, I always used Xilinx for that stuff too. The first time because 'X' had the I/O's (1.2V) I needed and the last time because that's what I was paid to use. ;-)Article: 142209
On Tue, 28 Jul 2009 20:35:27 -0500, krw <krw@att.bizzzzzzzzzzz> wrote: >On Tue, 28 Jul 2009 17:30:50 -0700, John Larkin ><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>On Tue, 28 Jul 2009 19:03:57 -0500, krw <krw@att.bizzzzzzzzzzz> wrote: >> >>>On Tue, 28 Jul 2009 15:12:35 -0700, "Joel Koltner" >>><zapwireDASHgroups@yahoo.com> wrote: >>> >>>>> http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif >>>> >>>>Interesting, indeed. >>>> >>>>Cypress had viable products but I'm convinced that management was the problem. >>>>(I also remember they wanted a rather large premium for their CPLDs that were >>>>sometimes only marginally better than the competition's.) >>> >>>Cypress' PSOC-3/5 looks quite interesting. If they had a better DAC >>>I'd probably use it. The Avenet rep is coming tomorrow with feedback >>>from the last meeting with the Cypress engineers, so we'll see. >>> >>>>I don't know what Vantis's problem was, but at least after Lattive bought them >>>>they kept a few of the parts around. >>>> >>>>Intel doesn't have its heart in much of anything but their desktop CPUs -- >>>>they consistently bring out interesting products and then discontinue them >>>>just when they're starting to gain traction. >>>> >>>>You're pretty much a pure Xilinx man these days, aren't you, John? >>> >>>Up until now I've been all Xilinx, but I'm just starting an Altera >>>design. I was on the fence between Altera and Actel, but the support >>>from Altera pushed them over the edge. I may still go to Actel down >>>the road. >> >> >>I use Xilinx because Peter Alfke told me to! > >Actually, that's not a bad reason. In my case the Altera FAE is >hungrier. Any of the cheap FPGAs will do the job. I was foraging through a box of old books at the Foothill Flea Market when I noticed another head in the box. It was Peter's. We started talking and I walked away a Xilinx convert. JohnArticle: 142210
John Larkin wrote: > http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif > > > John > Saw that in one of the trade mags i got. Prolly makes some of the investors a BIT nervous...Article: 142211
On Jul 28, 5:52=A0pm, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif > > John Looks a bit heavy-handed with the "out of business" designation. Most of those listed were bought out at some point, and some of those products live on under a new masthead. Still pretty cool as you noted. Regards, GaborArticle: 142212
On Jul 28, 5:14=A0pm, Mike Harrison <m...@whitewing.co.uk> wrote: > On Tue, 28 Jul 2009 08:46:07 -0700 (PDT), gabor <ga...@alacron.com> wrote= : > >On Jul 28, 5:42=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > >> On Tue, 28 Jul 2009 10:50:48 +0200, Charles Gardiner <inva...@invalid.= invalid> wrote: > >> >Hi Mike, > > >> >at what frequency is your SPI running. You can configure this in the > >> >*.lpf file or of course in the Design Planner. The actual frequency u= sed > >> >is process/batch dependent since it uses an internal PLL. I think > >> >Lattice have specified an inaccuracy of 30%. Does it still fail if yo= u > >> >set the load frequency to the lowest value? > > >> Default - 2.5MHz. > >> I've tried setting it faster and =A0do see the SPI rate increase once = config starts, so it is seeing > >> some of the datastream. > > >> >Other ideas: > >> >----------- > >> >I always put 10K pull-ups to 3.3V on the lines to and from the SPI > >> >flash. Have you tied any unused flash inputs? (e.g. WP/HOLD to 3.3V o= n > >> >Atmel parts) > > >> >You can also read a status register over the JTAG port with the Latti= ce > >> >USB thingy and ispVM. Is anything 'interesting' set in this if you re= ad > >> >it after flash load fails? I've forgotten the exact feature/function = in > >> >ispVM. I'll have mine hooked up later today so I'll take a look and p= ost > >> >back. > > >> >Regards, > >> >Charles > > >> I've now tried retargetting the project to a LFEC6 and loaded it on a = Lattice devboard with the same > >> result so AFAICS it looks like it's a software issue generating a bad = CRC on the bit file. > > >If you have an earlier version of ispLever, you can try it to see if > >the > >CRC problem is a software bug. =A0I tend to leave older versions of the > >tools around so I don't need to "upgrade" existing projects in order > >to make minor changes. =A0All of my EC/ECP (not ECP2 or newer) were > >built > >using ispLever 6.x versions. =A0Never seen this problem myself. > > >Regards, > >Gabor > > Good idea, unfortunately 6.x does not appear to be available on the Latti= ce website - only the > service packs Back in the 6.x days everything was delivered on CD-ROM. I still have mine. If you picked up ispLever after the 7.x updates, you still might be able to get the older versions if you ask.Article: 142213
On Jul 27, 9:14 pm, "shamanth" <shamant...@gmail.com> wrote: > Hi, > > I am trying to implement a bram using the "BRAM_SDP_MACRO" in Virtex5 fpga > on ML561 board using ISE 10.1 > > I want to write an array of data into it and then read it back to verify > that the data was written correctly. What are the different ways of doing > this? > > To start with, I have written a verilog code and am also using the > template I found in the "Virtex-5 Libraries Guide". Using a 4-bit counter I > write data into to the bram and later use a slower clock to read the data > back to be diplayed on the seven-segment display one after the other. But I > dont see any thing other than all the segments glowing, no matter how many > read-clocks pass. I think this means, my output data is stuck at all 0s and > is not changing at all. > > Can anyone please help me solve this? You have three parts to this circuit. One part generates and writes the data to the BRAM, the second part reads the data from the BRAM and the third part translates the read data for the display. You might want to test these parts separately. Or better, test it in simulation where you can see all of the signals, not just the outputs! To test separately, you need to "see" various signals. That you can do by connecting them to your display outputs. You will just need to interpret the lighted bars of the display appropriately. So first connect the display to the output of the data generator. When that works correctly, connect the display to the output of the read circuit. When that works correctly, connect the display to the output of the translator. RickArticle: 142214
It has worked at Xilinx ML605 board. plz mail me if more info. arcdoos@yahoo.comArticle: 142215
Hi I guess the way i do it, there is little feedback to be expected, ;) but, eh, its getting to be one year full now, the 1 year issue to be out soon, and still not have had time to get the LAYOUT and editorial templates all ironed out, made beatiful.. just tipping in things from my mind as it goes so, any commentary? wishes? ideas to submit? i am listening, as always writing up july issue right now AnttiArticle: 142216
On Jul 29, 5:37=A0pm, arcdoos <arcd...@yahoo.com> wrote: > It has worked at Xilinx ML605 board. plz mail me if more info. > > arcd...@yahoo.com you should get prize on wrong way to announce, what is what has worked? 1) you developed some IP and it works well? 2) you stole IP some and want to sell it? 3) or you need something? its totally unclear from your writeup what it is! pardon me, but from your style, i would guess [2] but even if so, it can be announced better :) AnttiArticle: 142217
On Jul 28, 2:52=A0pm, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif > > John As far as I know Achronix is still up and running. Is anybody actually using their chips ? EvgeniArticle: 142218
It's a shame it doesn't start slightly earlier. What and when was the first PLD (not including ROMs). I remember using the Signetics 82S series (100?, 105? 153?) back sometime in the mid 70's. Was Signetics the first? I think the MMI stuff was a bit later.Article: 142219
On Jul 28, 6:55 pm, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > On Tue, 28 Jul 2009 15:12:35 -0700, "Joel Koltner" > > > > <zapwireDASHgro...@yahoo.com> wrote: > >>http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif > > >Interesting, indeed. > > >Cypress had viable products but I'm convinced that management was the problem. > >(I also remember they wanted a rather large premium for their CPLDs that were > >sometimes only marginally better than the competition's.) > > >I don't know what Vantis's problem was, but at least after Lattive bought them > >they kept a few of the parts around. > > >Intel doesn't have its heart in much of anything but their desktop CPUs -- > >they consistently bring out interesting products and then discontinue them > >just when they're starting to gain traction. > > >You're pretty much a pure Xilinx man these days, aren't you, John? > > Yes, although I occasionally use a 22V10 for glue logic and such. > We've used MMI, Gould/AMI, Actel, TI, and Lattice in the past. > > We've been meaning to start using some CoolRunner type CPLDs for > various things, but no compelling application has come up. > > Where the hell are the Spartan 6's? Nobody will tell me when we can > get some. Sales reps fall off the face of the Earth when you ask that > question. The best I can get is "available for purchase in September" > and nobody knows what that means. So what else is new about Xilinx??? Same old, same old... I don't get all worked up about the latest and greatest tech in FPGA chips. I am much more concerned with availability and price than I am getting the smallest geometry or the most developed technology. So much of that stuff is actually in the noise when building a product. I care how well my vehicle moves, the MPG and how often it goes in the shop. Why should I care how many cylinders, how many valves or even if it is electric? With FPGAs, I care about if I can actually get them, will my design fit (along with any future expansion allowance) and how much it costs, optionally with what packaging if that matters in a given design. The rest is in the noise including, for the top three, the tool set. RickArticle: 142220
Frank Buss wrote: > Is this corruption problem on read really a "feature" of all FPGAs with > BRAM from all vendors? Just answering my question myself: Yes, Altera block RAMs have this problem, too, see e.g. page 9: http://www.altera.com/literature/hb/cyc2/cyc2_cii51008.pdf -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 142221
Hello, hello, I'm a grad student and am pretty new to the FPGA scene but I've been learning VHDL over the last month and now come to the point where I need to jump into embedded systems. I am trying to build an FPGA based system where I have an input from the outside world in the form of a logic level. Ever clock cycle, I check what the input logic level is and then if it's high I increment a counter. The value of this counter is then stored into the board's onboard DDR SDRAM. The values in this DDR must then be read out to a computer. I figured that the best way to read out these values to the computer would be some sort of web server that interfaces with the onboard DDR somehow, which is more or less where I get lost. I'm not entirely sure how to make the jump from writing VHDL scripts and loading them into the FPGA to embedded processes which execute the VHDL code. The BSB created a DDR memory interface to use, but using it falls into the category of getting the two IPs to talk to eachother which I do not yet know how to do. So in a nutshell I'm not sure how to: 1- Have an embedded processor execute VHDL scripts. 2- Have two IPs talk to each other (getting a data acquisition script to store values into the DDR via a MIG generated interface). 3- Have a web server interface with the onboard components (whether it be switches, LEDs or the DDR memory) I know it's possible for switches and LEDs because some XAPPS I've read have this as part of their functionality but are not explicit as to how they work. Essentially, does anyone know (or is anyone able to point me in a direction) where I can find some reference material on any of these subject? I doubt I'm the first person to try and readout the onboard DDR via ethernet, does anyone here have any experience in doing this? The board I'm planning on using is the ML402 (Virtex-4 FPGA) and I'm running ISE/EDK 11.2 . Thanks!Article: 142222
Un bel giorno glnazar digiṭ: > blocks). More specifically, the transition to NEXT_STATE happens in the > same cycle start is raised to 1 in the top level block, but will only > happen in the next cycle (when start already is 0) in inner blocks. Perhaps you've declared 'state' as a variable in the first case, and as a signal in the second. -- emboliaschizoide.splinder.comArticle: 142223
Griffin wrote: > I am trying to build an FPGA based system where I have an input from > the outside world in the form of a logic level. Ever clock cycle, I > check what the input logic level is and then if it's high I increment > a counter. The value of this counter is then stored into the board's > onboard DDR SDRAM. The values in this DDR must then be read out to a > computer. If it's just one counter, I don't need any ram. The other logic is very simple. > I figured that the best way to read out these values to the computer > would be some sort of web server that interfaces with the onboard DDR > somehow, which is more or less where I get lost. I would start with a parallel or serial port interface to the PC. > I'm not entirely sure how to make the jump from writing VHDL scripts > and loading them into the FPGA to embedded processes which execute the > VHDL code. Your vhdl code is converted to a netlist of gates and flops by synthesis. VHDL code is only executed on a simulator. > So in a nutshell I'm not sure how to: > 1- Have an embedded processor execute VHDL scripts. An embedded processor executes machine code from a C complier or an assembler. If I have an external computer reading the register, I don't need a cpu core on the fpga anyway. VHDL code might *describe* a cpu, but it does not run on one. -- Mike TreselerArticle: 142224
On Wed, 29 Jul 2009 10:24:07 -0700, Pete Fraser wrote: > It's a shame it doesn't start slightly earlier. What and when was the > first PLD (not including ROMs). I remember using the Signetics 82S > series (100?, 105? 153?) back sometime in the mid 70's. Was Signetics > the first? I think the MMI stuff was a bit later. Signetics were definitely before MMI. ISTR there's a note in the MMI "Designing with Programmable Array Logic" book (yes, I said "book", published by McGraw-Hill, authored by "The Technical Staff of Monolithic Memories Inc.") that implies this. Something about the PAL being an enhanced PLA. I'd grab my copy off the bookshelf and quote it, but there's half a dozen other books on top of it, and I'd rather not cause a Catastrophic Bookshelf Collapse this late in the day... :) Cheers, -- Phil. usenet09@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "09" with the last two digits of the current year.
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