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Hi David, Thanks for the reply. Actually, I am using VHDL entry. The design is implemented without errors nor warnings. But when it comes to optimizing, it generates these warnings. The problem is that these ports are inputs so I can not simulate the design ( input stimuli). Cheers.Article: 14276
John Schewel wrote: > > hello all.. > > thanks for the pointer .... in fact the Product of the Week changes each > week.... dhaaa on my part.... new link is (and i don't know for how long > ;)) > > http://www.edtn.com/pld/pldp208.htm > > a word on 'the catch'...... > > The HOT2 Interface Netlist contains the LogiCORE PCI Interface... to > obtain the HOT2 Netlist you must sign a special license from Xilinx > Inc., which only allows use of the Xilinx Interface on the HOT2 Board... > once you have 'Validated' your project and intend to go into production, > you must pay another license fee to Xilinx. > > -- > > Best Regards, > John Schewel, VP Marketing & Sales > Virtual Computer Corp. > http://www.vcc.com Can anyone tell us how much that license is? -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 14277
Randy Yates wrote: > I think you made some excellent points. But don't you think you > missed one major reason why VHDL is used? Intellectual Property. > In the software world, it's the same idea as code re-use. You've > got functional block that can be dropped into many different > systems that have many different types of hardware targets (ASIC, > FPGA, etc.). > -- > % Randy Yates % "The dreamer, the unwoken fool - > %% DIGITAL SOUND LABS % in dreams, no pain will kiss the brow..." > %%% Digital Audio Sig. Proc. % > %%%% <yates@ieee.org> % 'Eldorado Overture', *Eldorado*, ELO > http://www.shadow.net/~yates I may be a little dense sometimes, but how is this different with schematic? I am sure that Ray and some of the others will tell you how valuable their libraries are. And even many if not all of their larger designs can be "dropped" into another system. Changing the target would be a matter of replacing the primitives in their library. Although their designs are highly optimized for the application and target, library substitution might not produce a design as efficient as a new design. But I would be willing to bet it would still be more efficient than a "dropped" VHDL design. Anyone have an opinion on this? -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 14278
Tom Burgess wrote: > How about using a MC100LVEL29 dual D-FF (1.1 GHz, 3.3V) as a readable > divide by 4 prescaler (to bring the FPGA toggle rate down to 250 MHz) > and a SY100ELT23L (diff. PECL to TTL, 3.3V) to bring both bits into > the FPGA. The reset input of the first D-FF could be used for clock > gating. Remaining problems include finding a reasonable GHz clock > source and interfacing to the signal to be measured. For higher > clock rates, the MC100LVEL32 (3 GHz divide by 2, 3.3V) might be > of interest. > > Tom Burgess Maybe this is yet another topic that I can learn something about. Why do you need to read the bits of a prescaler. Can't you just use an ECL counter as a divide by circuit to bring the freq down to what the FPGA can handle. Then you can do a normal freq counter in the FPGA. The software or hardware reading the freq counter just needs to know the amount the freq was scaled by. Of course this would require that you take more time to reach the same resolution in your measurement. If you need 1 Hz resolution and you prescale by 10, you would need to measure for 10 seconds rather than 1 second if you had no prescaler. But is this the issue? Once again, am I missing something? ~(:) -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 14279
First, thanks for the moral support. Unfortunately I "downgraded" to M1.4 back because I don't really like to debug what I've already debugged. I guess I will start my next design from scratch on M1.5, but till then - Metamor's for me. Also, big disadvantage of FPGAEXP doesn't come from being VHDL87-ish - there are some complete portions of the language that it won't support, although they were available in 87 - like Multi-dimensional arrays, aliases, etc. If it was a complete 87 synth, I wouldn't whine. Synopsys guys -- Check out Aldec's tools for what completeness and perfectionism is. -- Yours, -- Ido Kleinman. kleinn@REMOVETHIS.mail.biu.ac.il ** Please delete the "REMOVETHIS." substring to Email me. Rickman wrote in message <36A6BF07.BCAE24B0@yahoo.com>... >Synopsys, are you listening??? > >VHDL-93 NOW! > > > > >Andy Peters wrote: >> >> Ido Kleinman wrote in message <77lek9$5mo$1@news2.inter.net.il>... >> >> >I've been using Foundation 1.4 with it's Metamor synthesis for a while now, >> >and I've got a few working designs. >> >I recently moved to Foundation 1.5 and it's FPGA Express synthesis - >> >> In case it wasn't clear from Evan's post: Metamor is a VHDL'93-compliant >> tool, FPGA Express is VHDL'87-compliant (with a couple of '93 things thrown >> in). The problems you're having are a result of Synopsys still living in >> the Reagan era.Article: 14280
I'm trying to design a RAM module in VHDL and am using the array
construct to represent my data - here is a snippet:
ARCHITECTURE behav OF ram256x1s IS
TYPE ram256b1_array IS ARRAY(255 DOWNTO 0) OF std_logic;
SIGNAL ram_256x1 : ram256b1_array;
BEGIN
PROCESS (wr_clk, a)
BEGIN
IF(rst='1') THEN
FOR i IN 0 TO ram_256x1'LENGTH - 1 LOOP
ram_256x1(i) <= '0';
END LOOP;
ELSIF(wr_clk'EVENT AND wr_clk='1' AND wr_en='1') THEN
ram_256x1(conv_integer(a)) <= di;
ELSIF(a'EVENT AND wr_en='0') THEN
do <= ram_256x1(conv_integer(a));
END IF;
END PROCESS;
END behav;
I'm using the conv_integer routine from std_logic_arith to access the
RAM elements but FPGA Express gives me an error:
Error:
E:/ADAM/WPI/Directed_Research_Spring_1999/Systolic_Array_Port/ram256x1s.vhd
line 29
Subprogram call, slice name, attribute name or indexed name argument
error. (VSS-525) (FE-dm-hdlc-unknown)
Error:
E:/ADAM/WPI/Directed_Research_Spring_1999/Systolic_Array_Port/ram256x1s.vhd
line 31
Subprogram call, slice name, attribute name or indexed name argument
error. (VSS-525) (FE-dm-hdlc-unknown)
Of course, when you look up error VSS-525, no help topic exists (thanks
so much Synopsys!). Can someone provide me with a clue as to what the
problem is?
Thanks much - email replies would be appreciated.
Adam
Article: 14281Alexander Sherstuk wrote: > > Dear colleagues, > > I am considering using FPGA for 1ns-accurate measurements. > As well as I understand, it is hardly possible to feed 1GHz clock > frequency into FPGA. > My questions are: > > 1. Has anybody used some kind of frequency prescaler in connection > with FPGA? > > What prescalers are suitable for such purpose? Does anybody > know VHF counters with internal stages accessible (which is > necessary to obtain lowest bits of the counter)? > > 2. Is it possible for XILINX Virtex to generate 1 GHz internally, > through it's on-chip PLL? > 3. Is Altera's on-chip PLL capable of such frequencies? > > Thanks, > Alex Sherstuk > sherstuk@amsd.com > AMSD Company Alex, if you just need edge resolution (and not extreme measurement reprates) it's common to use interpolation techniques to extend resolution. We make time-interval counters down into the low picosecond range. For 1 ns, it's common to run a reasonable clock through a tapped delay line and feed the taps into a latch. Freeze the latch at the edge of interest and examine the latched pattern for the fine time detail. Higher resolutions are usually achieved using analog ramp/ADC or pulse-magnification analog circuits. John -- ********************************************************************h John Larkin, President phone 415 753-5814 fax 753-3301 Highland Technology, Inc 320 Judah Street jjlarkin@worldnet.att.net San Francisco, CA 94122 http://www.highlandtechnology.comArticle: 14282
Did you hear that Synopsys? VHDL-93 NOW! and while you're at it, VHDL-87 as well! (more of it, that is) Ido Kleinman wrote: > > First, thanks for the moral support. > Unfortunately I "downgraded" to M1.4 back because I don't really like to > debug what I've already debugged. > I guess I will start my next design from scratch on M1.5, but till then - > Metamor's for me. > > Also, big disadvantage of FPGAEXP doesn't come from being VHDL87-ish - there > are some complete portions of the language that it won't support, although > they were available in 87 - like Multi-dimensional arrays, aliases, etc. If > it was a complete 87 synth, I wouldn't whine. > > Synopsys guys -- Check out Aldec's tools for what completeness and > perfectionism is. > > -- > > Yours, > -- Ido Kleinman. > kleinn@REMOVETHIS.mail.biu.ac.il > ** Please delete the "REMOVETHIS." substring to Email me. > > Rickman wrote in message <36A6BF07.BCAE24B0@yahoo.com>... > >Synopsys, are you listening??? > > > >VHDL-93 NOW! > > > > > > > > > >Andy Peters wrote: > >> > >> Ido Kleinman wrote in message <77lek9$5mo$1@news2.inter.net.il>... > >> > >> >I've been using Foundation 1.4 with it's Metamor synthesis for a while > now, > >> >and I've got a few working designs. > >> >I recently moved to Foundation 1.5 and it's FPGA Express synthesis - > >> > >> In case it wasn't clear from Evan's post: Metamor is a VHDL'93-compliant > >> tool, FPGA Express is VHDL'87-compliant (with a couple of '93 things > thrown > >> in). The problems you're having are a result of Synopsys still living in > >> the Reagan era. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 14283
Hello I am a customer from India to Xilinx. I purchased the Xilinx Express foundation series long almost 1 month ago. Till now either for installation or to tell how to start was not guided by any of the Indian representative. Hence it shows the poor service of the Xilinx company in INDIA. Hence I appeal to people of India not to go for purchsing the Xilinx products, which suffer from lack of service in Indian region. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14284
Dear friends in FPGA Group: I need help to implement a simple PLL in Xilinx FPGA for self-leaning. Appreciated for help to any webpages, application, or example. Regards, DavidArticle: 14285
> I am very interested in this discussion since I have become rather > dissatisfied with the Xilinx version of Synario's FPGA Express. I would > like to learn more about the various compilers available and their > strengths or faults. Cough, cough, if gurus forgive me, I want to give my experiences to this newsgroup. > There was a lot of good information in several of these posts, but I > have not been able to tell what software is being talked about. > > Is synplicity and synplify the same product? Who is the vendor and which > is the product? I can tell that you are running on the Sun workstation, > but is this a package that is supplied by Xilinx, or are you using the > Alliance software with the vendor's front end. My hardware ..... Sun Ultra-10 300 MHz / 128 MB RAM Design Entry .... Verilog Verification .... Cadence' Verilog-XL 2.6.10 Synthesis ....... Synplicity's Synplify FPGA Synthesizer Place&Route ..... Xilinx' Alliance Design Manager M1.5 Synplify includes vendor libraries. We are targetting our last chips to XC4000** families. Synplicity is the company (http://www.synplicity.com/) which sells FPGA Synthesizer. The official name of it is Synplify. The company is quite new (I think almost 4 years old). This tool is primarily a synthesizer. But it includes some additional features (algorithms) to contribute back-end tools (like Xilinx Design Manager Placement& Routing Tools) for a faster and smaller chip. It supports several vendors, like Xilinx, Actel and Altera etc. The main feature of this synthesizer is that it is very fast. I have designed a chip of 30.000 lines of synthesizable Verilog code and 70.000 lines testbench Verilog code, and such a complicated chip is compiled in just 2 minutes in this synthesizer. > When Synopsys's FPGA Compiler is mentioned, which is this? Is this the > FPGA Express package from Synopsys (ver 2.1.3), supplied via Xilinx in > the Foundation Express package? Or is this a version direct from > Synopsys? The tool I mentioned was the one from package Xilinx Foundation. I haven't used any other Synopsys tool yet. > About your comment on CLB usage, I see what you are talking about. I > guess this is a difference between the view of the back end tools which > know about the routing vs. the front end tool which know nothing about > the routing. But I have noticed that the Xilinx Foundation Express will > add logic to the CE of a FF as well as the D input when you have if > statements inside the clocked region of a process. This often requires > twice the number of LUTs for a given function vs. putting all the logic > in the path to the D input. My CLB usage went up about 10% when I > converted from the Metamor compiler (M1.4) to the FPGA Express compiler > (M1.5). Once I corrected the code for the worst offenders (large > registers and big FSMs) the difference dropped to about 5%. This IS the point. Front-End tools and Back-End tools must be compliant somehow. I don't see any problem with behavioral or RTL verification of synthesizable logic but synthesis and placement&routing programs must be in peace. I observe in the last years there is a tendency to integrate both design flow steps into one system (a tool, a program). Altera's tools is an example. Synplify is also an example. There is a so-called Synplify-Xilinx Design Methodology (you can find this documentation -PDF or HTML- in their homepage). I understand from there that synthesizer algorithms are closely bound to FPGA architectures and FPGA-oriented algorithms. Current tools restrict HDL's at the expense of unportability to get faster and better results. I don't know if it is good or bad. From the customer of view (it's my company, in this case) I think it is not so important. But for me, synthesizer must be as much standard as possible. For example, there are some cases for Synplify, which accepts just one HDL coding technique among several which is the only synthesizable solution. (I can't give this example for information security). Another unbelivable result of Synplify was like this: I got a ca. 100-state FSM, and it got a one-bit output and the number of CLB's was, em, 160. I removed that output and CLB number increased!! You can't find such results. It is gained by try-and-see. And Help Manuals don't include some similar information. It is not aimed to argue about this synthesizer, I just wanted to give an example. I am quite sure that there are similar examples in other tools. My last comment is: Company which design these tools must put more know-how information about the usage of their tools. UtkuArticle: 14286
> My last comment is: Company which design these tools must put more know-how > information about the usage of their tools. must be "companies".... UtkuArticle: 14287
Utku Ozcan wrote: > > My last comment is: Company which design these tools must put more know-how > > information about the usage of their tools. > > must be "companies".... > > Utku Let me add an AMEN to that. Most of my time is spent wrestling with the tool to get it to do what I want. I've always wondered why the examples in the tutorials are so trival as to not provide any insight into the useage of the tool. regards JerryArticle: 14288
David, Check out the Motorola or National Semiconductor web sites. These places have application notes comcerning PLL operation and loop filter design which you can down load. Griffith David T Le wrote: > Dear friends in FPGA Group: > > I need help to implement a simple PLL in Xilinx FPGA for self-leaning. > Appreciated for help to any webpages, application, or example. > > Regards, > DavidArticle: 14289
Yes, You would want and external A/D and then design a state machine to do the decode. Griffith nobody@nowhere wrote: > Hi guys, > > it is possible to implement a DTMF Decoder in a FPGA/Xilinx ? > Input signal would be a digital E1/T1 signal, generated by a E1/T1 Framer > (CLK, DATA) > > comments please here or to mb@cellware.de > > Thanx > > MichaelArticle: 14290
EKC, Contact your local Xilinix vendor and tell them you are looking into selecting between Altera & Xilinix for a consulting job. They will usuually let you borrow the CDs tools and license for a 3 month period if you can't afford the tools. Griffith EKC wrote: > I am a high-school student in the 10th grade interested in synthesizing > designs for the Xilinx XC4000 series of FPGAs using VHDL. However, I am > having trouble obtaining a low-cost VHDL/Verilog synthesis tool. I am > currently using the ABEL language supported by Foundation Version 3.1 > student edition. The Xilinx web-page states that I need to obtain the > Foundation V1.4 cd's to upgrade V1.3 so that I can design with VHDL. > Does anyone know how to obtain these CD's from Xilinx? Or alternatively, > are there any free or open-source VHDL synthesis tools available? > > Thanks in advance, > > -EKC > > I think it's a shame that Xilinx and Altera are charging such hefty sums > for their software. It seems that the distinguishing factor between FPGA's > from different vendors is the quality and ease-of-use of the design > software, especially as the gate numbers stretch into the millions. By > decreasing or eliminating the price-barrier, FPGA vendors with superior > design software would increase the rate of diffusion of their software into > the market-place, and consequently promote their FPGA's. Such a lowering of > the price-barrier would pose a serious threat to companies that offer only > synthesis tools, which generally target FPGA's from different companies. > This would lock clients into FPGAs from a single vendor.Article: 14291
David T Le wrote: > I need help to implement a simple PLL in Xilinx FPGA for self-leaning. > Appreciated for help to any webpages, application, or example. A part of a PLL is VCO, a Voltage Controlled Oscillator, which is not reasonable to implement in a Xilinx FPGA. Some of the newer parts have DLL's (Delay Locked Loops) built in, for more information look at the Virtex parts on http://www.xilinx.com. I think it would be possible to build a DLL in a Xilinx, however it would not be simple, as the designer would need to know a lot of details as to how Xilinx parts work, such as controlling placement and routing to produce consistent delays. Xilinx and other FPGA's are best used for synchronous digital designs. Perhaps you might want to build a tic-tac-toe playing machine? Or a vending machine model? Or a digital filter? -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principle." Carl SaganArticle: 14292
Prentice Hall is about to release the new version of the Xilinx Student Edition, which contains Foundation 1.5 (VHDL and Verilog Synthesis). I believe it will cost around $90.00. If you live near a college that uses Xilinx, you can borrow the commercial version and use your license file for V1.3. Good luck. -- Shane Tow Undergraduate: Computer Engineering Georgia Institute of Technology gt0085b@prism.gatech.eduArticle: 14293
Hi Guys I am interested in participating in an FPGA student Design contest for this year 1999. So please if you know or familier with any such contest tell me. Thanks Yousef M. Hawwar hawwar@uwm.eduArticle: 14294
Hi All, Dr. Chris Dick, of Xilinx, published an implementation using 2,248 CLBs, last year in a SPIE paper. Has anyone else out there got any CLB counts for real-time DCT implementations? I'm not looking for someone to give away a circuit, am putting one together myself. At this point, it looks like it should be well under 1000 CLBs, but if someone else has results significantly better than I end up with, I'd be interested. - JohnArticle: 14295
Adam J. Elbirt wrote: > > I'm trying to design a RAM module in VHDL and am using the array > construct to represent my data - here is a snippet: > > ARCHITECTURE behav OF ram256x1s IS > > TYPE ram256b1_array IS ARRAY(255 DOWNTO 0) OF std_logic; > SIGNAL ram_256x1 : ram256b1_array; > > BEGIN > > PROCESS (wr_clk, a) > BEGIN > IF(rst='1') THEN > FOR i IN 0 TO ram_256x1'LENGTH - 1 LOOP > ram_256x1(i) <= '0'; > END LOOP; > ELSIF(wr_clk'EVENT AND wr_clk='1' AND wr_en='1') THEN > ram_256x1(conv_integer(a)) <= di; > ELSIF(a'EVENT AND wr_en='0') THEN > do <= ram_256x1(conv_integer(a)); > END IF; > END PROCESS; > END behav; > > I'm using the conv_integer routine from std_logic_arith to access the > RAM elements but FPGA Express gives me an error: > > Error: > E:/ADAM/WPI/Directed_Research_Spring_1999/Systolic_Array_Port/ram256x1s.vhd > line 29 > Subprogram call, slice name, attribute name or indexed name argument > error. (VSS-525) (FE-dm-hdlc-unknown) > Error: > E:/ADAM/WPI/Directed_Research_Spring_1999/Systolic_Array_Port/ram256x1s.vhd > line 31 > Subprogram call, slice name, attribute name or indexed name argument > error. (VSS-525) (FE-dm-hdlc-unknown) > > Of course, when you look up error VSS-525, no help topic exists (thanks > so much Synopsys!). Can someone provide me with a clue as to what the > problem is? > > Thanks much - email replies would be appreciated. > > Adam which std_logic_arith? I have no conv_integer that takes std_logic_vector in ieee.std_logic_arith, but I have one in arithmetic.std_logic_arith, using that it compiles with no errors in QuickHDL btw. I think you could use ram_256x1 <= (others => '0') in the reset instead of the loop, and if you want to synthesize it, putting anything but "clk" in the "if clk'event...." is a bad idea --Lasse --___--_-_-_-____--_-_--__---_-_--__---_-_-_-__--_---- Lasse Langwadt Christensen, MSEE (to be in 1999) Aalborg University, Department of communication tech. Applied Signal Processing and Implementation (ASPI) http://www.kom.auc.dk/~fuz , mailto:langwadt@ieee.orgArticle: 14296
leslie.yip@asmpt.com wrote: > > Ido Kleinman > > Perhaps I don't quite understand your problem, it seems to be the FPGA > Express's limitation. I used to synthesize the VHDL design with ViewLogic's > Aurora. However, in ViewLogic 7.5, it is with FPGA Express. I am now using it > and find that it doesn't quite work well with other ViewLogic's product like > ViewDraw, ViewSim. I'am a Powerview user and wounder what is the problems with FW-VL tools you have. I have just replaced VL-syntheses(7.4) with FE2.1.3 so it would be nice to know before things happends. -- Michael Laajanen, Design Engineer | Mail : mila@enea.se ENEA DATA AB | Tel : +4686385000, Mobil +46706848526 -- Error #152 - Windows not found: (C)heer (P)arty (D)ance Note. All opinions are my own and not the opinion of the company I'm working for.Article: 14297
When I implement a design that uses a clock input the final result includes an internal oscillator on the FPGA device. Is there anyway to disable this feature within Design Manager, I want to be able to manually clock the circuit with a push button. BTW, the hardware is a XC4010XL FPGA device. Thanks NickArticle: 14298
EK, A netlist is the output you would get from a schematic entry program. It identifys all node of a circuit design and indicates what pins of which devices are interconnected. DTMF decoders is a common product so unless you are doing this for school I would just buy it. Secondly if you look in the right places you'll probally find a large number of designs to select from. Good Luck ekuria01@kepler.poly.edu wrote: > Eli, Thank you very much for your response! I came across a 30 day downlaod > progam called state cad whcih will let me draw staete diagrams and convert to > vhdl and optimize it for fpgas. > > Just a really stupid question (this will show you how ignorant i am of this > field) .. What exactly is a netlist ? > > My expertiese is assembly coding and that sort of work. I really want to get > my hands into FPGAs. > > Well, i know i would need a-d converter to do the digital peak detection, and > have worked out a way to do it. I just wanted to hear if anyone had any > detailed histories or examples of it. > > My project is a digital AGC which has to do some twisted stuff to find the > signal in some sick S/N conditions. It works as a microcontroller, I just > have to make it work in a completly digital world (with some A-Ds of course). > > I doubt that it would be as easy as generating the state diagram (whcih in > itself is pretty involved when you have over 1000 lines of assembly code) and > creating vhdl from it. > > Well, Thank you again for your response. > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14299
Sections of the PLL you could put into the Xilinix would be the dividers, phase frequency converter, lock detect, and possibly the prescaler depending on the frequency of your PLL output. Externally use a VCO and a charge pump circuit (PNP & NPN transitors or do it FETs) There's nothing magical about PLL's just check out those Motorola and National Semiconductor sights, read the 5-8 pages of application notes and do it. David T Le wrote: > Dear friends in FPGA Group: > > I need help to implement a simple PLL in Xilinx FPGA for self-leaning. > Appreciated for help to any webpages, application, or example. > > Regards, > David
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