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Messages from 14300

Article: 14300
Subject: Re: Synthesis tools for Xilinx FPGAs
From: APS <resp@associatedpro.com>
Date: Sun, 24 Jan 1999 09:08:54 -0500
Links: << >>  << T >>  << A >>
Rick,

I have used both. Synplicity and Exemplar go back and forth as to who is the
best Synthesis tool. They both have their strong points. Exemplar is better
at retargeting to different devices. Synplicity has a much easier interface.
Exemplar has more settings. It's all a trade off as to what you like. The
Lucent engineers I've talked to prefer Exemplar. The XILINX guys are mixed.
I use XILINX FPGA express packaged with the Foundation tools. The packages
are reason priced anf the interface is complete. Synopsys Xpress is VHDL 87
vs. VHDL93 compliant (which I don't like but tolerate since I can still get
my code out fine). The large user base of XILINX Foundation are a real
blessing in getting bugs run out fast. An I have to rate XILINX support as
excellent.  We sell the XILINX Foundation Kits with our FPGA development
boards, as well as also selling a low cost (relative to Synplicity and
Exemplar) complete VHDL suite (simulator and synthesis) that is fully VHDL
93 compliant. (PeakVHDL). I have used this tool a bunch and think that for
the money, its the best buy between the three (Synplicity, Exemplar,
PeakVHDL). The support is also excellent. If you want to spenfd the money
though, Synplicity and Exemplar offer some good features. For example the
technology viewer allows you to zoom in on the CLBs etc. while still in the
synthesis tool. I have found this useful ,though expensive (4K-5K option). A
typical Synplicity multivendor seat with the technology viewer will run you
~14-15K, and that is without a simulator. You can get multivendor synthesis
from us  (PeakVHDL) with an integrated VHDL simulator for ~$5200.00. That's
quite a difference in price. Also if you just wanted to go XILINX you get
synthesis (FPGA Xpress) , VHDL simulator (PersVHDL), and a test board plus
router and schematic capture to boot for as little as $1550.00.  See
http://www.associatedpro.com

Rick Filipkiewicz wrote:

> I need to buy an HDL  Synthesis tool  with the back-end Target = Xilinx.
> I've got it down to a choice of
> either Leonardo [Exemplar] or Synplify [Synplicity].  Anybody have a
> comments  +or - on this chain
> Verilog-> <TOOL>-> Xilinx Spartan-XL/XC4K-XL/Virtex.
>
> One thing I have discovered is that the Xilinx place&route tools take a
> lot longer to run with the Synplify
> output than with the Spectrum - esp. the placer.  In both cases the
> design was unconstrained.  Of course I might be doing something wrong to
> the Synplify tool !

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 14301
Subject: Re: The development of a free FPGA synthesis tool
From: Juergen.Kahrs@t-online.de (Juergen Kahrs)
Date: Sun, 24 Jan 1999 21:30:56 +0100
Links: << >>  << T >>  << A >>
jspeter@twinkle.roanoke.infi.net wrote:

> > I don't think any of them translate the full C language properly.
> > Handel-C has a nice approach to parallel processing, concurrency and timing.
> 
> So far as I know, none of these can take full ANSI-C code.  My research
> attempts to support full ANSI-C by running the input through the freely
> available retargettable compiler, LCC.  I then just use the output from LCC
> as the input to the core compiler.

Let's take a trivial example in C:

     void main() {
     /*
      * This is an implementation of the Euclidean algorithm.
      * It finds the greatest common divisor of two integers.
      * JK 16.1.99
      */
       int  a, b, r;

       a = 30;
       b = 21;
       do {
         r = a;
         /* r = a % b; */
         while (r >= b) 
           r = r - b;    /* to avoid division */
         a = b;
         b = r;
       } while (r != 0);
       /* a contains greatest common divisor */
       /* printf("ggt = %d\n", a); */
     }

Why not compile it into ABEL this way:

     MODULE  main
     TITLE   'ggt.s assembled by SYM2ABL Sun Jan 24 20:47:34 CET 1999'
     DECLARATIONS
     reset                           PIN     ISTYPE 'REG';
     ready                           PIN     ISTYPE 'REG';
              sreg_3 .. sreg_0       NODE    ISTYPE 'REG';
     sreg  = [sreg_3 .. sreg_0];
              i_a_15 .. i_a_0        NODE    ISTYPE 'REG';
     i_a  =  [i_a_15 .. i_a_0];
              i_b_15 .. i_b_0        NODE    ISTYPE 'REG';
     i_b  =  [i_b_15 .. i_b_0];
              i_r_15 .. i_r_0        NODE    ISTYPE 'REG';
     i_r  =  [i_r_15 .. i_r_0];

     STATE_DIAGRAM   sreg
       STATE 0000:   GOTO 0001 WITH i_a := 30;
       STATE 0001:   GOTO 0002 WITH i_b := 21;
       STATE 0002:   GOTO 0003 WITH i_r := i_a;
       STATE 0003:   GOTO 0004;
       STATE 0004:   GOTO 0005 WITH i_r :=  i_r - i_b;
       STATE 0005:   IF i_r >= i_b THEN 0004 ELSE 0006
       STATE 0006:   GOTO 0007 WITH i_a := i_b;
       STATE 0007:   GOTO 0008 WITH i_b := i_r;
       STATE 0008:   IF i_r != 0 THEN 0002 ELSE 0009
       STATE 0009:   IF reset == 1 THEN 0000 ELSE 0009 WITH ready := 1;
     END


The lcc compiler produces a file ggt.s with "symbolic" code that can
be processed like assembly language. The ABEL code above was produced
by a program that can only handle trivial examples like this one.
But the general scheme of creating a special purpose finite state
machine instead of a complex general purpose processor is not limited
to such trivial cases. 

Does this make sense or am I completely led astray ?

________________________________________________________________________

Juergen Kahrs                                       Tel.  0421  249 666 
Millstaetter Strasse 15                             Tel.  0421  457 2819
D 28359 Bremen                                      Fax   0421  457 3578
____________ http://home.t-online.de/home/Juergen.Kahrs/ _______________



Article 14848 of comp.arch.fpga:
Article: 14302
Subject: Re: I really want to study VLSI design!
From: "Stout" <stout@pdq.net>
Date: Sun, 24 Jan 1999 16:34:08 -0600
Links: << >>  << T >>  << A >>
You really should have cross posted to sci.engr.semiconductors, and
comp.arch.fpga.  I already have done this for you.

I also have some links to vlsi design at the office, but you'll have to
wait for those.

Good Luck,
Jeff Stout


Kim, sungchul wrote in message <36AB7313.53A55EFF@cais.kaist.ac.kr>...
>Hello.
>I major in material science and engineering.
>I really want to study VLSI design. But I have no knowledges about that.
>
>How can I start my study?
>


Article: 14303
Subject: Re: PLL in FPGA
From: Peter Alfke <peter@xilinx.com>
Date: Sun, 24 Jan 1999 16:45:01 -0800
Links: << >>  << T >>  << A >>
David T Le wrote:

> I need help to implement a simple PLL in Xilinx FPGA for
> self-leaning.
> Appreciated for  help to any webpages, application, or
> example.
>  

What do you mean by "simple PLL"?
If you mean an analog PLL, then you can implement the phase
comparator in the FPGA, but you need an external op amp,
low-pass filter, and voltage-controlled oscillator. Such a
circuit is never simple.
If you just want to detect the center of a bit time, e.g.
for Manchester decoding, there is a digital circuit for that
in a previous issue of XCell.

The new Virtex family from Xilinx offers four built-in
delay-locked loops, which are digitally controlled and can
perform many of the functions normally done by analog PLLs.

Peter Alfke, Xilinx Applications

Article: 14304
Subject: CFP ICPP99-PERH99
From: hammami@u-aizu.ac.jp (Omar Hammami)
Date: 25 Jan 1999 08:07:50 GMT
Links: << >>  << T >>  << A >>


                           CALL FOR PAPERS


               International Workshop on Parallel Execution on
                           Reconfigurable Hardware

           
         http://www.u-aizu.ac.jp/labs/sw-pe/PERH99/welcome.html

                              Aizu, JAPAN

                         September 21-24, 1999

                     in  conjunction with ICPP99

          28th International Conference on Parallel Processing

          US site:  http://www.cis.ohio-state.edu/~icpp99/
          JP site:  http://www.takilab.k.dendai.ac.jp/conf/icpp99/


Workshop proceedings to be published by IEEE Computer Society Press.


THEME

Continuous progress in density, speed and design tools for 
reconfigurable hardware devices regularly creates new design 
opportunities and directions.

Meanwhile, the increasing diversity of computer workloads are 
making  the design of a universal and resource-efficient solution 
for all computing applications more elusive. Several issues in this 
context deserve further investigation.

The main objective of this workshop is to bring together researchers 
and practitioners with the aim of stimulating the exchange of ideas and
experiences on the potential and limits of reconfigurable hardware, and
opening new avenues of research.
Topics of interest include but are not limited to:

   * Dynamically Customizable Processor Microarchitectures
   * Parallel Reconfigurable Architectures
   * Performance Evaluation Techniques for Reconfigurable Systems
   * General Reconfigurable Computing Models
   * Programmable Logic Devices and Systems
   * Merging FPGA and Logic/DRAM
   * Design Process Flows and Tools
   * Hardware/Software Co-design
   * Evolvable Hardware
   * Performance/Cost Comparative Studies with Standard Designs
   * Applications (in search of the "killer" applications)
   * Use of Reconfigurable Hardware in Emulation, Prototyping, and 
     System Validation.

IMPORTANT DATES


   * Submission deadline:               1   March        1999
   * Notification of acceptance:        8   May          1999
   * Camera-ready copies:               15  June         1999

Demos are strongly encouraged. If you plan to make a demo of software 
or hardware platform please inform one of the co-chair by the same  
deadline.We can provide you with various equipments (WSs, PCs, CAD 
Softwares, some FPGA boards,  Instruments (digital analyzers, 
oscilloscopes, power supplies,etc)).


WORKSHOP Co-CHAIRS

   *    Fadi Sibai, Intel
   *    Omar Hammami, University of Aizu

PROGRAM COMMITTEE

   *    Hideru Amano, Keio University (JP)
   *    Sameh Asaad, IBM T.J.Watson, (USA)
   *    Peter Athanas, Virginia Tech., (USA)
   *    Nader  Bagherzadeh,UCI, (USA)
   *    Pak Chan, UCSC, (USA)
   *    Abdelaziz Chihoub, SIEMENS (USA)
   *    Apostolos Dollas, Technical University of Crete, (GR)
   *    Michel Dubois, USC (USA)
   *    Carl  Ebeling, University of Washington (USA)
   *    Hossam Elgindy, University of Newcastle, (Au)
   *    John Granacki, ISI-USC(USA)
   *    Omar   Hammami, University of Aizu (JP)
   *    Hitoshi Hemmi, NTT (JP)
   *    Brad Hutchings, BYU (USA)
   *    Tom Kean, Algotronix, (USA)
   *    Hassan Kobeissi, AMD   (USA)
   *    Kenichi Kuroda, University of Aizu, (JP)
   *    Miriam Leeser, Northeastern U., (USA)
   *    Toshiaki Miyazaki, NTT (JP)
   *    Masato  Motomura, NEC (JP)
   *    Scott Robinson, Los Alamos National Laboratory, (USA)
   *    Jonathan Rose, U.Toronto, (CA)
   *    Stephen Smith, Altera Corp., (USA)
   *    Yuichiro Shibata, Keio University (JP)
   *    Fadi   Sibai, Intel  (USA)
   *    Steve Trimberger, Xilinx, (USA)

PUBLICITY CHAIRS

   * Abdullah Abonamah, University of Akron (USA)
   * Imad Mahgoub, Florida Atlantic University , (USA)

TUTORIAL CHAIR

   * Abdelaziz Chihoub, SIEMENS, (USA)

LOCAL ARRANGEMENTS

   * Omar Hammami, University of Aizu (JP)
   * Kenichi Kuroda, University of Aizu (JP)


SUBMISSION DETAILS

Authors are invited to submit research contributions representing 
original,previously unpublished work. Submitted papers will be 
carefully evaluated based on originality, significance, technical 
soundness, and clarity of exposition. All papers will be refereed by 
at least two members of the program committee. Accepted papers will 
be published by IEEE Computer Society Press as proceedings of the 
ICPP'99 workshops. All submitted papers MUST be formatted according 
to the author guidelines provided by  IEEE Computer Society Press 
(two-column format) and MUST NOT be longer than 6 pages.


Electronic Submission

Please check details at:

http://www.u-aizu.ac.jp/labs/sw-pe/PERH99/welcome.html



Hard Copy Paper

If, for some reason, you cannot place an electronic copy of your 
paper on our FTP site, ONLY THEN you may submit it as four hard 
copies to the following address:

Asia-Pacific/Europe/Africa            America

 Dr.Omar Hammami                   Dr.Fadi Sibai
 University of Aizu                Intel Corporation, M/S:SC12-202
 Fukushima 965-8580                2200 Mission College Boulevard
 JAPAN                             Santa Clara, CA 95052, USA

Please send also an electronic copy of your abstract, in ASCII format 
and including author's name, postal address, phone number, fax number,
e-mail address, title of your paper, keywords,abstract, to both emails:

hammami@u-aizu.ac.jp                   fsibai@mipos2.intel.com

with in the subject field: ICPP99-PERH.



For any further questions or inquiries please contact one of the 
program co-chair :


 Dr.Omar Hammami                     Dr.Fadi Sibai
 University of Aizu                  Intel Corporation, M/S: SC12-202
 Fukushima 965-8580                  2200 Mission College Boulevard
 JAPAN                               Santa Clara, CA 95052, USA
 Voice : +81-242-37-2558             Voice:(408) 765-5581
 Fax   : +81-242-37-2595             Fax  :(408) 765-5263
 e-mail: hammami@u-aizu.ac.jp        email:fsibai@mipos2.intel.com

Article: 14305
Subject: FPGA student contest
From: Youssef Hawwar <hawwar@csd.uwm.edu>
Date: Mon, 25 Jan 1999 02:30:24 -0600
Links: << >>  << T >>  << A >>

Are you familier with any DSP FPGA student contest for this
year 1999. I am interested to participate in a contest, but I don't
know if their is any such contest for FPGA design.
If you know please tell me.

Yousef M. Hawwar
hawwar@uwm.edu

Article: 14306
Subject: Re: The development of a free FPGA synthesis tool
From: Jonathan Bromley <jsebromley@brookes.ac.uk>
Date: Mon, 25 Jan 1999 12:25:20 +0000
Links: << >>  << T >>  << A >>
Juergen Kahrs wrote:
<snip example> 
> 
> The lcc compiler produces a file ggt.s with "symbolic" code that can
> be processed like assembly language. The ABEL code above was produced
> by a program that can only handle trivial examples like this one.
> But the general scheme of creating a special purpose finite state
> machine instead of a complex general purpose processor is not limited
> to such trivial cases.
> 
> Does this make sense or am I completely led astray ?

I think it makes perfect sense.  You can think of any sequential
program as a big state machine with the program counter as its
state variable (indeed, this is quite a useful way to think about
certain kinds of parallel programming problem).  Getting an 
optimal implementation is quite another matter, of course.

See CompiLogic Corp's material for some interesting results
in this field.  Personally I think C is a blind alley - you need
far more explicit control over parallelism, Handel-C comes close
but is not sufficiently configurable - but the possibilities are
obviously there.

Jonathan Bromley


Article 14851 of comp.arch.fpga:
Article: 14307
Subject: Re: DTMF Decoder in a FPGA/XILINX ?
From: "denis lachapelle" <sysacom@cam.org>
Date: Mon, 25 Jan 1999 07:48:42 -0500
Links: << >>  << T >>  << A >>
I would suggest a DSP that has a T1 interface. To me it will be more
appropriate.


--
Denis Lachapelle, sysacom@cam.org
Sysacom R&D plus inc.
www.cam.org/~sysacom
tel 450 585-6396, fax 450 582-3231
nobody@nowhere wrote in message <78a9n0$koh@cs1.FTA-Berlin.de>...
>Hi guys,
>
>it is possible to implement a DTMF Decoder in a FPGA/Xilinx  ?
>Input signal  would be a digital E1/T1 signal, generated by a E1/T1 Framer
>(CLK, DATA)
>
>comments please here or to mb@cellware.de
>
>Thanx
>
>Michael


Article: 14308
Subject: Re: Power Consumption in FPGAs
From: "Panci Gianpiero" <dep.elsys@microelettra.it>
Date: Mon, 25 Jan 1999 13:58:07 +0100
Links: << >>  << T >>  << A >>

Andres Garcia ha scritto nel messaggio <36A75AD2.FBB0B66@enst.fr>...
>
>If anyone knows something about power consumption in FPGAs
>or if you want to discuss about it, please, send me an e-mail.
>
>Thank you.
>
>
I am really interested on FLEX10K power consuption, I am going to realize a
test bench to measure it!
someone can give me information ?  Thanks

Panci Gianpiero
dep.elsys@microelettra.it





Article: 14309
Subject: Re: The development of a free FPGA synthesis tool
From: seebs@plethora.net (Peter Seebach)
Date: Mon, 25 Jan 1999 16:27:15 GMT
Links: << >>  << T >>  << A >>
In article <36AB8300.7BB5E94@t-online.de>,
Juergen Kahrs <Juergen.Kahrs@t-online.de> wrote:
>Let's take a trivial example in C:

>     void main() {

Interesting, but not C.  main returns int in C.

-s
-- 
Copyright 1999, All rights reserved.  Peter Seebach / seebs@plethora.net
C/Unix wizard, Pro-commerce radical, Spam fighter.  Boycott Spamazon!
Send me money - get cool programs and hardware!  No commuting, please.
Visit my new ISP <URL:http://www.plethora.net/> --- More Net, Less Spam!


Article: 14310
Subject: Xilinx flip flops hold time
From: pandey@my-dejanews.com
Date: Mon, 25 Jan 1999 16:50:59 GMT
Links: << >>  << T >>  << A >>
Hello, I have a doubt that how can a 0 hold time flip flop be implemented.
Does any one have an answer to this one. I know it is being done in Xilinx
FPGAs.


-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 14311
Subject: Metastability implementation
From: pandey@my-dejanews.com
Date: Mon, 25 Jan 1999 16:53:03 GMT
Links: << >>  << T >>  << A >>
Can somebody illustrate how flip flops handle metastability. What are hardened
flip flops.
Thanx in advance
Pandey

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 14312
Subject: Re: AHDL VS. VHDL
From: Tom Davidson <TomD@Nshore.com>
Date: Mon, 25 Jan 1999 12:06:22 -0600
Links: << >>  << T >>  << A >>
I've been working on a SDRAM controller in VHDL in MaxPlus 9.03, it's
VHDL compiler is pretty brain-dead. The logic it generates is huge.
I'm going to translate back to AHDL to get closer to the Silicon.
The VHDL of the completed design is looking like it wont fit into
a Max 7192, The VHDL compiler wont do function calls properly.
It seems that there is a lot of  different interpretations of VHDL,
whereas Verilog is a more focussed specification. Does Altera have
a Verilog compiler for Max7K?

aweas wrote:

> thank you , but as you said the question is , how good are compilers today,
> like
> altera's maxplusII , for my self I made designs using AHDL and some times I had
> to go
> to lower level (gates) so the AHDL compiler could under stand what I mean, are
> VHDL
> compilers better then me? and to what extant , regarding clock speed and
> silicon area?
> and yes I'm VERY interested in knowing more about this.
>
> Jamie Lokier wrote:
>
> > This is interesting, as I know someone who switch from _V_HDL to _A_HDL
> > because he found VHDL too difficult to work with, and AHDL much more
> > straightforward.
> >
> > His AHDL code contains a fair amount of asynchronous stuff, crossing clock
> > domains, tight timing etc.  (I know, I work with his code).  So it can
> > be done.
> >
> > I don't know much about either language (except I have had to read and
> > understand some AHDL), but it does appear that with VHDL, you are
> > relying to some extent on the compiler knowing what you mean by various
> > constructs.  See other threads in this very newsgroup for "how do I
> > generate XXX flip-flop" questions.
> >
> > -- Jamie
> >
> > Brett George writes:
> > > do you want me to answer all three queries?
> > > Anyway, thought you might be interested to know that I have performed
> > > one design using AHDL/graphical logic. And found AHDL very difficult
> > > to use when trying to do things more complicated than can be visualised
> > > in terms of gates. Things like asyncronous state-machines had to be
> > > re-designed
> > > in terms of edge triggered FFs etc.
> > >     We will be making the move to VHDL shortly, for the next design and
> > > expect
> > > much better results. It seems to be a lot more flexible, as it is an
> > > actual language,
> > > rather than a text based logic system.
> >
> > > Will let you know how it went in a few weeks if you are still interested.
> >
> > > Brett.
> >
> > > aweas wrote:
> >
> > >> Hi
> > >> I think a lot of poeple made the transfer from altera's ahdl to vhdl.
> > >> those how did it , can you please give me some feed back about the
> > >> results.
> > >> and info about the transfer to VHDL .
> > >> I'll be happy to get as much answer's as possible
> > >>
> > >> thank you
> > >> Aweas

Article: 14313
Subject: Re: Q: Counting GHz pulses - ?
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Mon, 25 Jan 1999 10:24:53 -0800
Links: << >>  << T >>  << A >>
Rickman wrote:
<snipped>
> 
> Maybe this is yet another topic that I can learn something about. Why do
> you need to read the bits of a prescaler. Can't you just use an ECL
> counter as a divide by circuit to bring the freq down to what the FPGA
> can handle. Then you can do a normal freq counter in the FPGA. The
> software or hardware reading the freq counter just needs to know the
> amount the freq was scaled by.
> 

AS I understand it, the original questioner wanted 1 ns accurate time
interval measurements, rather than frequency. For this, you need to read
all the counter bits including prescaler to get the needed resolution.
This is for a non-repetitive pulse measurement. If you were just wanting
to know the period of a repetitive signal, it would be just the
reciprocal
of frequency, and a normal frequency counter would do.

-- 
Tom Burgess
-- 
Digital Engineer
National Research Council of Canada
Herzberg Institute of Astrophysics
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3

Email:        tom.burgess@hia.nrc.ca
Office:       (250) 490-4360 
Switch Board: (250) 493-2277
Fax:          (250) 493-7767
Article 14847 of comp.arch.fpga:
Article: 14314
Subject: Re: Power Consumption in FPGAs
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Mon, 25 Jan 1999 10:45:17 -0800
Links: << >>  << T >>  << A >>
Panci Gianpiero wrote:
> 
> Andres Garcia ha scritto nel messaggio <36A75AD2.FBB0B66@enst.fr>...
> >
> >If anyone knows something about power consumption in FPGAs
> >or if you want to discuss about it, please, send me an e-mail.
> >
> >Thank you.
> >
> >
> I am really interested on FLEX10K power consuption, I am going to realize a
> test bench to measure it!
> someone can give me information ?  Thanks
> 
> Panci Gianpiero
> dep.elsys@microelettra.it

Most manufacturers have application notes on this topic. Altera's
for example, at http://www.altera.com/document/an/an074.pdf
The bottom line is that dynamic power consumption is mostly design
and data dependant and current FPGA design tools provide little or
no help with power estimation. You will need to make rough
estimates from available data, then verify them on a test bench,
or in the final product (when it is too late to do much).

Tom Burgess
-- 
Digital Engineer
National Research Council of Canada
Herzberg Institute of Astrophysics
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3

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Article 14851 of comp.arch.fpga:
Article: 14315
Subject: Re: Xilinx flip flops hold time
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 25 Jan 1999 10:56:00 -0800
Links: << >>  << T >>  << A >>
pandey@my-dejanews.com wrote:

> Hello, I have a doubt that how can a 0 hold time flip flop
> be implemented.
> Does any one have an answer to this one. I know it is
> being done in Xilinx
> FPGAs.

Set-up time and hold time describe the timing window, with
respect to the clock edge, where input data must be stable
in order to guarantee reliable flip-flop operation. For any
given flip-flop and operating condition ( temperature,
voltage ) this window is very narrow ( picoseconds wide )
but the position of this window varies with processing and
operating conditions. The IC manufacturer specifies the
worst-case earliest edge of this window as a set-up time,
and the worst-case latest edge as a hold time. ( Whether
these should be labeled min or max is an old contentious
argument best left alone here ).

Zero hold time just means that the flip-flop-internal delay
in the data path is longer than the delay in the clock path,
so the data need not be held beyond the clock edge.

The IC designer has a lot of freedom to move the window left
or right. Since a positive hold time has ugly systems
ramifications, most IC manufacturers go to some trouble to
avoid it, and they have to pay for this with a longer set-up
time, which reduces the max performance.
"There is no free lunch".

For ways to measure metastability, see - among other sources
- page 1347 of the xilinx data book.

Peter Alfke, Xilinx Applications

Article: 14316
Subject: Re: Xilinx flip flops hold time
From: fliptron@netcom.com (Philip Freidin)
Date: Mon, 25 Jan 1999 18:59:46 GMT
Links: << >>  << T >>  << A >>
To achieve 0nS hold time for a flip flop, you add delay to the data path 
to the flipflop. If you add sufficient delay that even at its minimum it 
exceeds the intrinsic flipflop hold time, the resultant structure (delay 
plus flip flop) exhibits 0 ns (or even negative) hold time. The trade off 
is that the delay also affects setup time by the maximum value that it 
can take. Xilinx uses the delay through the fuction generator to achieve 
this delay in the main array, and in the I/O cells it uses an explicit 
delay block. From a system point of view, for an I/O cell you want the 
hold time for an external input to be 0nS with respect to a clock signal 
that is also external to the device. The explicit delay block in the I/O 
cells is matched to not just the flip flop, but also the delay in the 
global clock distribution network. If you dont use a global clock to 
clock an I/O cell input flip flop, or you disable the explicit delay, 
then setup times and hold times are different and you will need to take 
that into account.

Philip Freidin


In article <78i7df$r2b$1@nnrp1.dejanews.com> pandey@my-dejanews.com writes:
>Hello, I have a doubt that how can a 0 hold time flip flop be implemented.
>Does any one have an answer to this one. I know it is being done in Xilinx
>FPGAs.
>
>
>-----------== Posted via Deja News, The Discussion Network ==----------
>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    


Article: 14317
Subject: Re: PLL in FPGA
From: Ray Andraka <randraka@ids.net>
Date: Mon, 25 Jan 1999 15:02:52 -0500
Links: << >>  << T >>  << A >>
What are the required frequency and jitter specifications?  If they are
reasonably low, you can implement a digital PLL in an FPGA.  An example
might be a 100uS clock locked to the pulse per second signal associated
with certain GPS receivers.  If you need an analog PLL, the FPGA can still
be used for the feedback and reference dividers, and even for the phase
comparator.  My preference in these cases is to use a device that has a
VCO, loop filter, and phase comparator integrated in it (such as the 88915
available from a number of sources) and do the dividers in the FPGA.  This
lets you make the programming interface any flavor you want instead of
having to live with one of the goofy serial programming protocols
available in most of the all-in one PLLs.

David T Le wrote:

> Dear friends in FPGA Group:
>
> I need help to implement a simple PLL in Xilinx FPGA for self-leaning.
> Appreciated for  help to any webpages, application, or example.
>
> Regards,
> David



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 14318
Subject: Actel A1280CQFP Prototype Adapter board
From: "David A. Baldwin" <dave@baldwin-tech.com>
Date: Mon, 25 Jan 1999 13:04:31 -0700
Links: << >>  << T >>  << A >>
If you're creating a new design utilizing the Actel A1280CQFP
rad-hardened FPGA, here's a solution that will save you a lot of money
and engineering d-bug time.

We offer an adapter board which enables the use of the Actel A1280TQFP
or the A1280PGA, without modification or damage to the main board.

Please check it out at http://www.baldwin-tech.com/actel.htm

Article: 14319
Subject: Re: 8x8 (x8 -> 11) DCT Implementation Results?
From: Ray Andraka <randraka@ids.net>
Date: Mon, 25 Jan 1999 15:09:18 -0500
Links: << >>  << T >>  << A >>
John,

I started looking at a 1-d implementation using CORDIC rotations and
butterfly like reductions.  It appeared to have about a 15% CLB savings
over the 1-d implementation (8point) Chris used for the last stage of
his 2-D DCT.  The polynomial reductions Chris used would still be
applicable.  I didn't finish on that implementation because the client
put a hold on the project.  The CORDIC implementation may be extendable
to 2 dimensions as well with additional savings.  Sorry I can't give you
anything more conclusive as of yet.

John L. Smith wrote:

> Hi All,
>
> Dr. Chris Dick, of Xilinx, published an
> implementation using 2,248 CLBs,
> last year in a SPIE paper.
>
> Has anyone else out there got any CLB counts for
> real-time DCT implementations? I'm not looking
> for someone to give away a circuit, am putting
> one together myself. At this point, it looks like
> it should be well under 1000 CLBs, but if
> someone else has results significantly
> better than I end up with, I'd be interested.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 14320
Subject: Re: FPGA express warning
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 25 Jan 1999 13:54:12 -0700
Links: << >>  << T >>  << A >>
Khaled benkrid wrote in message <36A93CD0.709B515B@qub.ac.uk>...
>Hi David,
>
>Thanks for the reply. Actually, I am using VHDL entry. The design is
implemented without errors nor
>warnings. But when it comes to optimizing, it generates these warnings. The
problem is that these ports are
>inputs so I can not simulate the design ( input stimuli).


Make sure you indicate which source file is the Top Level when you
synthesize the design.  Only ports on the top level will get IBUFs and
OBUFs.


-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

"In the beginning, there was darkness.  And it was without form, and void.
And there was also me!"
-- Bomb #20, John Carpenter's "Dark Star"



Article: 14321
Subject: Re: Worst service in India by Xilinx
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 25 Jan 1999 14:00:37 -0700
Links: << >>  << T >>  << A >>
satish_me@hotmail.com wrote in message <78bt35$eql$1@nnrp1.dejanews.com>...
>Hello  I am a customer from India to Xilinx. I purchased the Xilinx Express
>foundation series long almost 1 month ago. Till now either for installation
>or to tell how to start was not guided by any of the Indian representative.
>Hence it shows the poor service of the Xilinx company in INDIA. Hence I
>appeal to people of India not to go for purchsing the Xilinx products,
which
>suffer from lack of service in Indian region.


Instead of blaming Xilinx and their reps for lack of support, have you tried
READING THE MANUALS THAT COME WITH THE SOFTWARE?

------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

"In the beginning, there was darkness.  And it was without form, and void.
And there was also me!"
-- Bomb #20, John Carpenter's "Dark Star"



Article: 14322
Subject: Re: Needed: PCI interface
From: rajesh52@my-dejanews.com
Date: Mon, 25 Jan 1999 23:53:33 GMT
Links: << >>  << T >>  << A >>
Greetings
Xilinx sales PCI master and slave IP cores along with test bench.
You can download one from their website for evaluation.

I am not sure whether you need core or just PCI bus functional model.

Xilinx supplies good enough test harness to simulate PCI
cycles on PCI bus. It is quite simple to understand and modify to
create your own cycles from it.

You might endup using just testbench if you already have pci target design
with you. You need to checkup for interrupts. I recall that in earlier
version of implementations they did not have interrupts.

Rajesh Bawankule
Verilog FAQ : http://www.angelfire.com/in/verilogfaq/index.html
Verilog Page : http://www.angelfire.com/in/rajesh52/verilog.html




In article <78i8cv$rtf$1@nnrp1.dejanews.com>,
  tim@techsource.com wrote:
> I'm designing a chip that needs to talk to a PCI bus, presently only as a
> target with interrupts.  If anyone could direct me to where I might acquire
> or lisence Verilog code for this, I would be most appreciative.

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 14323
Subject: Re: Metastability implementation
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Mon, 25 Jan 1999 16:14:53 -0800
Links: << >>  << T >>  << A >>
go to http://www.ti.com/sc/docs/psheets/abstract/apps/sdya006.htm
and all will be revealed

pandey@my-dejanews.com wrote in message <78i7hc$r3k$1@nnrp1.dejanews.com>...
>Can somebody illustrate how flip flops handle metastability. What are
hardened
>flip flops.
>Thanx in advance
>Pandey
>
>-----------== Posted via Deja News, The Discussion Network ==----------
>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own


Article: 14324
Subject: Re: FPGA express warning
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Mon, 25 Jan 1999 16:24:16 -0800
Links: << >>  << T >>  << A >>
In Foundation Express there is a little box somewhere that says to map the
top level signals to I/O pins.  Find that little box and check it.  If you
look at your .xnf file, you should see IBUF and OBUF components connected to
your signals.

Learn to look at the .xnf file.  It will help diagnose and prevent many
common errors.  It's a quick way to see what is going on.

Also, synthesis tools are notorious for optimizing away all you logic (due
to a design error) and giving you no clue.  Check the synthesis reports to
see if all your registers still exist.

Bruce

Andy Peters wrote in message <78ilns$p4r$1@noao.tuc.noao.edu>...
>Khaled benkrid wrote in message <36A93CD0.709B515B@qub.ac.uk>...
>>Hi David,
>>
>>Thanks for the reply. Actually, I am using VHDL entry. The design is
>implemented without errors nor
>>warnings. But when it comes to optimizing, it generates these warnings.
The
>problem is that these ports are
>>inputs so I can not simulate the design ( input stimuli).
>
>
>Make sure you indicate which source file is the Top Level when you
>synthesize the design.  Only ports on the top level will get IBUFs and
>OBUFs.
>
>
>-- andy
>------------------------------------------
>Andy Peters
>Sr. Electrical Engineer
>National Optical Astronomy Observatories
>950 N Cherry Ave
>Tucson, AZ 85719
>apeters@noao.edu
>
>"In the beginning, there was darkness.  And it was without form, and void.
>And there was also me!"
>-- Bomb #20, John Carpenter's "Dark Star"
>
>
>




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