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On Tue, 15 Sep 2009 04:05:47 -0500 "maxascent" <maxascent@yahoo.co.uk> wrote: > I agree totally with the op. I have had so many problems downloading > ISE 11.2 that I have just given up. Every time I try and resume after > stopping I just get error and have to strt all over again. Why cant > Xilinx just give us the option to download the file using our own > download manger. After all if I have the capability to design with > their FPGA then surely I can work out how to download a zip file. > > Jon > > --------------------------------------- > This message was sent using the comp.arch.fpga web interface on > http://www.FPGARelated.com Me too. Took me 4 tries to download ISE 11.2 using Windows XP, the first three times I got an hour and change into the download and then it hung up and wouldn't restart. The fourth time it still hung up, but when I force quit the downloader, then started to try for the FIFTH time, it picked up where it left off. Back in my day we had FTP servers that supported resuming in the middle of the file, and goshdarnit we liked it that way. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 143026
Hello, I have been trying to fit a deserializer into a Spartan 6 but I am running into some problems: - I am able to fit my design if the deserializer is on a top or a bottom bank. I can't get it fit when the deserializer is on the left or the right bank. There seems to be a problem with the BUFIO2. This is the error: ERROR:Place - SIO has over-constrained componet g_LTC2173Decoder[0].i_LTC2173Decoder/i_LVDSClockBuffer/i_BUFIO2 to have to placeable sites. Constraints come from driver constraints AND load IO constraints This error message doesn't really help me... In FPGA editor I find the BUFIO2's on all sides (top, bottom, left and right) but it looks as if these on the left and right side are a little different (they have no negative input). - The reportArticle: 143027
Thanks to all of you for useful feedback. My clock freq is 133 MHz. Based on your inputs and my understandig from reading "Spartan 3 FPGA Guide" this is what I plan to do. clk_i (main clock) connect it to one DCM input clock. 4 phased shifted output from the DCM will give me, clk90, clk180, clk 270. clk_i_inv_delayed ( inverted main clock delayed by 22.5 degree) connect it to another DCM input clock. 4 phased shifted output from the DCM will give me, clk45, clk135, clk225, clk315. Am I in the right path? Each clock line drives only two FFs, is 133 MHz okay? How can I create "clk_i_inv_delayed" ? Best regards, Qamrul >Qamrul > >If you don't need super fast clock outputs, that is less than say >12-25 MHz, you can use an internal clock at X8, X16, and a clock >enable structure to generate such outputs. If you take care such the >outputs are "buffered" through an I/O register, running at the X8/16, >then you won't get any significant skew on the phases due to routing. > >The clock enable can be a preloaded shift register, with wrap, that is >loaded with X"0001" (X16) loaded at reset or other control condition. >One thing that is ice about this way is that clocks can be "stopped" >easily and restarted without any retraining or lock sequences. > >For higher frequencies using PLL or DLL techniques to achieve the >required outputs is probably better. > >John Adair >Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. > > >On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: >> Hi All, >> >> I need to provide 8 clock outs shifted by 45 degree, >> >> clk_0 -> 0 degree phase shift >> clk_1 -> 45 degree phase shift >> clk_1 -> 90 degree phase shift >> clk_1 -> 135 degree phase shift >> clk_1 -> 180 degree phase shift >> clk_1 -> 225 degree phase shift >> clk_1 -> 270 degree phase shift >> clk_1 -> 315 degree phase shift >> clk_1 -> 360 degree phase shift >> >> Is it at all possible? >> >> Thanks in advance for your feed back. >> >> Qamrul > > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143028
On Sep 15, 8:20=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > Thanks to all of you for useful feedback. > > My clock freq is 133 MHz. Based on your inputs and my understandig from > reading "Spartan 3 FPGA Guide" this is what I plan to do. > > clk_i (main clock) connect it to one DCM input clock. > 4 phased shifted output from the DCM will give me, clk90, clk180, clk > 270. > > clk_i_inv_delayed ( inverted main clock delayed by 22.5 degree) connect i= t > to another DCM input clock. > > 4 phased shifted output from the DCM will give me, clk45, clk135, clk225, > clk315. > > Am I in the right path? Each clock line drives only two FFs, is 133 MHz > okay? > > How can I create "clk_i_inv_delayed" ? > > Best regards, > Qamrul > > > > >Qamrul > > >If you don't need super fast clock outputs, that is less than say > >12-25 MHz, you can use an internal clock at X8, X16, and a clock > >enable structure to generate such outputs. If you take care such the > >outputs are "buffered" through an I/O register, running at the X8/16, > >then you won't get any significant skew on the phases due to routing. > > >The clock enable can be a preloaded shift register, with wrap, that is > >loaded with X"0001" (X16) loaded at reset or other control condition. > >One thing that is ice about this way is that clocks can be "stopped" > >easily and restarted without any retraining or lock sequences. > > >For higher frequencies using PLL or DLL techniques to achieve the > >required outputs is probably better. > > >John Adair > >Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. > > >On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: > >> Hi All, > > >> I need to provide 8 clock outs shifted by 45 degree, > > >> clk_0 -> 0 degree phase shift > >> clk_1 -> 45 degree phase shift > >> clk_1 -> 90 degree phase shift > >> clk_1 -> 135 degree phase shift > >> clk_1 -> 180 degree phase shift > >> clk_1 -> 225 degree phase shift > >> clk_1 -> 270 degree phase shift > >> clk_1 -> 315 degree phase shift > >> clk_1 -> 360 degree phase shift > > >> Is it at all possible? > > >> Thanks in advance for your feed back. > > >> Qamrul > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com you are trying todo something that you should not. why do you need those clock phases? AnttiArticle: 143029
you are trying todo something that you should not. why do you need those clock phases? Antti I am trying to capture DATA which comes into FPGA with skew and jitter. I need to sample this data with 8 phase shifted clock and need to find the correct data through pattern matching and training. Please explain why I should not do this? Any other better way? >On Sep 15, 8:20=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: >> Thanks to all of you for useful feedback. >> >> My clock freq is 133 MHz. Based on your inputs and my understandig from >> reading "Spartan 3 FPGA Guide" this is what I plan to do. >> >> clk_i (main clock) connect it to one DCM input clock. >> 4 phased shifted output from the DCM will give me, clk90, clk180, clk >> 270. >> >> clk_i_inv_delayed ( inverted main clock delayed by 22.5 degree) connect i= >t >> to another DCM input clock. >> >> 4 phased shifted output from the DCM will give me, clk45, clk135, clk225, >> clk315. >> >> Am I in the right path? Each clock line drives only two FFs, is 133 MHz >> okay? >> >> How can I create "clk_i_inv_delayed" ? >> >> Best regards, >> Qamrul >> >> >> >> >Qamrul >> >> >If you don't need super fast clock outputs, that is less than say >> >12-25 MHz, you can use an internal clock at X8, X16, and a clock >> >enable structure to generate such outputs. If you take care such the >> >outputs are "buffered" through an I/O register, running at the X8/16, >> >then you won't get any significant skew on the phases due to routing. >> >> >The clock enable can be a preloaded shift register, with wrap, that is >> >loaded with X"0001" (X16) loaded at reset or other control condition. >> >One thing that is ice about this way is that clocks can be "stopped" >> >easily and restarted without any retraining or lock sequences. >> >> >For higher frequencies using PLL or DLL techniques to achieve the >> >required outputs is probably better. >> >> >John Adair >> >Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. >> >> >On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: >> >> Hi All, >> >> >> I need to provide 8 clock outs shifted by 45 degree, >> >> >> clk_0 -> 0 degree phase shift >> >> clk_1 -> 45 degree phase shift >> >> clk_1 -> 90 degree phase shift >> >> clk_1 -> 135 degree phase shift >> >> clk_1 -> 180 degree phase shift >> >> clk_1 -> 225 degree phase shift >> >> clk_1 -> 270 degree phase shift >> >> clk_1 -> 315 degree phase shift >> >> clk_1 -> 360 degree phase shift >> >> >> Is it at all possible? >> >> >> Thanks in advance for your feed back. >> >> >> Qamrul >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> This message was sent using the comp.arch.fpga web interface onhttp://www= >.FPGARelated.com > > > > > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143030
On Tue, 15 Sep 2009 12:43:25 -0500 "qamrul" <qamrul.hasan@spansion.com> wrote: > > [snip] > > you are trying todo something that you should not. > > why do you need those clock phases? > > Antti > > I am trying to capture DATA which comes into FPGA with skew and > jitter. I need to sample this data with 8 phase shifted clock and > need to find the correct data through pattern matching and training. > > Please explain why I should not do this? Any other better way? > Sure. You could just have one clock phase coming out of the DCM, and use the variable phase shift to get the phase right dynamically. This will give you better phase resolution and a simpler circuit. Though managing to "train" the proper phase shift is left as a serious exercise for the student. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 143031
On Sep 15, 8:43=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > you are trying todo something that you should not. > > why do you need those clock phases? > > Antti > > I am trying to capture DATA which comes into FPGA with skew and jitter. I > need to sample this data with 8 phase shifted clock and need to find the > correct data through pattern matching and training. > > Please explain why I should not do this? Any other better way? > > > > > > >On Sep 15, 8:20=3DA0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > >> Thanks to all of you for useful feedback. > > >> My clock freq is 133 MHz. Based on your inputs and my understandig > from > >> reading "Spartan 3 FPGA Guide" this is what I plan to do. > > >> clk_i (main clock) connect it to one DCM input clock. > >> 4 phased shifted output from the DCM will give me, clk90, clk180, clk > >> 270. > > >> clk_i_inv_delayed ( inverted main clock delayed by 22.5 degree) connec= t > i=3D > >t > >> to another DCM input clock. > > >> 4 phased shifted output from the DCM will give me, clk45, clk135, > clk225, > >> clk315. > > >> Am I in the right path? Each clock line drives only two FFs, is 133 > MHz > >> okay? > > >> How can I create "clk_i_inv_delayed" ? > > >> Best regards, > >> Qamrul > > >> >Qamrul > > >> >If you don't need super fast clock outputs, that is less than say > >> >12-25 MHz, you can use an internal clock at X8, X16, and a clock > >> >enable structure to generate such outputs. If you take care such the > >> >outputs are "buffered" through an I/O register, running at the X8/16, > >> >then you won't get any significant skew on the phases due to routing. > > >> >The clock enable can be a preloaded shift register, with wrap, that > is > >> >loaded with X"0001" (X16) loaded at reset or other control condition. > >> >One thing that is ice about this way is that clocks can be "stopped" > >> >easily and restarted without any retraining or lock sequences. > > >> >For higher frequencies using PLL or DLL techniques to achieve the > >> >required outputs is probably better. > > >> >John Adair > >> >Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. > > >> >On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: > >> >> Hi All, > > >> >> I need to provide 8 clock outs shifted by 45 degree, > > >> >> clk_0 -> 0 degree phase shift > >> >> clk_1 -> 45 degree phase shift > >> >> clk_1 -> 90 degree phase shift > >> >> clk_1 -> 135 degree phase shift > >> >> clk_1 -> 180 degree phase shift > >> >> clk_1 -> 225 degree phase shift > >> >> clk_1 -> 270 degree phase shift > >> >> clk_1 -> 315 degree phase shift > >> >> clk_1 -> 360 degree phase shift > > >> >> Is it at all possible? > > >> >> Thanks in advance for your feed back. > > >> >> Qamrul > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> This message was sent using the comp.arch.fpga web interface > onhttp://www=3D > >.FPGARelated.com > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com ISERDES IDELAYArticle: 143032
On Sep 15, 10:43=A0am, "qamrul" <qamrul.ha...@spansion.com> wrote: > you are trying todo something that you should not. > > why do you need those clock phases? > > Antti > > I am trying to capture DATA which comes into FPGA with skew and jitter. I > need to sample this data with 8 phase shifted clock and need to find the > correct data through pattern matching and training. > > Please explain why I should not do this? Any other better way? RTFM for Xilinx Virtex4 and 5 "SelectIO" ILOGIC blocks. It can do what you want without the ridiculous stuff you think you need.Article: 143033
On Tue, 15 Sep 2009 10:48:34 -0700, Rob Gaddi <rgaddi@technologyhighland.com> wrote: >On Tue, 15 Sep 2009 12:43:25 -0500 >"qamrul" <qamrul.hasan@spansion.com> wrote: >> >> [snip] >> >> you are trying todo something that you should not. >> >> why do you need those clock phases? >> >> Antti >> >> I am trying to capture DATA which comes into FPGA with skew and >> jitter. I need to sample this data with 8 phase shifted clock and >> need to find the correct data through pattern matching and training. >> >> Please explain why I should not do this? Any other better way? >> > >Sure. You could just have one clock phase coming out of the DCM, and >use the variable phase shift to get the phase right dynamically. This >will give you better phase resolution and a simpler circuit. Though >managing to "train" the proper phase shift is left as a serious >exercise for the student. He seems to be working a clock recovery application which means to do the training you mention, first he needs to get a phase error. He wants to use 8x oversampled data as a phase detector, the output of which he'll need to filter and use as the input to the variable phase shift control. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 143034
Andy Peters <google@latke.net> wrote:
>On Sep 15, 10:43=A0am, "qamrul" <qamrul.ha...@spansion.com> wrote:
>> you are trying todo something that you should not.
>>
>> why do you need those clock phases?
>>
>> Antti
>>
>> I am trying to capture DATA which comes into FPGA with skew and jitter. I
>> need to sample this data with 8 phase shifted clock and need to find the
>> correct data through pattern matching and training.
>>
>> Please explain why I should not do this? Any other better way?
>
>RTFM for Xilinx Virtex4 and 5 "SelectIO" ILOGIC blocks. It can do what
>you want without the ridiculous stuff you think you need.
Perhaps Spartan 6 is a better choice if he is concerned with costs.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143035Nico Coesel <nico@puntnl.niks> wrote: > Andy Peters <google@latke.net> wrote: ... > >RTFM for Xilinx Virtex4 and 5 "SelectIO" ILOGIC blocks. It can do what > >you want without the ridiculous stuff you think you need. > Perhaps Spartan 6 is a better choice if he is concerned with costs. Doesn't the Virtex have deeper ILOGIC? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143036
Hi, In my design I have to delay 8 clock lines (i can't delay the data line). Can I drive the Data input and the clock input with CLK coming into the FPGA at 133 MHz? Thanks Qamrul >Nico Coesel <nico@puntnl.niks> wrote: >> Andy Peters <google@latke.net> wrote: > >... >> >RTFM for Xilinx Virtex4 and 5 "SelectIO" ILOGIC blocks. It can do what >> >you want without the ridiculous stuff you think you need. > >> Perhaps Spartan 6 is a better choice if he is concerned with costs. > >Doesn't the Virtex have deeper ILOGIC? >-- >Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > >Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >--------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143037
Brian Drummond wrote: > My favourite (unnoticed by its authors) was on a slide, presented by Motorola, > describing the features of a new chip - or rather, since they hadn't built it > yet - describing what they wanted us to believe the chip would do. > And the slide was titled... > > Specifiction Perfect, since fiction is often based on a true story ;)Article: 143038
On Sep 15, 9:01=A0am, Antti wrote: > is not possible to create models that use all different features of > the block ram primitives for all 5 vendors > > of course i would be nice to have generic models that do it all > for all vendors and all synthesis tools, > but as of today it isnt possible No, but it is possible to get very close. That's why the download I offered has not only a discussion paper but no fewer than twelve different RAM models, all in both VHDL and Verilog, covering a wide range of commonly needed functionality; most of the models synthesize correctly on all the major vendors' FPGAs, although there are some models that use features that simply don't exist on some FPGAs. Only in a very few cases did I find limitations caused by synthesis tools rather than by devices. I don't think the OpenCores material comes anywhere near that breadth of coverage. And I don't want to contribute them to OC, because they aren't cores - the last thing in the world I want is for people to use them as complete modules. They are code fragments that could be incorporated into the code for your behavioral-style designs. -- Jonathan BromleyArticle: 143039
On 15 Sep., 19:43, "qamrul" <qamrul.ha...@spansion.com> wrote: > you are trying todo something that you should not. > > why do you need those clock phases? > > Antti > > I am trying to capture DATA which comes into FPGA with skew and jitter. I > need to sample this data with 8 phase shifted clock and need to find the > correct data through pattern matching and training. > > Please explain why I should not do this? Any other better way? You could use one 1064MHz clock. Kolja Sulimma cronologic.deArticle: 143040
On Sep 16, 2:41=A0pm, Kolja <ksuli...@googlemail.com> wrote: > On 15 Sep., 19:43, "qamrul" <qamrul.ha...@spansion.com> wrote: > > > you are trying todo something that you should not. > > > why do you need those clock phases? > > > Antti > > > I am trying to capture DATA which comes into FPGA with skew and jitter.= I > > need to sample this data with 8 phase shifted clock and need to find th= e > > correct data through pattern matching and training. > > > Please explain why I should not do this? Any other better way? > > You could use one 1064MHz clock. > > Kolja Sulimma > cronologic.de :) you are thinking amongst same lines as I attempt to use 8x pahses of 135MHz is actual resolution of 1064MHz so while it may be doable withing low cost fabric, one should be VERY familiar with "DIRT" constrains, but i bet those who are are not asking help at c.a.f. using 1064 direclty is also possible, as i have measured actual clock in the fabric of slowest speed grade V-4 about 975MHz (real measurement not simulation!) so fastest V-4 should do 1064mhz AnttiArticle: 143041
"qamrul" <qamrul.hasan@spansion.com> wrote:
>Hi,
>
>In my design I have to delay 8 clock lines (i can't delay the data line).
>Can I drive the Data input and the clock input with CLK coming into the
>FPGA at 133 MHz?
IIRC the Spartan 6 has serdes. This means you can deserialize the
incoming data. So you will be sampling the input with a multiple of
133MHz and get parallel outputs without the headache of crossing 8
clock domains. You could also user an external deserializer. It all
depends on costs versus board space.
>Thanks
>Qamrul
>
>>Nico Coesel <nico@puntnl.niks> wrote:
>>> Andy Peters <google@latke.net> wrote:
>>
>>...
>>> >RTFM for Xilinx Virtex4 and 5 "SelectIO" ILOGIC blocks. It can do
>what
>>> >you want without the ridiculous stuff you think you need.
>>
>>> Perhaps Spartan 6 is a better choice if he is concerned with costs.
>>
>>Doesn't the Virtex have deeper ILOGIC?
>>--
>>Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
>>
>>Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
>>--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>>
>
>---------------------------------------
>This message was sent using the comp.arch.fpga web interface on
>http://www.FPGARelated.com
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143042On Sep 15, 10:20=A0am, "qamrul" <qamrul.ha...@spansion.com> wrote: > Thanks to all of you for useful feedback. > > My clock freq is 133 MHz. Based on your inputs and my understandig from > reading "Spartan 3 FPGA Guide" this is what I plan to do. > > clk_i (main clock) connect it to one DCM input clock. > 4 phased shifted output from the DCM will give me, clk90, clk180, clk > 270. > > clk_i_inv_delayed ( inverted main clock delayed by 22.5 degree) connect i= t > to another DCM input clock. > > 4 phased shifted output from the DCM will give me, clk45, clk135, clk225, > clk315. > > Am I in the right path? Each clock line drives only two FFs, is 133 MHz > okay? > > How can I create "clk_i_inv_delayed" ? > > Best regards, > Qamrul > > > > > > >Qamrul > > >If you don't need super fast clock outputs, that is less than say > >12-25 MHz, you can use an internal clock at X8, X16, and a clock > >enable structure to generate such outputs. If you take care such the > >outputs are "buffered" through an I/O register, running at the X8/16, > >then you won't get any significant skew on the phases due to routing. > > >The clock enable can be a preloaded shift register, with wrap, that is > >loaded with X"0001" (X16) loaded at reset or other control condition. > >One thing that is ice about this way is that clocks can be "stopped" > >easily and restarted without any retraining or lock sequences. > > >For higher frequencies using PLL or DLL techniques to achieve the > >required outputs is probably better. > > >John Adair > >Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. > > >On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: > >> Hi All, > > >> I need to provide 8 clock outs shifted by 45 degree, > > >> clk_0 -> 0 degree phase shift > >> clk_1 -> 45 degree phase shift > >> clk_1 -> 90 degree phase shift > >> clk_1 -> 135 degree phase shift > >> clk_1 -> 180 degree phase shift > >> clk_1 -> 225 degree phase shift > >> clk_1 -> 270 degree phase shift > >> clk_1 -> 315 degree phase shift > >> clk_1 -> 360 degree phase shift > > >> Is it at all possible? > > >> Thanks in advance for your feed back. > > >> Qamrul > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com Do you need 8 phases? Have you read the relevant Xilinx app notes such as xapp224 that use this technique, even in the low cost FPGAs? kevinArticle: 143043
On Sep 16, 7:59=A0pm, kevin93 <ke...@whitedigs.com> wrote: > On Sep 15, 10:20=A0am, "qamrul" <qamrul.ha...@spansion.com> wrote: > > > > > Thanks to all of you for useful feedback. > > > My clock freq is 133 MHz. Based on your inputs and my understandig from > > reading "Spartan 3 FPGA Guide" this is what I plan to do. > > > clk_i (main clock) connect it to one DCM input clock. > > 4 phased shifted output from the DCM will give me, clk90, clk180, clk > > 270. > > > clk_i_inv_delayed ( inverted main clock delayed by 22.5 degree) connect= it > > to another DCM input clock. > > > 4 phased shifted output from the DCM will give me, clk45, clk135, clk22= 5, > > clk315. > > > Am I in the right path? Each clock line drives only two FFs, is 133 MHz > > okay? > > > How can I create "clk_i_inv_delayed" ? > > > Best regards, > > Qamrul > > > >Qamrul > > > >If you don't need super fast clock outputs, that is less than say > > >12-25 MHz, you can use an internal clock at X8, X16, and a clock > > >enable structure to generate such outputs. If you take care such the > > >outputs are "buffered" through an I/O register, running at the X8/16, > > >then you won't get any significant skew on the phases due to routing. > > > >The clock enable can be a preloaded shift register, with wrap, that is > > >loaded with X"0001" (X16) loaded at reset or other control condition. > > >One thing that is ice about this way is that clocks can be "stopped" > > >easily and restarted without any retraining or lock sequences. > > > >For higher frequencies using PLL or DLL techniques to achieve the > > >required outputs is probably better. > > > >John Adair > > >Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. > > > >On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: > > >> Hi All, > > > >> I need to provide 8 clock outs shifted by 45 degree, > > > >> clk_0 -> 0 degree phase shift > > >> clk_1 -> 45 degree phase shift > > >> clk_1 -> 90 degree phase shift > > >> clk_1 -> 135 degree phase shift > > >> clk_1 -> 180 degree phase shift > > >> clk_1 -> 225 degree phase shift > > >> clk_1 -> 270 degree phase shift > > >> clk_1 -> 315 degree phase shift > > >> clk_1 -> 360 degree phase shift > > > >> Is it at all possible? > > > >> Thanks in advance for your feed back. > > > >> Qamrul > > > --------------------------------------- =A0 =A0 =A0 =A0 > > This message was sent using the comp.arch.fpga web interface onhttp://w= ww.FPGARelated.com > > Do you need 8 phases? > > Have you read the relevant Xilinx app notes such as xapp224 that use > this technique, even in the low cost FPGAs? > > kevin he hasntArticle: 143044
Kolja wrote: > On 15 Sep., 19:43, "qamrul" <qamrul.ha...@spansion.com> wrote: >> >> Please explain why I should not do this? Any other better way? > > You could use one 1064MHz clock. > > Kolja Sulimma > cronologic.de He really could do that if he used the MGTs. IIRC you can lock the sample clock to the reference, so he could sample at 6G if the fancy took him. I think that's how the MGTs work in STM-4 / OC 12 mode. Cheers, Syms.Article: 143045
PSoC 3, build report says this:
Warp Verilog Synthesis Compiler: Version 6.3 IR 41
Copyright (C) 1991-2001 Cypress Semiconductor
------------------------------------------------------------
Technology mapping summary
------------------------------------------------------------
Resource Type : Used : Free : Max : % Used
====================================================
Macrocells : 0 : 192 : 192 : 0.00%
Unique Pterms : 0 : 384 : 384 : 0.00%
Total Pterms : 0 : 384 : 384 : 0.00%
IO Cells : 3 : 69 : 72 : 4.17%
Datapath Cells : 0 : 24 : 24 : 0.00%
Control Cells : 0 : 24 : 24 : 0.00%
Drqs : 0 : 24 : 24 : 0.00%
Interrupts : 0 : 32 : 32 : 0.00%
DSM Fixed Blocks : 0 : 1 : 1 : 0.00%
VIDAC Fixed Blocks : 0 : 4 : 4 : 0.00%
SC Fixed Blocks : 0 : 4 : 4 : 0.00%
Comparator Fixed Blocks : 0 : 4 : 4 : 0.00%
Opamp Fixed Blocks : 0 : 4 : 4 : 0.00%
CapSense Buffers : 0 : 2 : 2 : 0.00%
CAN Fixed Blocks : 0 : 1 : 1 : 0.00%
Decimator Fixed Blocks : 0 : 1 : 1 : 0.00%
I2C Fixed Blocks : 0 : 1 : 1 : 0.00%
Timer Fixed Blocks : 0 : 4 : 4 : 0.00%
DFB Fixed Blocks : 0 : 1 : 1 : 0.00%
USB Fixed Blocks : 0 : 1 : 1 : 0.00%
LCD Fixed Blocks : 0 : 1 : 1 : 0.00%
EMIF Fixed Blocks : 0 : 1 : 1 : 0.00%
LPF Fixed Blocks : 0 : 2 : 2 : 0.00%
Status Cells : 0 : 24 : 24 : 0.00%
Count7 Cells : 0 : 24 : 24 : 0.00%
cool :)
Antti
Article: 143046
On Sep 17, 8:14=A0pm, Antti <antti.luk...@googlemail.com> wrote:
> PSoC 3, build report says this:
>
> =A0Warp Verilog Synthesis Compiler: Version 6.3 IR 41
> =A0 Copyright (C) 1991-2001 Cypress Semiconductor
>
> ------------------------------------------------------------
> Technology mapping summary
> ------------------------------------------------------------
>
> =A0 =A0 =A0 =A0 =A0 =A0 Resource Type : Used : Free : =A0Max : =A0% Used
> =A0 =A0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Macrocells : =A0 =A00 : =A0192 : =A0192 : =
=A0 0.00%
> =A0 =A0 =A0 =A0 =A0 =A0 Unique Pterms : =A0 =A00 : =A0384 : =A0384 : =A0 =
0.00%
> =A0 =A0 =A0 =A0 =A0 =A0 =A0Total Pterms : =A0 =A00 : =A0384 : =A0384 : =
=A0 0.00%
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IO Cells : =A0 =A03 : =A0 69 : =A0 72 =
: =A0 4.17%
> =A0 =A0 =A0 =A0 =A0 =A0Datapath Cells : =A0 =A00 : =A0 24 : =A0 24 : =A0 =
0.00%
> =A0 =A0 =A0 =A0 =A0 =A0 Control Cells : =A0 =A00 : =A0 24 : =A0 24 : =A0 =
0.00%
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Drqs : =A0 =A00 : =A0 24 : =A0=
24 : =A0 0.00%
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Interrupts : =A0 =A00 : =A0 32 : =A0 32 : =
=A0 0.00%
> =A0 =A0 =A0 =A0 =A0DSM Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> =A0 =A0 =A0 =A0VIDAC Fixed Blocks : =A0 =A00 : =A0 =A04 : =A0 =A04 : =A0 =
0.00%
> =A0 =A0 =A0 =A0 =A0 SC Fixed Blocks : =A0 =A00 : =A0 =A04 : =A0 =A04 : =
=A0 0.00%
> =A0 Comparator Fixed Blocks : =A0 =A00 : =A0 =A04 : =A0 =A04 : =A0 0.00%
> =A0 =A0 =A0 =A0Opamp Fixed Blocks : =A0 =A00 : =A0 =A04 : =A0 =A04 : =A0 =
0.00%
> =A0 =A0 =A0 =A0 =A0CapSense Buffers : =A0 =A00 : =A0 =A02 : =A0 =A02 : =
=A0 0.00%
> =A0 =A0 =A0 =A0 =A0CAN Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> =A0 =A0Decimator Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =A0 0.00=
%
> =A0 =A0 =A0 =A0 =A0I2C Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> =A0 =A0 =A0 =A0Timer Fixed Blocks : =A0 =A00 : =A0 =A04 : =A0 =A04 : =A0 =
0.00%
> =A0 =A0 =A0 =A0 =A0DFB Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> =A0 =A0 =A0 =A0 =A0USB Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> =A0 =A0 =A0 =A0 =A0LCD Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> =A0 =A0 =A0 =A0 EMIF Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =A0 =
0.00%
> =A0 =A0 =A0 =A0 =A0LPF Fixed Blocks : =A0 =A00 : =A0 =A02 : =A0 =A02 : =
=A0 0.00%
> =A0 =A0 =A0 =A0 =A0 =A0 =A0Status Cells : =A0 =A00 : =A0 24 : =A0 24 : =
=A0 0.00%
> =A0 =A0 =A0 =A0 =A0 =A0 =A0Count7 Cells : =A0 =A00 : =A0 24 : =A0 24 : =
=A0 0.00%
>
> cool :)
>
> Antti
and a Nice 8051 core too ;)
192MC is ok, but that 384 PT is going to be the real ceiling...
Since you have the tools there Antti, some questions
a) Do Cypress include the source code for their UDB Blocks ?
b) What languages does this support ?
Verilog by the looks - What about VHDL ?, ABEL ?
c) If you have silicon, how fast can the CPLD area clock ?
-jg
Article: 143047Hi everyone, does anyone on this list have a pointer to a (freely available) JEDEC file disassembler that also supports N82S153 (PLS153) or at least a document showing which bit in the JEDEC file maps to what fuse in the PLS153? Unfortunately, also the N82S153 datasheet on alldatasheets.com doesn't really help (unless someone could confirm that the order of bits in the explained TWX format is the same order as in the JEDEC fusemap). Regards, RainerArticle: 143048
Does anybody know if this is a known issue, I couldn't find information in the manuals...Article: 143049
Karel Deprez <karel.deprez@skynet.be> wrote: > Does anybody know if this is a known issue, I couldn't find > information in the manuals... Did you try 11.3? It just cam out, you have to download a 2+ GB files. Perhaps is addresses the issue. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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