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Messages from 143050

Article: 143050
Subject: Re: 82S153 Fuse Map / Disassembler
From: Andy <jonesandy@comcast.net>
Date: Thu, 17 Sep 2009 06:40:32 -0700 (PDT)
Links: << >>  << T >>  << A >>
You might look for simulation models of it. I've seen vhdl models for
PALs, etc. that read the jedec file and configure the model
accordingly.

While they may not "disassemble" the file to the higher level you
want, at least you could configure an emulator with it.

Andy

Article: 143051
Subject: Re: WARP PLD's are back in new shape
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Thu, 17 Sep 2009 08:15:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 17, 12:20=A0pm, -jg <jim.granvi...@gmail.com> wrote:
> On Sep 17, 8:14=A0pm, Antti <antti.luk...@googlemail.com> wrote:
>
>
>
> > PSoC 3, build report says this:
>
> > =A0Warp Verilog Synthesis Compiler: Version 6.3 IR 41
> > =A0 Copyright (C) 1991-2001 Cypress Semiconductor
>
> > ------------------------------------------------------------
> > Technology mapping summary
> > ------------------------------------------------------------
>
> > =A0 =A0 =A0 =A0 =A0 =A0 Resource Type : Used : Free : =A0Max : =A0% Use=
d
> > =A0 =A0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Macrocells : =A0 =A00 : =A0192 : =A0192 =
: =A0 0.00%
> > =A0 =A0 =A0 =A0 =A0 =A0 Unique Pterms : =A0 =A00 : =A0384 : =A0384 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0Total Pterms : =A0 =A00 : =A0384 : =A0384 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IO Cells : =A0 =A03 : =A0 69 : =A0 7=
2 : =A0 4.17%
> > =A0 =A0 =A0 =A0 =A0 =A0Datapath Cells : =A0 =A00 : =A0 24 : =A0 24 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0 =A0 Control Cells : =A0 =A00 : =A0 24 : =A0 24 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Drqs : =A0 =A00 : =A0 24 : =
=A0 24 : =A0 0.00%
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Interrupts : =A0 =A00 : =A0 32 : =A0 32 =
: =A0 0.00%
> > =A0 =A0 =A0 =A0 =A0DSM Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0VIDAC Fixed Blocks : =A0 =A00 : =A0 =A04 : =A0 =A04 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0 SC Fixed Blocks : =A0 =A00 : =A0 =A04 : =A0 =A04 : =
=A0 0.00%
> > =A0 Comparator Fixed Blocks : =A0 =A00 : =A0 =A04 : =A0 =A04 : =A0 0.00=
%
> > =A0 =A0 =A0 =A0Opamp Fixed Blocks : =A0 =A00 : =A0 =A04 : =A0 =A04 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0CapSense Buffers : =A0 =A00 : =A0 =A02 : =A0 =A02 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0CAN Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> > =A0 =A0Decimator Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =A0 0.=
00%
> > =A0 =A0 =A0 =A0 =A0I2C Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0Timer Fixed Blocks : =A0 =A00 : =A0 =A04 : =A0 =A04 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0DFB Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0USB Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0LCD Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 EMIF Fixed Blocks : =A0 =A00 : =A0 =A01 : =A0 =A01 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0LPF Fixed Blocks : =A0 =A00 : =A0 =A02 : =A0 =A02 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0Status Cells : =A0 =A00 : =A0 24 : =A0 24 : =
=A0 0.00%
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0Count7 Cells : =A0 =A00 : =A0 24 : =A0 24 : =
=A0 0.00%
>
> > cool :)
>
> > Antti
>
> and a Nice 8051 core too ;)
>
> 192MC is ok, but that 384 PT is going to be the real ceiling...
>
> Since you have the tools there Antti, some questions
> a) Do Cypress include =A0the source code for their UDB Blocks ?
> b) What languages does this support ?
> =A0 =A0 Verilog by the looks - What about VHDL ?, ABEL ?
> c) If you have silicon, how fast can the CPLD area clock ?
>
> -jg

ah i am just writing september brain :)

you can download and try yourself
i spent some 15 minutes cant tell much yet
and no i dont have hardware yet :(

Antti

Article: 143052
Subject: Quartus top level entity name vs names of generated files
From: "Niieg" <stefan.nagel@kit.edu>
Date: Thu, 17 Sep 2009 10:28:23 -0500
Links: << >>  << T >>  << A >>
Hi everybody,
is it possible to generate all the names with an other name than that of
the top level entity in Alteras Quartus?

I want it like this:
project: my_choice.qpf
top level entity: my_top.v
generated files: my_choice.rbf, my_choice.fit.rpt, my_choice.flow.rpt,
my_choice.pin, ... etc

Quartus does this:
project: my_choice.qpf
top level entity: my_top.v
generated files: my_top.rbf, my_top.fit.rpt, my_top.flow.rpt, my_top.pin,
... etc


Kind regards and thank you	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

Article: 143053
Subject: Re: Quartus top level entity name vs names of generated files
From: Andy <jonesandy@comcast.net>
Date: Thu, 17 Sep 2009 09:09:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 17, 10:28=A0am, "Niieg" <stefan.na...@kit.edu> wrote:
> Hi everybody,
> is it possible to generate all the names with an other name than that of
> the top level entity in Alteras Quartus?
>
> I want it like this:
> project: my_choice.qpf
> top level entity: my_top.v
> generated files: my_choice.rbf, my_choice.fit.rpt, my_choice.flow.rpt,
> my_choice.pin, ... etc
>
> Quartus does this:
> project: my_choice.qpf
> top level entity: my_top.v
> generated files: my_top.rbf, my_top.fit.rpt, my_top.flow.rpt, my_top.pin,
> ... etc
>
> Kind regards and thank you =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> This message was sent using the comp.arch.fpga web interface onhttp://www=
.FPGARelated.com

I don't know if there is a Quartus-based solution to this, but you
could create different "wrapper" entities, whose names reflect the
name of the project in which they are used.

Andy

Article: 143054
Subject: Re: 82S153 Fuse Map / Disassembler
From: buchty@atbode100.lrr.in.tum.de (Rainer Buchty)
Date: Thu, 17 Sep 2009 18:16:03 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <6875efc3-68cd-479e-adca-432525a3d340@q35g2000vbi.googlegroups.com>,
 Andy <jonesandy@comcast.net> writes:
|> You might look for simulation models of it. I've seen vhdl models for
|> PALs, etc. that read the jedec file and configure the model
|> accordingly.
|> 
|> While they may not "disassemble" the file to the higher level you
|> want, at least you could configure an emulator with it.

Didn't find any. But since I had a JEDEC file at my hands where I also
possess the equations, it was rather simple to rev-engineer the fusemap
as laid out in the JEDEC file.

Rainer


Article: 143055
Subject: Re: To Xilinx: Regarding the download manager
From: Michael Schwingen <news-1235297497@discworld.dascon.de>
Date: 17 Sep 2009 22:12:29 GMT
Links: << >>  << T >>  << A >>
On 2009-09-14, LittleAlex <alex.louie@email.com> wrote:
> Regarding the use of 'entitlenow' to download from your web site:  May
> I respectfully request that you gather together everyone at Xilinx
> that thought that this was a good idea, drag them out to the parking
> lot, and beat them with a cricket bat until they promise to never do
> anything this foolish ever again.
>
> I am running a modern OS, with the latest browser and a very current
> copy of Java.  I do not recall ever having so many problems
> downloading updates.  Crashes, hangs, bad file names, errant pop-ups,
> you name it.

Full ACK.

No crashes, but first entitlenow did not like my existing account (which had
all information entered, and worked fine for the previous downloads). It
sent me back to Xilinx to fill in "missing information" without specifying
what was wrong. I filled *all* fields - still no luck.

After creating a new account, entitlenow complained about non-ascii
characters. How am I supposed to enter accurate information if I can't
correctly enter the address?

This is on a Debian Linux box with the latest Firefox version.

Linux has one good side: the ActiveX downloader failed to install, and when
closing the popup, I finally got a normal "save as" dialog.

cu
Michael

Article: 143056
Subject: VHDL: obtaining the length of a record
From: "tmueller" <till.c.mueller@web.de>
Date: Thu, 17 Sep 2009 19:57:38 -0500
Links: << >>  << T >>  << A >>
Hi,

I need to get the length of a record in order to set an integer constant,
like this:

type T_MyRecord is record
  element_1 : unsigned (3 downto 0);
  element_2 : unsigned (2 downto 0);
end record T_MyRecord;

constant REC_LENGTH : integer := T_MyRecord'length -- should set
REC_LENGTH to 7

But this method gives me an error ("Unconstrained array type is used as
prefix for attribute length.")

Is this at all possible or do I have to work through functions and convert
the record to a vector first? Several parameters will possibly be
added/removed to/from the record later on, so a generic solution would be
preferrable.

Thanks for your help in advance,
Till



Article: 143057
Subject: Memory Interface Generator
From: "mlin" <maddie.gun@gmail.com>
Date: Thu, 17 Sep 2009 19:57:49 -0500
Links: << >>  << T >>  << A >>
Hi,

I am using MIG v2.1 that targets spartan 3 starter kit. I want to know, if
sram on the starter board could be accessed using MIG and if the MIG is
used for accessing memory development boards?

Thanks in advance!



Article: 143058
Subject: Re: Looking for Virtex-6 PCIe development board
From: "richk" <richk@pentek.com>
Date: Thu, 17 Sep 2009 19:58:15 -0500
Links: << >>  << T >>  << A >>
>Does anyone know of anyone that can shp a Virtex-6 PCIe development
>board (within about 4 weeks)?
>
>Xilinx still doesn't seem to have their evaluation/development kits
>for Virtex-6 ready to ship.
>

I don't know of a development board available yet, however their is a
Virtex-6 LX240T available for purchase on ebay.

http://cgi.ebay.com/Xilinx-Virtex-6-LX240T-FPGA-XC6VLX240T-1FF1159CES_W0QQitemZ290350044058QQcmdZViewItemQQptZLH_DefaultDomain_0?hash=item439a36139a&_trksid=p3286.c0.m14




Article: 143059
Subject: Re: 8 phase clock output
From: "sylvain_azarian" <sylvain.azarian@gmail.com>
Date: Thu, 17 Sep 2009 19:58:29 -0500
Links: << >>  << T >>  << A >>
>On Sep 15, 10:43=A0am, "qamrul" <qamrul.ha...@spansion.com> wrote:
>> you are trying todo something that you should not.
>>
>> why do you need those clock phases?
>>
>> Antti
>>
>> I am trying to capture DATA which comes into FPGA with skew and jitter.
I
>> need to sample this data with 8 phase shifted clock and need to find
the
>> correct data through pattern matching and training.
>>
>> Please explain why I should not do this? Any other better way?
>
>RTFM for Xilinx Virtex4 and 5 "SelectIO" ILOGIC blocks. It can do what
>you want without the ridiculous stuff you think you need.
>

Why not implement a DDS creating the main clock, then just add the phase
shift you need ?



Article: 143060
Subject: Re: VHDL: obtaining the length of a record
From: KJ <kkjennings@sbcglobal.net>
Date: Thu, 17 Sep 2009 18:04:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 17, 8:57=A0pm, "tmueller" <till.c.muel...@web.de> wrote:
> Hi,
>
> I need to get the length of a record in order to set an integer constant,
> like this:
>
> type T_MyRecord is record
> =A0 element_1 : unsigned (3 downto 0);
> =A0 element_2 : unsigned (2 downto 0);
> end record T_MyRecord;
>
> constant REC_LENGTH : integer :=3D T_MyRecord'length -- should set
> REC_LENGTH to 7
>
> But this method gives me an error ("Unconstrained array type is used as
> prefix for attribute length.")
>

That's because records to not have a length.

> Is this at all possible or do I have to work through functions and conver=
t
> the record to a vector first?

You need to convert it to a vector in order to get a length.  Before
you dismiss that though, I'd be willing to bet that in your design
you'll be wanting to convert to/from vectors anyway for other
reasons.  So creating a 'to_std_logic_vector' and a
'from_std_logic_vector' function for this record will be worth the
effort.  Put those functions in the same package that you define the
record.

KJ

Article: 143061
Subject: Re: Memory Interface Generator
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Thu, 17 Sep 2009 18:06:36 -0700
Links: << >>  << T >>  << A >>
On Thu, 17 Sep 2009 19:57:49 -0500
"mlin" <maddie.gun@gmail.com> wrote:

> Hi,
> 
> I am using MIG v2.1 that targets spartan 3 starter kit. I want to
> know, if sram on the starter board could be accessed using MIG and if
> the MIG is used for accessing memory development boards?
> 
> Thanks in advance!
> 
> 

MIG is for talking to DRAMs, which are complicated.  SRAM is
easy: there are data lines and address lines and it just does what you
ask it to.  The interface is trivial enough to implement that I'd be
surprised if anyone has a core to do it; it would mostly just be wires. 

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 143062
Subject: Re: Looking for Virtex-6 PCIe development board
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Thu, 17 Sep 2009 18:57:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 25, 10:22=A0pm, Poojan Wagh <poojanw...@gmail.com> wrote:
> Does anyone know of anyone that can shp a Virtex-6 PCIe development
> board (within about 4 weeks)?
>
> Xilinx still doesn't seem to have their evaluation/development kits
> for Virtex-6 ready to ship.

The first V-6 PCIe board that will be available for sale and ship to
customers will be the ML605.  If you need this and haven't place an
order yet, you really should place the order.

Ed McGettigan
--
Xilinx Inc.

Article: 143063
Subject: Re: Looking for Virtex-6 PCIe development board
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Thu, 17 Sep 2009 19:01:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 17, 5:58=A0pm, "richk" <ri...@pentek.com> wrote:
> >Does anyone know of anyone that can shp a Virtex-6 PCIe development
> >board (within about 4 weeks)?
>
> >Xilinx still doesn't seem to have their evaluation/development kits
> >for Virtex-6 ready to ship.
>
> I don't know of a development board available yet, however their is a
> Virtex-6 LX240T available for purchase on ebay.
>
> http://cgi.ebay.com/Xilinx-Virtex-6-LX240T-FPGA-XC6VLX240T-1FF1159CES...

I'm a bit disconcerted about this ebay auction.  Anyone that decides
to plunk down $3800 for the part should know up front that this isn't
a -1CES part.  This part has a SCD number attached to it which means
that it has been tested under different conditions.  The online errata
for the LX240T-1CES does not apply to this part.

Ed McGettigan
--
Xilinx Inc.


Article: 143064
Subject: Re: 8 phase clock output
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Thu, 17 Sep 2009 20:35:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 18, 3:58=A0am, "sylvain_azarian" <sylvain.azar...@gmail.com>
wrote:
> >On Sep 15, 10:43=3DA0am, "qamrul" <qamrul.ha...@spansion.com> wrote:
> >> you are trying todo something that you should not.
>
> >> why do you need those clock phases?
>
> >> Antti
>
> >> I am trying to capture DATA which comes into FPGA with skew and jitter=
.
> I
> >> need to sample this data with 8 phase shifted clock and need to find
> the
> >> correct data through pattern matching and training.
>
> >> Please explain why I should not do this? Any other better way?
>
> >RTFM for Xilinx Virtex4 and 5 "SelectIO" ILOGIC blocks. It can do what
> >you want without the ridiculous stuff you think you need.
>
> Why not implement a DDS creating the main clock, then just add the phase
> shift you need ?- Hide quoted text -
>
> - Show quoted text -

for the resolution he desires the DDS clock should be 2128mhz or so
thats why

Antti

Article: 143065
Subject: Re: To Xilinx: Regarding the download manager
From: Kim Enkovaara <kim.enkovaara@iki.fi>
Date: Fri, 18 Sep 2009 08:28:18 +0300
Links: << >>  << T >>  << A >>
Michael Schwingen wrote:
> No crashes, but first entitlenow did not like my existing account (which had
> all information entered, and worked fine for the previous downloads). It
> sent me back to Xilinx to fill in "missing information" without specifying
> what was wrong. I filled *all* fields - still no luck.

I had the same problem with my account, but Xilinx managed to fix the
account after few trials, and there was no need for new account (and
the hassle of moving all licenses there etc.)

But has anyone seen xilinx update crashing in Win XP. For me it
seems to crash with all the machines I have tried (about 5-10) ;) It
has gotten worse over the time. It may be able to update one component
at a time, but not even that always.

And I agree with the download manager, it's horrible. Fortunately the SW
can be ordered on DVD. Maybe the idea is to force people to use DVDs and
not use network bandwidth ;)

--Kim

Article: 143066
Subject: Re: Quartus top level entity name vs names of generated files
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Fri, 18 Sep 2009 10:37:09 +0200
Links: << >>  << T >>  << A >>
"Niieg" <stefan.nagel@kit.edu> writes:

> Hi everybody,
> is it possible to generate all the names with an other name than that of
> the top level entity in Alteras Quartus?
>
> I want it like this:
> project: my_choice.qpf
> top level entity: my_top.v
> generated files: my_choice.rbf, my_choice.fit.rpt, my_choice.flow.rpt,
> my_choice.pin, ... etc

You can certainly do it from a tcl script:

$ ls -1
compile.tcl
my_top.v
$ quartus_sh -t compile.tcl
...
$ ls -1 my_choice.*
my_choice.asm.rpt
my_choice.done
my_choice.fit.rpt
my_choice.fit.smsg
my_choice.fit.summary
my_choice.flow.rpt
my_choice.map.rpt
my_choice.map.summary
my_choice.pin
my_choice.pof
my_choice.qpf
my_choice.qsf
my_choice.rbf
my_choice.sof
my_choice.tan.rpt

Here's compile.tcl:

# -*-Mode: tcl;-*-

set tstart [clock seconds]

set project my_choice
set source my_top.v
set top my_top
set family stratix
set device ep1s10f780c6

if {! [project_exists $project]} {
    project_new $project
} else {
    project_open $project
}

# proc to set pin locations
proc pin_loc {net pin ios} {
    set_instance_assignment -name IO_STANDARD -to $net $ios
    set_location_assignment -to $net Pin_$pin
}

set_global_assignment -name family $family
set_global_assignment -name device $device

set_global_assignment -name USER_LIBRARIES .

set_global_assignment -name FOCUS_ENTITY_NAME "|$top"

foreach file $source {
    set_global_assignment -name VERILOG_FILE $file
}

# assign pins

set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"

pin_loc pad_reconf_req_   U2    LVTTL
pin_loc pad_rst_          AC9   LVTTL
pin_loc pad_clk           K17   LVTTL
pin_loc pad_clk_out       E15   LVTTL

# serial port
pin_loc pad_txd           U21   LVTTL
pin_loc pad_rxd           Y28   LVTTL


# programming files
set_global_assignment -name GENERATE_RBF_FILE ON

# speed up compilation
set_global_assignment -name SPEED_DISK_USAGE_TRADEOFF Smart

package require ::quartus::flow
execute_flow -compile


set tend    [clock seconds]
set secs    [expr $tend - $tstart]
set hours   [expr $secs / 3600]
set minutes [expr ($secs % 3600) / 60]

puts  "total run time [format "%d:%02d" $hours $minutes] ($secs seconds)"

exit


Doing it this way makes it easy to clean the directory:

$rm -fr my_choice* db incremental_db

Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 143067
Subject: FPGA for acoustic adaptive beamforming
From: DOD <domenicodonisi@libero.it>
Date: Fri, 18 Sep 2009 03:53:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

i'm not an expert user of FPGA but i need to solve a problem before
starting to work on it.
I have to choose an FPGA to implement an acoustic beam forming. My
system has 512 input channels (microphones). After A/D conversion at
48 KHz with 24 bit per sample i need to have all the 512 signals
syncronysed to perform the beamforming. So far i have read that Xilinx
tools and FPGA (Spartan or Virtex) should fix my problem but i have
difficulties in choosing the right model.
From a SW point of view I'd like to implement my model on Simulik,
translate it into VHDL and then put the code into FPGA. DO you think
that Xilinx products could solve my problem and which model do you
suggest to buy?
The FPGA + SW at about what price is sold? Please any suggestion could
be very useful for me. Thanks in advance for your help.

Article: 143068
Subject: Re: xc3sprog
From: "theom" <theobjectmachine@gmail.com>
Date: Fri, 18 Sep 2009 08:43:15 -0500
Links: << >>  << T >>  << A >>
>On Feb 6, 12:45 am, dim...@gmail.com wrote:
>
>> Current version of xc3sprog in SVN incorporates all of the patches
>> submitted
>> so far. I pulled them in a couple of days ago, partially in response
>> to this
>> thread. Please submit your new patches - I will try to keep the
>> project
>> up to date.
>
>I've sent you my patches to your gmail address.
>Please let me know if you've received them.
>
>--
>mmihai
>
>

Hi

Hope this thread is still alive :)

I've been trying to use xc3sprog on FreeBSD 7.2 RELEASE to detect my
Digilent Spartan 3 Starter Board by running the command

xc3sprog -j -d /dev/ppi0

but get the failure message

Release $Rev: 215 $
Please provide feedback on success/failure/enhancement requests! Check
Sourceforge SVN!
Missing power for Parallel Cable III

I'm using the Xilinx parallel JTAG cable to connect the board.

To compile xc3sprog I had to change 'port->fd' to 'fd' in a few places in
ioparport.cpp - don't know if that might be causing this.

Thought this might be an issue with the port not being detected by the
kernel but dmesg shows that the port is indeed detected:

ppc0: <Parallel port> at port 0x378-0x37f irq 7 on isa0
ppc0: SMC-like chipset (ECP/EPP/PS2/NIBBLE) in COMPATIBLE mode
ppc0: FIFO with 16/16/9 bytes threshold
ppbus0: <Parallel port bus> on ppc0
ppbus0: [ITHREAD]
plip0: <PLIP network interface> on ppbus0
plip0: WARNING: using obsoleted IFF_NEEDSGIANT flag
lpt0: <Printer> on ppbus0
lpt0: Interrupt-driven port
ppi0: <Parallel I/O> on ppbus0
ppc0: [GIANT-LOCKED]
ppc0: [ITHREAD]

I'm running the GENERIC kernel.

Thanks,
JP



Article: 143069
Subject: Re: 82S153 Fuse Map / Disassembler
From: mike_la_jolla <mdini@dinigroup.com>
Date: Fri, 18 Sep 2009 09:07:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 17, 3:10=A0am, buc...@atbode100.lrr.in.tum.de (Rainer Buchty)
wrote:
> Hi everyone,
>
> does anyone on this list have a pointer to a (freely available) JEDEC
> file disassembler that also supports N82S153 (PLS153) or at least a
> document showing which bit in the JEDEC file maps to what fuse in the
> PLS153?
>
> Unfortunately, also the N82S153 datasheet on alldatasheets.com doesn't
> really help (unless someone could confirm that the order of bits in the
> explained TWX format is the same order as in the JEDEC fusemap).
>
> Regards,
> =A0 =A0 =A0 =A0 Rainer

Not sure why you are using JEDEC for this.  If you have the 82S153,
just put
the device on the programmer and read the fuse locations back.  I did
this
many times 25 years ago.   What device programmer are you using?


Article: 143070
Subject: Re: FPGA for acoustic adaptive beamforming
From: "MK" <mk@nospam.please>
Date: Fri, 18 Sep 2009 17:11:59 +0100
Links: << >>  << T >>  << A >>

"DOD" <domenicodonisi@libero.it> wrote in message 
news:f2edb08f-7467-4e41-8843-6ff3d9567b8e@j9g2000vbp.googlegroups.com...
> Hi,
>
> i'm not an expert user of FPGA but i need to solve a problem before
> starting to work on it.
> I have to choose an FPGA to implement an acoustic beam forming. My
> system has 512 input channels (microphones). After A/D conversion at
> 48 KHz with 24 bit per sample i need to have all the 512 signals
> syncronysed to perform the beamforming. So far i have read that Xilinx
> tools and FPGA (Spartan or Virtex) should fix my problem but i have
> difficulties in choosing the right model.
> From a SW point of view I'd like to implement my model on Simulik,
> translate it into VHDL and then put the code into FPGA. DO you think
> that Xilinx products could solve my problem and which model do you
> suggest to buy?
> The FPGA + SW at about what price is sold? Please any suggestion could
> be very useful for me. Thanks in advance for your help.


You are picking a pretty big job for your first FPGA - what's wrong with 
traffic lights like everyone else ?

Seriously, you may be confusing developing with an FPGA with writing code 
for a processor.  Although Xilinx and the Mathworks offer a Simulink to FPGA 
path don't expect it to be easy or do all the work for you.
You can (should) get the software before you buy any hardware and work out 
how much FPGA the design will need. You can start with some fairly cheap 
tools from Xilinx (check on their website) but in the end you will need 
MATLAB, SIMULINK and other licenses from the Mathworks (expect about $10k 
last time I looked).

Michael Kellett



Article: 143071
Subject: Re: To Xilinx: Regarding the download manager
From: Sean Durkin <news_MONTH@tuxroot.de>
Date: Fri, 18 Sep 2009 18:36:10 +0200
Links: << >>  << T >>  << A >>
Michael Schwingen wrote:
> No crashes, but first entitlenow did not like my existing account (which had
> all information entered, and worked fine for the previous downloads). It
> sent me back to Xilinx to fill in "missing information" without specifying
> what was wrong. I filled *all* fields - still no luck.

I had the same problem. In my case it was the fact that I didn't fill in
the "state" field properly. You can't leave the field empty or put in
"none", and "Bayern" doesn't work, either, and of course the
drop-down-list doesn't include any even remotely fitting options.

I contacted Xilinx support and they then put in "N/A" manually, which
does now work...

cu,
Sean

Article: 143072
Subject: Spartan-6 - Drigmorn3 Board Picture
From: John Adair <g1@enterpoint.co.uk>
Date: Fri, 18 Sep 2009 09:40:14 -0700 (PDT)
Links: << >>  << T >>  << A >>
Drigmorn3 webpage now has a photo for the curious
http://www.enterpoint.co.uk/component_replacements/drigmorn3.html.

We will be showing this board working at ESC in Boston next week for
anyone coming along there. We running a raffle for one first batch of
boards at ESC and continued on our website (assuming we get the form
sorted out on our website in time).

John Adair
Enterpoint Ltd.

Article: 143073
Subject: Re: FPGA for acoustic adaptive beamforming
From: phil hays <philhays@dont.spam>
Date: Fri, 18 Sep 2009 18:26:49 GMT
Links: << >>  << T >>  << A >>
DOD wrote:

> Hi,
> 
> i'm not an expert user of FPGA but i need to solve a problem before
> starting to work on it.
> I have to choose an FPGA to implement an acoustic beam forming. My
> system has 512 input channels (microphones). After A/D conversion at 48
> KHz with 24 bit per sample i need to have all the 512 signals
> syncronysed to perform the beamforming. So far i have read that Xilinx
> tools and FPGA (Spartan or Virtex) should fix my problem but i have
> difficulties in choosing the right model. From a SW point of view I'd
> like to implement my model on Simulik, translate it into VHDL and then
> put the code into FPGA. DO you think that Xilinx products could solve my
> problem and which model do you suggest to buy?
> The FPGA + SW at about what price is sold? Please any suggestion could
> be very useful for me. Thanks in advance for your help.

Yes, this sort of problem can be solved in an FPGA, and Xilinx has 
software to translate from a Simulink model into VHDL. I've used it, it 
works.

List price for the software "DSP Edition" is about USD $4000 for a node 
locked license. Of course MatLab is also required, which will cost about 
twice as much or more depending on options selected. If your application 
is for University, sizable discounts are available for both software 
packages.

The size FPGA required is very hard to estimate, as there are a lot of 
details needed.

It would make sense to spend a lot of time developing the design before 
choosing a part to get a good idea of the minimum cost FPGA than can do 
all the required functions.

What are the requirements? There are a lot of different application 
requirements under the general category of beamforming. Some would fit in 
the larger Spartan parts. Some would require more resources. Some could 
be done in software only, or some combination of hardware processing and 
software processing. Frequency or time domain? Adaptive, prefiltering, 
noise reduction or echo cancellation per channel? Number of beams? Focus? 
Shape of array? All can change the amount and type of resources required.


-- 
Phil Hays
(phil_hays at eeei.gro (fix the order for email)

Article: 143074
Subject: Re: FPGA for acoustic adaptive beamforming
From: "Marco" <null@null.net>
Date: Fri, 18 Sep 2009 11:40:44 -0700
Links: << >>  << T >>  << A >>
What is the algorithm you need to perform on the 512 samples every 20 micro 
seconds.  Do you just need to move their zero crossing's of the inputs to 
some common time at the output, or is there more involved.

What accuracy do you need in time and amplitude for your output?

What type of latency do you need between a given input and the corresponding 
effect on its output?

-- 
Marco
UCO Lick Observatory
Laboratory for Adaptive Optics

"DOD" <domenicodonisi@libero.it> wrote in message 
news:f2edb08f-7467-4e41-8843-6ff3d9567b8e@j9g2000vbp.googlegroups.com...
> Hi,
>
> i'm not an expert user of FPGA but i need to solve a problem before
> starting to work on it.
> I have to choose an FPGA to implement an acoustic beam forming. My
> system has 512 input channels (microphones). After A/D conversion at
> 48 KHz with 24 bit per sample i need to have all the 512 signals
> syncronysed to perform the beamforming. So far i have read that Xilinx
> tools and FPGA (Spartan or Virtex) should fix my problem but i have
> difficulties in choosing the right model.
> From a SW point of view I'd like to implement my model on Simulik,
> translate it into VHDL and then put the code into FPGA. DO you think
> that Xilinx products could solve my problem and which model do you
> suggest to buy?
> The FPGA + SW at about what price is sold? Please any suggestion could
> be very useful for me. Thanks in advance for your help. 





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