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theom <theobjectmachine@gmail.com> wrote: ... > xc3sprog -j -d /dev/ppi0 > but get the failure message > Release $Rev: 215 $ > Please provide feedback on success/failure/enhancement requests! Check > Sourceforge SVN! > Missing power for Parallel Cable III > I'm using the Xilinx parallel JTAG cable to connect the board. > To compile xc3sprog I had to change 'port->fd' to 'fd' in a few places in > ioparport.cpp - don't know if that might be causing this. Could you please try sourceforge SVN http://sourceforge.net/projects/xc3sprog/develop svn co https://xc3sprog.svn.sourceforge.net/svnroot/xc3sprog xc3sprog ? Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143101
theom <theobjectmachine@gmail.com> wrote: ... > xc3sprog -j -d /dev/ppi0 > but get the failure message > Release $Rev: 215 $ > Please provide feedback on success/failure/enhancement requests! Check > Sourceforge SVN! > Missing power for Parallel Cable III > I'm using the Xilinx parallel JTAG cable to connect the board. > To compile xc3sprog I had to change 'port->fd' to 'fd' in a few places in > ioparport.cpp - don't know if that might be causing this. Could you please try sourceforge SVN http://sourceforge.net/projects/xc3sprog/develop svn co https://xc3sprog.svn.sourceforge.net/svnroot/xc3sprog xc3sprog ? Regarding the parallel port, I fixed port->fd and some error inhibiting the use with win32 introduced sometimes after $Rev: 215 If the problem persists and if you can, try running in gdb to see what goes wrong. Otherwise send me the output of "strace -f -o /tmp xc3sprog.strace xc3sprog -j -d /dev/ppi0" or something equivalent on BSD. Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143102
On Sep 15, 8:38 am, Rob Gaddi <rga...@technologyhighland.com> wrote: > On Tue, 15 Sep 2009 04:05:47 -0500 > > "maxascent" <maxasc...@yahoo.co.uk> wrote: > > I agree totally with the op. I have had so many problems downloading > > ISE 11.2 that I have just given up. Every time I try and resume after > > stopping I just get error and have to strt all over again. Why cant > > Xilinx just give us the option to download the file using our own > > download manger. After all if I have the capability to design with > > their FPGA then surely I can work out how to download a zip file. > > > Jon > > > --------------------------------------- > > This message was sent using the comp.arch.fpga web interface on > >http://www.FPGARelated.com > > Me too. Took me 4 tries to download ISE 11.2 using Windows XP, the > first three times I got an hour and change into the download and then > it hung up and wouldn't restart. The fourth time it still hung up, but > when I force quit the downloader, then started to try for the FIFTH > time, it picked up where it left off. > > Back in my day we had FTP servers that supported resuming in the middle > of the file, and goshdarnit we liked it that way. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order I agree. What's wrong with FTP? It has all the features needed, it's documented, and it works. Why go and invent something that's worse? Proof that the education system is failing...Article: 143103
>On Thu, 17 Sep 2009 19:57:49 -0500 >"mlin" <maddie.gun@gmail.com> wrote: > >> Hi, >> >> I am using MIG v2.1 that targets spartan 3 starter kit. I want to >> know, if sram on the starter board could be accessed using MIG and if >> the MIG is used for accessing memory development boards? >> >> Thanks in advance! >> >> > >MIG is for talking to DRAMs, which are complicated. SRAM is >easy: there are data lines and address lines and it just does what you >ask it to. The interface is trivial enough to implement that I'd be >surprised if anyone has a core to do it; it would mostly just be wires. > >-- >Rob Gaddi, Highland Technology >Email address is currently out of order > Thank you so much. Could you please clear my other doubt? How do I send address and data to the SRAM? Thanks. --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143104
>On Sep 17, 8:28=A0am, "Niieg" <stefan.na...@kit.edu> wrote: >> Hi everybody, >> is it possible to generate all the names with an other name than that of >> the top level entity in Alteras Quartus? >> >> I want it like this: >> project: my_choice.qpf >> top level entity: my_top.v >> generated files: my_choice.rbf, my_choice.fit.rpt, my_choice.flow.rpt, >> my_choice.pin, ... etc >> >> Quartus does this: >> project: my_choice.qpf >> top level entity: my_top.v >> generated files: my_top.rbf, my_top.fit.rpt, my_top.flow.rpt, my_top.pin, >> ... etc >> >> Kind regards and thank you =A0 =A0 =A0 =A0 >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> This message was sent using the comp.arch.fpga web interface onhttp://www= >.FPGARelated.com > >Niieg, > >What matters to Quartus (in terms of naming output file names) is not >the project name (.QPF file) or the top level entity name (.V/.VHD >file), but the revision name (.QSF file). If you have a my_top.qsf, >Quartus will generate a my_top.fit.rpt, but if you had a >my_choice.qsf, it will generate a my_choice.fit.rpt. You can choose a >different revision name when creating a project (at least using the >New Project Wizard), or you can create/change a revision from the >revision dialog box. Note that if the top level file is not equal to >the revision file name, then you will be required to specify what >source files you want Quartus to read, and what the top level entity >is. You can do this from the "Add Files to Project" dialog. After >doing that, you will see the following assignments in the QSF: > >set_global_assignment -name TOP_LEVEL_ENTITY "|my_top" >set_global_assignment -name VERILOG_FILE my_top.v > >In other words, if you don't specify anything, then Quartus will >assume that your project name =3D=3D revision name =3D=3D top level source >file =3D=3D top level entity name, but you can change it all. > >- David Karchmer > Altera > Hi David, thanks a lot for that post. It helped me a lot. Kind regards Stefan PS Thank you, Andy and Petter, too for your posts --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143105
Why dont you just read the data sheet on the device? Generally you just set the address and data you want and then set the write enable (all synchronous with the clock). Nothing more to it really Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143106
Hi, when starting a netlist simulation (vho) with timing file (sdf) what is the saving in simulation time when simulating a small 8bit counter a) on a netlist which represents an CPLD being 90% filled b) on a netlist which represents an CPLD being 3% filled Does the simulation take the same simulation duration (real time) ? I mean the vho file has to be compiled anyway. Rgds, HssigArticle: 143107
hssig <hssig@gmx.net> wrote: < when starting a netlist simulation (vho) with timing file (sdf) what < is the < saving in simulation time when simulating a small 8bit counter < a) on a netlist which represents an CPLD being 90% filled < b) on a netlist which represents an CPLD being 3% filled < Does the simulation take the same simulation duration (real time) ? I < mean the vho file has to be compiled anyway. Place and Route takes a lot longer for 90% full. I would expect the simulation time not to change much, though maybe a little bit. With the usual event driven simulation, there might be some glitches that propagate through the logic as the signals change, and those might affect the timing in different ways. For synchronous logic, the signals are expected to settle to the final value before the next clock, but the time needed for simulation could be different. -- glenArticle: 143108
Hi Glen, thank you for your answer. The 8bit counter "coexists" with the rest of the design, that means there is no dependency. Does it have an influence on the simulation duration if the a) the "rest" of the design is not activated in simulation b) the "rest" of the design is frequently toggling ? What exactly leads to a slowdown in gate-level simulation ? Are the events on the gates the time consuming factor ? Rgds, HssigArticle: 143109
hssig wrote:
> Does the simulation take the same simulation duration (real time) ? I
> mean the vho file has to be compiled anyway.
And recompiled every time I make the slightest change.
If I were testing a synchronous counter, I would
sim the .vhd file directly.
I would only make a .vho if I were testing Quartus.
-- Mike Treseler
Article: 143110Hi Mike, yes, I know. But I am trying to understand under which circumstances a gate-level simulation gets slow and whether it makes a difference how many gates are simulated. Rgds, HssigArticle: 143111
hssig wrote:
> yes, I know. But I am trying to understand under which circumstances a
> gate-level simulation gets slow
> and whether it makes a difference how many gates are simulated.
A .vho netlist is composed of altera primitives like luts and flops,
not gates, so I'm not sure what the question means.
I have never made an exact measurement of netlist sims, but I would
guess that they average ten times slower than code.
-- Mike Treseler
Article: 143112On Mon, 21 Sep 2009 14:17:20 -0700 (PDT), hssig <hssig@gmx.net> wrote: >Hi Mike, > > >yes, I know. But I am trying to understand under which circumstances a >gate-level simulation gets slow Back-annotated gate-level simulations are much slower than simple behavioral gate-level simulations. If you are using gate level sims as a replacement for formal verification, this might make sense for you. Check out +nospecify option in your simulator. >and whether it makes a difference how many gates are simulated. All event based simulators become slower as the number of events go up. More gates usually mean more events so larger designs usually simulate more slowly whether they're RTL or gate-level sims. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 143113
On Mon, 21 Sep 2009 14:17:20 -0700 (PDT), hssig wrote: >...I am trying to understand under which circumstances a >gate-level simulation gets slow Almost all circumstances :-) As you speculated in another post, it's all the events on all those single-bit signals that makes everything so slow. A gate-level simulation is a very large number of parallel processes (gate descriptions), each of which does very little work; it's the communication between them (triggering of activity because of signal transitions) that costs the simulator so much work. >and whether it makes a difference how many gates are simulated. Of course it does! The processing of signal events dominates the computation. The number of events per simulated clock cycle will scale (very roughly) linearly with the number of gates. More gates -> slower. Adding timing backannotation with an SDF file will add another performance hit, because each signal event then gives rise to a bunch more work computing delays, timing checks and so forth. Of course, simulator vendors work hard to optimize all this stuff for performance. But it's still waaaaaay slow by comparison with RTL simulation, in which there are many fewer events and each event does much more work (more complex computations in each process). Go to a very abstract transaction-level model of your system and you should expect to see yet another couple of orders of magnitude of speedup, hence the trend towards C++ or SystemC modelling of large systems at early stages in the design cycle. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 143114
On Mon, 21 Sep 2009 14:44:03 -0700, Mike Treseler <mtreseler@gmail.com> wrote: >hssig wrote: > >> yes, I know. But I am trying to understand under which circumstances a >> gate-level simulation gets slow >> and whether it makes a difference how many gates are simulated. > >A .vho netlist is composed of altera primitives like luts and flops, >not gates, so I'm not sure what the question means. An ASIC gate level netlist is composed of the primitives in the standard cell library like complex functions (AOI221 etc. ) and flops which is not all that different from the LUT and flops in an fpga gate level netlist. It's definitely possible to write a specialized definition for every initialization of a LUT to convert it from a LUT based netlist to a "gate" based netlist. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 143115
On Sep 20, 4:31=A0pm, LittleAlex <alex.lo...@email.com> wrote: > On Sep 15, 8:38 am, Rob Gaddi <rga...@technologyhighland.com> wrote: > > > > > On Tue, 15 Sep 2009 04:05:47 -0500 > > > "maxascent" <maxasc...@yahoo.co.uk> wrote: > > > I agree totally with the op. I have had so many problems downloading > > > ISE 11.2 that I have just given up. Every time I try and resume after > > > stopping I just get error and have to strt all over again. Why cant > > > Xilinx just give us the option to download the file using our own > > > download manger. After all if I have the capability to design with > > > their FPGA then surely I can work out how to download a zip file. > > > > Jon > > > > --------------------------------------- > > > This message was sent using the comp.arch.fpga web interface on > > >http://www.FPGARelated.com > > > Me too. =A0Took me 4 tries to download ISE 11.2 using Windows XP, the > > first three times I got an hour and change into the download and then > > it hung up and wouldn't restart. =A0The fourth time it still hung up, b= ut > > when I force quit the downloader, then started to try for the FIFTH > > time, it picked up where it left off. > > > Back in my day we had FTP servers that supported resuming in the middle > > of the file, and goshdarnit we liked it that way. > > > -- > > Rob Gaddi, Highland Technology > > Email address is currently out of order > > I agree. =A0What's wrong with FTP? =A0It has all the features needed, it'= s > documented, and it works. > > Why go and invent something that's worse? =A0Proof that the education > system is failing... Devil's Advocate: Xilinx wants to track every download, to make sure that they know who's getting it. I can't speculate on the reasons for this but it probably has to do with their licensing. Anonymous ftp is just that -- anonymous -- and the only thing possibly linking a download to a person is an IP address in the server logs. -aArticle: 143116
Andy Peters wrote: > Anonymous ftp is just that -- anonymous -- and the only thing possibly > linking a download to a person is an IP address in the server logs. What about then requiring a username/password, like some other CAD companies do? FTP doesn't have to be anonymous, after all. -- Phil Hays (phil_hays at eeei.gro (fix the order for email)Article: 143117
Hi Jonathan, thank you for explaining, it becomes clear now. Rgds, HssigArticle: 143118
signal next : integer range -1 to 2;
function find_first(vector, enable : std_ulogic_vector(0 to 2))
return integer is
variable result : integer;
begin
result := -1;
-- omitted calc of first in range of 0..2
return result;
end find_first;
next <= find_first(valid, enable);
-------
is this code fully synthesis safe?
how many bits is variable next?
this is not my code, i need to troubleshoot it,
i guess it is 100% legal code, just curious how are
synthesis tools doing it
next could be 2 bits, but then -1 would map to 0 ?
or ?
Antti
Article: 143119i am just a new user of modelsim and debussy, can anyone help me transfer my code to modelsim and debussy from quartus? i have a code in verilog using quartus..but due to long simulation time i can't view all the output..so i switched to modelsim..however, i cant view the memory contents in modelsim.. how can i double check the contents of my memory in modelsim?Article: 143120
Antti <antti.lukats@googlemail.com> wrote: < signal next : integer range -1 to 2; < function find_first(vector, enable : std_ulogic_vector(0 to 2)) < return integer is < variable result : integer; < begin < result := -1; < -- omitted calc of first in range of 0..2 < return result; < end find_first; < next <= find_first(valid, enable); < is this code fully synthesis safe? < how many bits is variable next? I have done priority encoders in verilog before, though always specifying the width of the result. < this is not my code, i need to troubleshoot it, < i guess it is 100% legal code, just curious how are < synthesis tools doing it I believe it is fine. In verilog, the result would be 32 bits (on the usual implementation). If you assign the result to a something smaller, it will truncate. Also, the tools are pretty good at removing unused logic. Still, I don't see any reason not to specify the size of the result. < next could be 2 bits, but then -1 would map to 0 ? < or ? 3 (the low two bits of twos complement -1) -- glenArticle: 143121
On Sep 22, 2:53=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Antti <antti.luk...@googlemail.com> wrote: > > < =A0signal next =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: integer range -1 to 2; > > < =A0function find_first(vector, enable : std_ulogic_vector(0 to 2)) > < =A0 =A0return integer is > < =A0 =A0variable result : integer; > < =A0begin > < =A0 =A0result :=3D -1; > < =A0 =A0 -- omitted calc of first in range of 0..2 > < =A0 =A0return result; > < =A0end find_first; > > < =A0next <=3D find_first(valid, enable); > > < is this code fully synthesis safe? > < how many bits is variable next? > > I have done priority encoders in verilog before, though > always specifying the width of the result. > > < this is not my code, i need to troubleshoot it, > < i guess it is 100% legal code, just curious how are > < synthesis tools doing it > > I believe it is fine. =A0In verilog, the result would be 32 bits > (on the usual implementation). =A0If you assign the result to a > something smaller, it will truncate. =A0Also, the tools are pretty > good at removing unused logic. =A0Still, I don't see any reason > not to specify the size of the result. > > < next could be 2 bits, but then -1 would map to 0 ? > < or ? > > 3 =A0(the low two bits of twos complement -1) > > -- glen yeah i assumed 3 but it could be 2 if doing hand coded functionally same code AnttiArticle: 143122
On Sep 22, 7:18=A0am, Antti <antti.luk...@googlemail.com> wrote: > =A0 signal next =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: integer range -1 to 2; > > =A0 function find_first(vector, enable : std_ulogic_vector(0 to 2)) > =A0 =A0 return integer is > =A0 =A0 variable result : integer; > =A0 begin > =A0 =A0 result :=3D -1; > =A0 =A0 =A0-- omitted calc of first in range of 0..2 > =A0 =A0 return result; > =A0 end find_first; > > =A0 next <=3D find_first(valid, enable); > > ------- > is this code fully synthesis safe? It looks to be. > how many bits is variable next? > To know that you would need to look at the declaration for 'next' not the function that assigns to 'next'. The defined range for the integer will end up defining the number of bits required for synthesis. Whether it can be implemented in less bits would depend on whether or not the logic reduces to something smaller. For example, the code you listed 'as is' would reduce to a constant and therefore most likely result in 0 bits for 'next'. signal next: integer; -- 32 bits signal next: integer range 0 to 7; -- 3 bits signal next: integer range -3 to 3; -- 3 bits signal next: integer range -4 to 3; -- 3 bits also > > next could be 2 bits, but then -1 would map to 0 ? > or ? -1 in two bits is "11" Kevin JenningsArticle: 143123
On Sep 22, 7:18=A0am, Antti <antti.luk...@googlemail.com> wrote: > =A0 signal next =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: integer range -1 to 2; > I missed this line in my first post. So for starters, 'next' would have to be 3 bits based on the defined range. As I mentioned in the previous post, depending on what the logic actually is, some of the bits could be optomized away during synthesis. If there is a two bit (or one bit) implementation, synthesis tools will most likely find it. Reduction of simple boolean logic as in this case is their strong suit. Kevin JenningsArticle: 143124
Hello all
I am facing a problem with XST (ISE Webpack 11.1 actually) that
doesn't give proper results with a counter.
I copied the working code at the end of this message. If I define
variable v_bcnt as unsigned(5 downto 0) then the design stops working.
I haven't dug into the problem but SPI communication doesn't work
anymore.
You may wonder why I want to add a bit to a counter that counts from
31 down to 0. It's because I want it to count from a higher (and
programmable) value. I traced the problem I had down to this vector
length problem.
I know I should probably submit a testcase but I don't have much time
at the moment. Any help around this problem is welcome.
Thanks
Nicolas
-------------------------------------------------------------------------------
-- Title : SPI master interface
-- Project :
-------------------------------------------------------------------------------
-- File : spi_master.vhd
-- Author : <nicolas.matringe@itron.com>
-- Company : Itron SAS
-- Created : 2009-06-10 11:43
-- Last update: 2009-09-22 16:07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2009 Itron SAS
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-06-10 11:43 1.0 nmatring Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
port (
sck : out std_logic;
miso : in std_logic;
mosi : out std_logic;
cs_n : out std_logic;
td : in std_logic_vector(31 downto 0);
rd : out std_logic_vector(31 downto 0);
rq : in std_logic;
rdy : out std_logic;
clk : in std_logic;
rst : in std_logic);
end entity spi_master;
architecture rtl of spi_master is
constant C_CS_SU : natural := 10;
constant C_CK_HALFPER : natural := 2;
constant C_CS_HD : natural := 10;
begin -- architecture rtl
process (clk, rst) is
type t_spi_state is (idle, cs_su, transmit, cs_hd);
variable v_spi_crt : t_spi_state;
variable v_cntr : natural range 0 to 10;
variable v_bcnt : unsigned(4 downto 0);
variable v_toggle : std_logic;
variable v_sr : std_logic_vector(31 downto 0);
variable v_miso : std_logic;
begin -- process
if rst = '1' then -- asynchronous reset (active
high)
sck <= '1';
cs_n <= '1';
mosi <= '1';
rd <= (others => '0');
rdy <= '1';
v_spi_crt := idle;
v_cntr := 0;
v_bcnt := (others => '0');
v_toggle := '0';
v_miso := '1';
elsif rising_edge(clk) then -- rising clock edge
case v_spi_crt is
when idle =>
v_toggle := '0';
cs_n <= '1';
if rq = '1' then
rdy <= '0';
cs_n <= '0';
v_sr := td;
v_cntr := C_CS_SU;
v_spi_crt := cs_su;
end if;
when cs_su =>
if v_cntr = 0 then
sck <= v_toggle;
v_toggle := '1';
mosi <= v_sr(31);
v_bcnt := to_unsigned(31, v_bcnt'length);
v_cntr := C_CK_HALFPER;
v_spi_crt := transmit;
else
v_cntr := v_cntr - 1;
end if;
when transmit =>
if v_cntr = 0 then
v_cntr := C_CK_HALFPER;
if v_toggle = '0' then
mosi <= v_sr(31);
-- v_sr := v_sr(v_sr'left-1 downto 0) & miso;
v_bcnt := v_bcnt - 1;
else
v_sr := v_sr(v_sr'left-1 downto 0) & v_miso;
-- mosi <= v_sr(31);
if v_bcnt = 0 then
v_spi_crt := cs_hd;
v_cntr := C_CS_HD;
end if;
end if;
sck <= v_toggle;
v_toggle := not v_toggle;
else
v_cntr := v_cntr - 1;
end if;
when cs_hd =>
if v_cntr = 0 then
rd <= v_sr;
v_spi_crt := idle;
rdy <= '1';
else
v_cntr := v_cntr - 1;
end if;
when others => null;
end case;
v_miso := miso;
end if;
end process;
end architecture rtl;
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