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skyworld wrote: > thanks for your reply. To my understanding, syn_keep is used to keep > wire signals and syn_preserve is used to keep sequential signals. The > signals I want to keep is generated in process(clk, reset) Synthesis works from a device input pin to an output pin. If my process(clk, reset) does not look at an input pin *and* drive an output pin in the top entity, I get no gates and no flops, in any case. -- Mike TreselerArticle: 143826
On 10=D4=C228=C8=D5, =C9=CF=CE=E711=CA=B148=B7=D6, Mike Treseler <mtrese...= @gmail.com> wrote: > skyworld wrote: > > thanks for your reply. To my understanding, syn_keep is used to keep > > wire signals and syn_preserve is used to keep sequential signals. The > > signals I want to keep is generated in process(clk, reset) > > Synthesis works from a device input pin to an output pin. > If my process(clk, reset) does not look at an input pin > *and* drive an output pin in the top entity, > I get no gates and no flops, in any case. > > -- Mike Treseler Hi, does this mean I don't have a way to monitor these signals? thanks. regards skyworldArticle: 143827
I had a similar problem with chipscope cores. Try using the syn_noprune attribute which is an integer with a value of 1. This worked for me where syn-keep failed. ---Matthew Hicks > On 10月27日, 下午7时43分, skyworld <chenyong20...@gmail.com> wrote: > >> Hi, >> >> I inserted some circuit in source code for debug. These code aren't >> ported as output and is monitored by chipscope. In order not to be >> optimised by synplify, I use attribute syn_preserve to keep these >> registers. But synplify still removed these signals, I can't insert >> these signals into cdc file in ISE. Is there a way to keep these >> signals so that it can be used in chipscope? >> >> for example, >> > signal a : std_logic; > signal b : std_logic; > attribute syn_preserve : boolean; > attribute syn_preserve of a : signal is true; > attribute syn_preserve of b: signal is true; > process(clk, reset) > begin > a <= ... > b <= ... > end > signal a/b are internal signals and not sent to output port. how can I > keep these signals? thanks. >Article: 143828
kclo4 wrote: > do they do not teach politeness in school anymore those days?? no > please, no care for syntax, only "do my homework quickly and i do not > want to search by myself"... A sign of the times, unfortunately. And usually, it's "...and don't waste my time trying to teach me _how_ to do it - I'm not at all interested. Just tell me where to find a pre-packaged, working solution! Now!" Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 143829
Hi jmariano, I have implemented a similar FPGA-based pulse programmer system for my master's thesis, but instead of a Microblaze, I ended up designing a custom processor and instruction set architecture just for outputting pulses, detecting input pulses, looping, executing subroutines, and branching conditionally. The problem with using a general-purpose processor is that precise timing of the output cannot be guaranteed, so I assume you are just using the Microblaze to load your banks of SRAM before letting the timer run and stream the pulses directly from memory. There appear to be several Microblaze modules available on http://www.opencores.org, maybe you can adapt some of them to your needs. All of my project's design documents are released as open source on SourceForge. Perhaps the VHDL source code will give you some ideas, although the board I used is a custom design (also released on the website). http://pulse-sequencer.svn.sourceforge.net/viewvc/pulse-sequencer/firmware/= sequencer-vhdl/ I assume you are designing this pulse programmer for scientific applications, and if so, I would like to hear about it by personal e- mail. Good luck, Paul On Oct 6, 8:42=A0am, jmariano <jmarian...@gmail.com> wrote: > Dear Group, > > I have very little experience in FPGA (and in digital design!). > > As part of a research project I have to add to an existing microblaze > system, implemented on spartan 3 starter kit board, apulseprogrammer > (PP). A PP is a system that outputs a given pattern to a set of > digital lines for a given time and then changes the pattern according > to a program. > There are several ways of implementing the PP but I have decided to > use what seams to me to be the simpler on: two blocks of RAM, say 2K > deep and 16 bits wide, pointed by the same address counter. One block > holds the time duration and the other the bit pattern. The control > block load's the contents of the first ram into a counter and latches > the content of the second one to the output. When the counter reaches > the end, the AC in incremented and the next time and pattern words are > loaded. > > The IP access to RAM must be fast (this determines the time resolution > of the PP), but the access of the processor can be slow, since this is > done only once at the beginning of the experiment to write the > programming words and then the IP works by is one. > > I was thinking on using BRAM to hold the data. Is this a good choice? > My other question is, what is the easiest way to implement microblaze > access the ram? I appreciate any commets on this. > > I also appreciate if you could point me to somme examples or > application notes of a similar system (not a PP, but a system were > memory is accessed by an IP and microblaze), were I can get somme > ideas. > > Tank you very much, > > jmarianoArticle: 143830
On 10=E6=9C=8828=E6=97=A5, =E4=B8=8B=E5=8D=8812=E6=97=B650=E5=88=86, Matthe= w Hicks <mdhic...@uiuc.edu> wrote: > I had a similar problem with chipscope cores. =C2=A0Try using the syn_nop= rune > attribute which is an integer with a value of 1. =C2=A0This worked for me= where > syn-keep failed. > > ---Matthew Hicks > > > > > On 10=E6=9C=8827=E6=97=A5, =E4=B8=8B=E5=8D=887=E6=97=B643=E5=88=86, sky= world <chenyong20...@gmail.com> wrote: > > >> Hi, > > >> I inserted some circuit in source code for debug. These code aren't > >> ported as output and is monitored by chipscope. In order not to be > >> optimised by synplify, I use attribute syn_preserve to keep these > >> registers. But synplify still removed these signals, I can't insert > >> these signals into cdc file in ISE. Is there a way to keep these > >> signals so that it can be used in chipscope? > > >> for example, > > > signal a : std_logic; > > signal b : std_logic; > > attribute syn_preserve : boolean; > > attribute syn_preserve of a : signal is true; > > attribute syn_preserve of b: signal is true; > > process(clk, reset) > > begin > > a <=3D ... > > b <=3D ... > > end > > signal a/b are internal signals and not sent to output port. how can I > > keep these signals? thanks.- =E9=9A=90=E8=97=8F=E8=A2=AB=E5=BC=95=E7=94= =A8=E6=96=87=E5=AD=97 - > > - =E6=98=BE=E7=A4=BA=E5=BC=95=E7=94=A8=E7=9A=84=E6=96=87=E5=AD=97 - In fact I have tried this. First I tried to use syn_noprune to keep these signals, but synplify reports this is an error usage for syn_noprune. At last I found the solution: I use core generator to generate icon and ila, I connect these signals to ila and use syn_noprune to keep ila and icon. In this way I can observe those signals in chipscope. But this is a complicated one because VHDL doesn't like verilog, you can infer signals from different levels, such as level1.level2.signal_a, I have to connect signals from different module to the correct module which I put the ila and icon. So do anybody has a good way to use those attributes to keep these signals? thanks.Article: 143831
On Tue, 27 Oct 2009 18:28:11 -0700, skyworld wrote: > On 10月27日, 下午9时31分, General Schvantzkoph <schvantzk...@yahoo.com> wrote: >> On Tue, 27 Oct 2009 04:43:25 -0700, skyworld wrote: >> > Hi, >> >> > I inserted some circuit in source code for debug. These code aren't >> > ported as output and is monitored by chipscope. In order not to be >> > optimised by synplify, I use attribute syn_preserve to keep these >> > registers. But synplify still removed these signals, I can't insert >> > these signals into cdc file in ISE. Is there a way to keep these >> > signals so that it can be used in chipscope? >> >> > for example, >> >> Rather then rely on syn_preserve I generally use a spare pin and then >> OR all the signals that I want to protect together and connect the OR >> to the pin. > > Hi, > > thanks for your reply. This is a big design and I don't have an option > to connect debug signals to a pin. That is the reason why I use > chipscope and use those annoying attributes. Another technique that I've used is to add a bit to a status register that accessed from a control/status register bus. Anything that would have no effect on the actual operation of the design but fools the synthesis tool into thinking that the registers are necessary will do the trick.Article: 143832
I have a design with some level of hierarchy and I want to connect a chipscope ILA core to the bottom level. For example say I have 3 modules A, B and C with a signal temp in C. Module A is the top level with B inside A and C inside B. I would of thought that I could just do the following chipscope_ila U_ila( .CLK (clk), .CONTROL (control), .TRIG0 (A.B.C.temp)); The ila is in the top level and I want to monitor temp. When I try and synthesize it with Synplify the program just errors. Can anyone tell me what I am ddoing wrong? Thanks Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143833
On Oct 27, 4:50=A0am, Antti <antti.luk...@googlemail.com> wrote: > On Oct 27, 10:45=A0am, Matthieu Michon > > > > <matthieu.d.u.m.m.y.mic...@gmail.com> wrote: > > On Mon, 26 Oct 2009 12:43:12 -0700 (PDT) > > > Mawa_fugo <cco...@netscape.net> wrote: > > > On Oct 24, 11:51=A0am, kevin93 <ke...@whitedigs.com> wrote: > > > > On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > > > > I have SP3 installed in the 10.1 - =A0but sometimes - once a whil= e, the > > > > > entire project just corrupted - when "rerun all" it TOOK the topm= odule > > > > > source from "nowhere" - nomatter how you change your topmodule it > > > > > still lock the topmodule source fom that mystery source > > > > > > Oh my goodness > > > > > The "Cleanup Project Files" under the "Project" menu can solve many= of > > > > these problems. > > > > > kevin > > > > Thanks for suggestion - it does something difference when I tried to > > > clean the project but it still lock the source from "nowhere" > > > Hi > > > I also had to deal with the same kind of issue with ISE 10.1SP3: after = checking out a project stored on a version control system (SVN), the top-le= vel mark disappeared and the "Set as Top Module" action was disabled. =A0Ne= edless to say that I tried all the usuals (amongst other things: "Cleanup P= roject Files", "Check Syntax", removing/adding again the top-level source f= ile) without much success. > > > After a few minutes fiddling around, I tried to change the "Top-Level S= ource Type" project property from HDL to EDIF and back to HDL --define long= shoot ;) -- and YGTBK! my top-level came back! > > > > THis is a night mare > > > At the very least it must scare some EEs away from FPGA design =A0;) = =A0One a more serious note, I'm still hoping that five years after the buyo= ut of Hier Design, the people behind Planahead didn't get brainwashed and w= ould suggest the rest of the Design Software Division at Xilinx to put some= common sense in ISE (such as using --again-- a text format for the project= file). > > > -- > > Matthieu Michon <prenom....@gmail.com>- Hide quoted text - > > > - Show quoted text - > > 11.x uses text format again > > so at least once Xilinx has listened, well I bet they just had no > choice as the binary project file in their implementation is nothing > else and pure nightmare > > Antti 10.x has a project restore file, which is a bit of a pain to use but not as bad as copying all your sources and building a new hierarchy and remembering all of the build settings. Just run the <project_name>.restore file in a Tcl shell (directions are included in the .restore file - yes it's a text file). 10.x has a problem with certain background applications including Carbonite backup for instance that insert themselves into the file system. I imagine your source control may fall in this category. You could try to disable it while running ISE from the GUI and see if the problem goes away. Regards, GaborArticle: 143834
Dear all, Has anyone ordered and used the ML605 Evaluation Kit? http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm I noticed some attractive features like DDR3, PCIe Gen 2 and quite high FPGA capacity (241,152 logic cells). Before my ordering I would like to hear some comments. Another feature of this board is the adoption of the FMC interfaces. This is a new face to me, but it looks quite promising. However I have a concern about it: if I just want to interface some simple IO devices (e.g. a LCD panel and some push buttons), does that mean I still have to do the PCB layout for them with a FMC connection (previously it could be solved just by some IO pin headers)? I also do not quite understand the pricing, I notice that the XC6VLX240T-1FFG1156CES chip itself costs about $2,100, but the fledged ML506 Kit only takes $1,995. Is this just a marketing scheme or there are some other reasons? Thanks very much for your time! LucienArticle: 143835
On Oct 26, 10:38=A0pm, Kastil Jan <ikas...@stud.fit.vutbr.cz> wrote:
> Hello all,
> I am hoping that someone had solved problem similar to mine. I want to ru=
n
> tcl
> script in planAhead to create project, run some implementation and import
> the results into the floorplan. So I run these commands:
>
> hdi::run add -name impl_1 -project project_bft_core_hdl -floorplan
> floorplan_1 -parentRun synth_2 -part {xc5vsx35tff665-1} -flow {ISE 11}
> -strategy {Strategy #1};
> hdi::run launch -project project_bft_core_hdl
> -runs impl_1 -jobs 2 -scriptsOnly no -allPlacement no -dir
> /.../Projects/project_bft_core_hdl/project_bft_core_hdl.runs;
> hdi::run import -name impl_1 -project project_bft_core_hdl -placement yes
>
> Unfortunatelly I receive error:
>
> ERROR: Run 'impl_1' appears to not be finished. Unable to import
>
> Is there any way how to force tcl script to wait for the result of the
> dhi::run launch?
>
> Thanks for every answer
>
> Jan
hdi::run wait -name impl_1 -project project_bft_core_hdl
Article: 143836On Oct 21, 5:49=A0pm, nobody <cydrollin...@gmail.com> wrote: > me? Now if a collection of individuals got together and developed an > account it looks more like a firm many hands producing on the capital > someone spends to get the job done. That is actually the way it works > together we get the job done quick and capable. But that is one idea > among one individual, now put several individuals together and see > what we can get done. How would you make sure that every team member got his/her fair share of the revenue? How would licensing of necessary tools be made? What about lab testing? Production and distribution of evaluation boards? How will NDAs be handled? I am a simple salaryman, but I see how big the bucks are in FPGA programming. I would really like to have a piece of that cake, but it is safer to stay in a paid job than taking the risk of self-employment even though my FPGA coding make my company rich and prosperous. I would join your team, but I would not give up my regular job and that is going to limit me. I can't work on things that would be in direct competition to my employer, all my code would be tainted, and sooner or later I would face legal actions if I get too successful as a contributor. I think your idea is good and even if others have failed that is not a reason to not try to make it work. Good luck and thumbs up, -- SvennArticle: 143837
On Oct 28, 8:27=A0am, LucienZ <lucien.zh...@gmail.com> wrote: > Dear all, > > Has anyone ordered and used the ML605 Evaluation Kit?http://www.xilinx.co= m/products/devkits/EK-V6-ML605-G.htm > I noticed some attractive features like DDR3, PCIe Gen 2 and quite > high FPGA capacity (241,152 logic cells). Before my ordering I would > like to hear some comments. > > Another feature of this board is the adoption of the FMC interfaces. > This is a new face to me, but it looks quite promising. However I have > a concern about it: if I just want to interface some simple IO devices > (e.g. a LCD panel and some push buttons), does that mean I still have > to do the PCB layout for them with a FMC connection (previously it > could be solved just by some IO pin headers)? > > I also do not quite understand the pricing, I notice that the > XC6VLX240T-1FFG1156CES chip itself costs about $2,100, but the fledged > ML506 Kit only takes $1,995. Is this just a marketing scheme or there > are some other reasons? > > Thanks very much for your time! > Lucien Yes, the features do make it a pretty cool board. :-) The main board already has push buttons, LEDS and a LCD so you are covered there. If you do want add on additional peripherals then yes, you will need to design a board as it isn't practical to attach wires to the FMC connectors. Xilinx will/should be releasing a FMC that is primarily intending for simple debug and is comprised of a series of 100 mil headers that are connected to the FMC connector. This board could also be used for prototyping purposes. Ed McGettigan -- Xilinx Inc.Article: 143838
> Yes, the features do make it a pretty cool board. :-) > > The main board already has push buttons, LEDS and a LCD so you are > covered there. If you do want add on additional peripherals then yes, > you will need to design a board as it isn't practical to attach wires > to the FMC connectors. Thanks Ed! Maybe I would like to interface a color LCD and two CMOS image sensors, which are not very demanding for the IO performance. Without testing I do not want to make a custom PCB first... > Xilinx will/should be releasing a FMC that is primarily intending for > simple debug and is comprised of a series of 100 mil headers that are > connected to the FMC connector. This board could also be used for > prototyping purposes. This is what I would like to see for fast prototyping some simple IO devices :). Do you already have such a plan? And when could such a daughter board be available?Article: 143839
On Oct 28, 6:43=A0pm, LucienZ <lucien.zh...@gmail.com> wrote: > > Yes, the features do make it a pretty cool board. :-) > > > The main board already has push buttons, LEDS and a LCD so you are > > covered there. If you do want add on additional peripherals then yes, > > you will need to design a board as it isn't practical to attach wires > > to the FMC connectors. > > Thanks Ed! > > Maybe I would like to interface a color LCD and two CMOS image > sensors, which are not very demanding for the IO performance. Without > testing I do not want to make a custom PCB first... > > > Xilinx will/should be releasing a FMC that is primarily intending for > > simple debug and is comprised of a series of 100 mil headers that are > > connected to the FMC connector. =A0This board could also be used for > > prototyping purposes. > > This is what I would like to see for fast prototyping some simple IO > devices :). Do you already have such a plan? And when could such a > daughter board be available? Yes, we have this in the current plan and have the first article in house. It should be released by the end of the year, but it could slip into January. Pricing hasn't been set yet, but since it appears that we are subsidizing the ML605 we'll probably have to make it up on the modules. Sort of the razor and razor blades model. :-) I have been concerned about the hobbyist/academic/small-shop use of the FMC interface. I'm hoping that we can find the time to put together some basic LPC and HPC 6 layer PCB examples using the free tools from low cost, quick turn PCB fabricators like PCB123. These could then be used as the basis for a quick custom FMC board. Ed McGettigan -- Xilinx Inc.Article: 143840
Hi, I am working on designing a state machine which will read some data from a relatively large external ROM and process it. I expect the ROM size to be on the order of 32k x 32 bits, or 64k x 32 bits (quite likely the latter because my data table is just a little larger than 32k entries at the moment). Is there a good way to model this in a VHDL testbench in such a way that XST simulator can handle it? I don't really want to have to build a gigantic constant assignment table, but I also suspect that declaring an array of std_logic_vectors as a signal and then writing them one by one in from a file would probably take a really long time to execute. I searched around a while last week but didn't really find any concrete answers on this... Cheers, TSMArticle: 143841
Hi all, I am now using an Atmel AT45DB321D SPI flash booting xc5vsx50t-ff1136 and there is something wrong. First, the FPGA can be programmed successfully, and the flash also can be programmed successfully both directly & indirectly via iMPACT. But the FPGA just can't boot from the flash. I checked the timing diagram of the signals: PROG_B, INIT_B, M[2:0], FS[2:0], FCS_B, CCLK, MOSI, DIN, the MOSI did not function right compared to the timing diagram in XAPP951 page8 (M[2:0] =001,FS[2:0]=111). Pin MOSI clocks out 001100000.... after FCS_B goes low and it should be 000010110... I have no idea what's wrong and what should I do to fix this. So any help would be thankfull!Article: 143842
I'm a little bit confused-- Why are you using the microblaze-xilinx- elf targeted gcc to compile what should be the PC-side application where you want to do fprintf? What does your source code look like? I've never used microblaze, but my assumption is that you'd want to use the microblaze gcc only to compile that code that goes onto your microblaze on the FPGA. Then you could compile a regular C (or other language) program on the computer to send commands to your FPGA board and listen for data coming back, which can then be easily written to a text file for later analysis. Personally I like to use Python to do this, though, because once you have pyserial installed, the serial port routines are a breeze to work with.. and matplotlib is nice for graphing results, too. Writing to a text file with VHDL is useful to log results from a simulation, not from an actual running chip.Article: 143843
On Oct 29, 6:21=A0am, TSMGrizzly <sbatt...@yahoo.co.jp> wrote: > > I don't really want to have to build a gigantic constant assignment > table, Why not? That's the fastest way to accomplish the task...fast both for development as well as fast sim. > but I also suspect that declaring an array of std_logic_vectors > as a signal and then writing them one by one in from a file would > probably take a really long time to execute. Well, the first order of business is that you won't be writing an array of std_logic_vectors to a file in order model a ROM, you would be reading them in from a file. Second, your suspicions are not correct, the sim time to read in and parse the ROM data would be negligible. The development time to do this however, would be considerably longer though then simply defining the constant array. It's up to you to decide on how to spend your time. > I searched around a while last week but didn't really find any > concrete answers on this... You may find an already written model for the part that you'll be using on http://www.freemodelfoundry.com/ Kevin JenningsArticle: 143844
Hi, I'm designing using ROM and hex file.I'm new at using this. I've created this .hex file for the ROM and everytime I close the quartus window and open the hex file again to edit it, it says "cant open file -- file contains ni memory cell values"..?? what I did wrong?helpArticle: 143845
TSMGrizzly <sbattazz@yahoo.co.jp> wrote: > I'm a little bit confused-- Why are you using the microblaze-xilinx- > elf targeted gcc to compile what should be the PC-side application > where you want to do fprintf? > What does your source code look like? Well, one could connect up some device to an FPGA mircoblaze that one could fprintf to. A serial printer might not be so hard, a little harder for a disk drive and file system. Maybe NFS through ethernet wouldn't be so bad, either. > I've never used microblaze, but my assumption is that you'd want to > use the microblaze gcc only to compile that code that goes onto your > microblaze on the FPGA. > Then you could compile a regular C (or other language) program on the > computer to send commands to your FPGA board and listen for data > coming back, which can then be easily written to a text file for later > analysis. Yes, it doesn't seem that the OP has such attached to the microblaze. -- glenArticle: 143846
> > I don't really want to have to build a gigantic constant assignment > > table, > > Why not? =A0That's the fastest way to accomplish the task...fast both > for development as well as fast sim. Well, because I didn't really want such a long constant table as part of my testbench, though I suppose I can keep it in package in a separate file where it would be out of the way. > Well, the first order of business is that you won't be writing an > array of std_logic_vectors to a file in order model a ROM, you would > be reading them in from a file. Yes, this is what I meant.. writing the values into the std_logic_vectors after having read them from the file. > > Second, your suspicions are not correct, the sim time to read in and > parse the ROM data would be negligible. =A0The development time to do > this however, would be considerably longer though then simply defining > the constant array. =A0It's up to you to decide on how to spend your > time. I don't really see too much difference in the time spent either way. I have some code from my last testbench where I read stimulus in from a text file, so it should be pretty quick to adapt. Admittedly a script to write the constant table would be a little quicker, so I will probably go with your suggestion on that. > You may find an already written model for the part that you'll be > using onhttp://www.freemodelfoundry.com/ Awesome, I will take a look. > > Kevin Jennings Thanks for the quick answer! Sorry to be bothering you with such a trivial question.Article: 143847
On Wed, 28 Oct 2009 20:56:46 -0700 (PDT), Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: >On Oct 28, 6:43pm, LucienZ <lucien.zh...@gmail.com> wrote: >> > Yes, the features do make it a pretty cool board. :-) >> > Xilinx will/should be releasing a FMC that is primarily intending for >> > simple debug and is comprised of a series of 100 mil headers that are >> > connected to the FMC connector. This board could also be used for >> > prototyping purposes. >> >> This is what I would like to see for fast prototyping some simple IO >> devices :). Do you already have such a plan? And when could such a >> daughter board be available? > >I have been concerned about the hobbyist/academic/small-shop use of >the FMC interface. I'm hoping that we can find the time to put >together some basic LPC and HPC 6 layer PCB examples using the free >tools from low cost, quick turn PCB fabricators like PCB123. These >could then be used as the basis for a quick custom FMC board. If you don't want to get involved with the fabrication etc, simply make the PCB123 design files available in the download section. One for a debug-type board (0.1" headers). Possibly one for an 0.1" stripboard with power planes and FMC connector. And DEFINITELY one for an empty FMC board with the correct outline and the connector placed, possibly also tracked out. I gave up on the PCB123 schematic editor long ago; it's easier to edit the netlist, so these board files should be accompanied by the netlist (and/or schematic if appropriate). - BrianArticle: 143848
On Thu, 29 Oct 2009 04:31:49 -0700 (PDT), TSMGrizzly <sbattazz@yahoo.co.jp> wrote: >> > I don't really want to have to build a gigantic constant assignment >> > table, >> >> Why not? That's the fastest way to accomplish the task...fast both >> for development as well as fast sim. > >Well, because I didn't really want such a long constant table as part >of my testbench, though I suppose I can keep it in package in a >separate file where it would be out of the way. Keep it as a separate file. The tool that creates it simply has to print a few lines of boilerplate VHDL at each end. >> Second, your suspicions are not correct, the sim time to read in and >> parse the ROM data would be negligible. The development time to do >> this however, would be considerably longer though then simply defining >> the constant array. Seconded. If you need to read files created by other tools (e.g. a spreadsheet, or a binary file like a .bmp) this is a reasonable way to do it, and more flexible than the above approach. However ISE Simulator has some not-well-documented obstacles(*) to reading binary files, which is more straightforward in Modelsim. (*) As of ISE10: a) it is opposite-endian to Modelsim's treatment of the same file. b) ISIM writes an undocumented header before the file contents, and expects to see that header on any file it reads. You can convert a 3rd party file to/from ISIM using head, tail and cat to extract/insert the header (on Linux, or the Windows equivalent commands) but it's a bother. c) Xilinx have declined to document this header. However there is a Change Request to fix these issues; I have no idea if/when it will happen. - BrianArticle: 143849
On Thu, 29 Oct 2009 06:22:33 -0500, "zss" <zarithss@yahoo.com> wrote: >Hi, I'm designing using ROM and hex file.I'm new at using this. >I've created this .hex file for the ROM and everytime I close the quartus >window and open the hex file again to edit it, it says > >"cant open file -- file contains ni memory cell values"..?? > >what I did wrong?help You may need to build a shrubbery. - Brian
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