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I have seen this message when I placed a clock input on a clock capable (CC) IO pin rather than a global clock (GC) IO pin. Maybe ISE thinks that your signal is a clock. Try looking in the synthesis report to see how that input is being synthesized. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144176
maxascent wrote:
> Try looking in the synthesis report to see how that
> input is being synthesized.
Yes, a coding error can give an unexpected clock input.
-- Mike Treseler
Article: 144177Antti wrote: > from vhdl to the programming files, and programming without actel > programmer using DirecC and usb-jtag cable great ! however there is an issue with DirectC : I couldn't find a distribution license. That is : what if I design some stuff using that is meant to flash an Actel ProASIC3, and that reuses Actel's DirectC ? Is it intended by Actel, or just as a design guide, or something else that is highly proprietary and can't be republished ? My local rep has no answer to this, though a bit of code reading shows that it's just a JTAG wrapper, or something like that. And a rather nice one, but what am I allowed to do with that ? > Antti yg -- http://ygdes.com / http://yasep.orgArticle: 144178
On Nov 17, 8:29=A0pm, whygee <y...@yg.yg> wrote: > Antti wrote: > > from vhdl to the programming files, and programming without actel > > programmer using DirecC and usb-jtag cable > > great ! > however there is an issue with DirectC : > I couldn't find a distribution license. > That is : what if I design some stuff using > that is meant to flash an Actel ProASIC3, > and that reuses Actel's DirectC ? > Is it intended by Actel, or just as > a design guide, or something else > that is highly proprietary and can't be republished ? > My local rep has no answer to this, > though a bit of code reading shows that > it's just a JTAG wrapper, or something like that. > And a rather nice one, but what am I allowed to > do with that ? > > > Antti > > yg > > --http://ygdes.com/http://yasep.org did you have to sign NDA? NO. was click-through license required to get download? NO. The is no restrictive license bound, and see DirectC is not some "generic" JTAG wrapper it is ABSOLUTLY Actel only code. So whatever you do with DirectC it is only to program Actel FPGA's so I am confident that there will be no issues. AnttiArticle: 144179
Antti wrote: > did you have to sign NDA? NO. > was click-through license required to get download? NO. > > The is no restrictive license bound, and see DirectC > is not some "generic" JTAG wrapper it is ABSOLUTLY > Actel only code. So whatever you do with DirectC > it is only to program Actel FPGA's so I am confident > that there will be no issues. I believe you. However, I am annoyed that there is no mention of this anywhere. For example, let's suppose I integrate it in either a proprietary or GPLv3 project : I can't either, from a legal point of view. So what I expect is an official, clear and useful statement from Actel about this code. Put this in the public domain, or Creative Commons, or BSD, but please Actel, do something. Or I'll trade efforts for time and rewrite a DirectC clone myself, which is not something that I wish. > Antti yg -- http://ygdes.com / http://yasep.orgArticle: 144180
For Altera Straix4 GX FPGA, Is there a bridge module available between the Avalon-ST to Avalon-MM? Trying to use the PCIE endpoint hard IP using Altera Megawizard software. But this interface generates the Avalon streaming output. I think for what I am doing I do not need very high performance bus and Avalon-MM may work. Avalon MM is much simpler bus The thing is that the PCIE endpoint interface needs to be connected to several modules with other users trying to design. It may be much easier in multi-user environment to use the Avalon-MM bus then to use the Avalon-ST bus. This is why I was just curious if there is Avalon-ST to Avalon-MM bus bridge? This way the endpoint can use the Avalon-ST bus but then bridge will have Avalon-MM interface which will allow numerous devices to be on that bus. Any suggestions.Article: 144181
On Nov 14, 3:18=A0pm, Michael S <already5cho...@yahoo.com> wrote: > Hi > We have a problem with Altera Stratix IV GX FPGA Development Kit. > Specifically, we build a PCI Express design based on Altera's own > "hard" PCI-E core configured for Gen.1 x4 operation. The design works > (more or less, but that's behind the scope of this message) when it is > plugged into x8 mechanical/x4 electrical slot. However when plugged in > x8 or x16 mechanical slots which are electrically x8 the design not > only doesn't work but not even recognized by the host as valid PCI-E > device. Exactly the same happens when we are trying to build x1 > device. > We validated (by plugging off-the-shelf x1 and x4 PCI-E cards) that > it's not a host issue. > My only PCI-E book (Mindshare "PCI Express System Architecture") tells > virtually nothing about width negotiation so right now I am totally > lost. > > Any ideas to help? I'm guessing a bit, but... That card has an x8 PHY on it. So the motherboard thinks that it is an x8 card, and link aggregation fails. The motherboard (typically) decides that it's an x8 card by doing a receiver detect. All the receiver detect does is check for a load on the drivers. To test this out, mask off all of the receivers for the unused (last 4) channels. If I'm right (it could happen) the motherboard won't see the receivers, and aggregate as an x4. RKArticle: 144182
Antti wrote: > 5 minutes video > http://www.youtube.com/watch?v=hnmSJJOD86A > > from vhdl to the programming files, and programming without actel > programmer using DirecC and usb-jtag cable Can you update your website(s) to reflect the offer you present at the end of the video ? And where can one find the technical details about the USB/JTAG device you present ? > Antti yg -- http://ygdes.com / http://yasep.orgArticle: 144183
On Nov 11, 2:20=A0am, pavithra gowda <pavithra08051...@gmail.com> wrote: > hi... > i m using edk 10.1 version.i m new to edk.now i m able to create > simple pheripheral(it is not having any submodules and user libaries). > actualy my code having many submodules and user libraries.please can > any one tell how to add other suhmodules and user libraries with > custom pherpheral using create or import pheripheral wizard.or how > compile my libaries and submodules in the custom pheripheral > directory.if any tells it will be more usefull for me. > thanku.... u must instantiate the submodule in the userlogic.vhd file inside the pcore\vhdl directory. then u must port map the required signals appropriately with the appropriate bits of slaveregister.Article: 144184
I wonder if anyone have experience with this. I want some HW that can compete with the serial flash programming speed. Maybe some kind of usb-io pre-programmed microcontroller that can run at full speed. Will any of the available blaster HW's be able to run at full speed if integrated close to the fpga?Article: 144185
On Nov 18, 11:36=A0am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > I wonder if anyone have experience with this. > I want some HW that can compete with the serial flash programming speed. > Maybe some kind of usb-io pre-programmed microcontroller that can run at > full speed. > Will any of the available blaster HW's be able to run at full speed if > integrated close to the fpga? if this is commercial project please contact me per email, we have several products that built in USB blaster mode from FS USB you can not get full speed as of the usb limit with HS usb, possible, or when downloading from local fast media AnttiArticle: 144186
ML 403 evaluation board (Virtex 4)
Xilinx ISE 11.1
Essentially we are trying to a load a simple program onto our FPGA but we
have been having a lot of trouble. We have a simple program with two inputs
a and b and and output y. We are simply trying to execute y <= a OR b. We
are trying to assign a and b inputs to button switches on the board and the
output y to an LED. We have looked online for the proper pinouts but are
getting an error after changing the ucf file to match the pinouts posted
online. Can someone please offer a step by step process to load this simple
program onto the virtex 4?
--------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY orgate IS
PORT ( a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
y : OUT_STD_LOGIC_VECTOR (1 DOWNTO 0));
END orgate;
ARCHITECTURE orgate1 OF orgate IS
BEGIN
y <= (a OR b);
END orgate1;
---------------------------------------------------
thanks!
Article: 144187glallenjr wrote: > Can someone please offer a step by step process to load this simple > program onto the virtex 4? > -------------------------------------------------- > LIBRARY ieee; > USE ieee.std_logic_1164.all; > > ENTITY orgate IS > PORT ( a : IN STD_LOGIC_VECTOR (1 DOWNTO 0); > b : IN STD_LOGIC_VECTOR (1 DOWNTO 0); > y : OUT_STD_LOGIC_VECTOR (1 DOWNTO 0)); > END orgate; > > ARCHITECTURE orgate1 OF orgate IS > BEGIN > y <= (a OR b); > END orgate1; > --------------------------------------------------- it's completely buggy : a, b and y are 2-bit vectors ??? and what about the OUT_ : remove the '_' it's more a VHDL syntax learning problem that is the cause of those troubles (for now). > thanks! well... -- http://ygdes.com / http://yasep.orgArticle: 144188
Hi folks- I'm in the beginning stages of crafting a high-speed measurement device which needs to output a floating point value in ASCII string form that represents the measurement at a rate of 10 kHz. I'm using an Altera FPGA that runs Nios2. Convenient standard library functions like sprintf() or ftoa() running as code will be too time-consuming to meet my high throughput requirements. What I need is an ultrafast float to ASCII conversion function that can run in code *or* a strategy for implementing a conversion function in HDL. Altera has a nice tool called C to HDL compiler which I'm looking at now. It seems to me that a fast float to ASCII conversion function would be a common function of many embedded systems. Rather than me reinventing the wheel, can anyone point me to a resource (example on the web or a product for sale) that I can use to achieve my goal? Thanks, John Speth.Article: 144189
John Speth <johnspeth@yahoo.com> wrote: > I'm in the beginning stages of crafting a high-speed measurement device > which needs to output a floating point value in ASCII string form that > represents the measurement at a rate of 10 kHz. I'm using an Altera FPGA > that runs Nios2. Convenient standard library functions like sprintf() or > ftoa() running as code will be too time-consuming to meet my high throughput > requirements. What I need is an ultrafast float to ASCII conversion > function that can run in code *or* a strategy for implementing a conversion > function in HDL. Altera has a nice tool called C to HDL compiler which I'm > looking at now. It would seem easier to write the internal form of the floating point value and convert it outside. > It seems to me that a fast float to ASCII conversion function would be a > common function of many embedded systems. Rather than me reinventing the > wheel, can anyone point me to a resource (example on the web or a product > for sale) that I can use to achieve my goal? Most embedded work is done in fixed point. One of the slowest parts of the library for most HLLs is the conversion between floating point and ASCII representation. It also tends to be big, especially if it tries to be fast. As you don't say what your underlying problem is, it is hard to say much more. It might be that using decimal floating point, which is much easier to convert, would help. -- glenArticle: 144190
Reading from the "PCI Express Compiler User Guide 9.1": "The PCI Express Compiler configured using the SOPC Builder design flow uses the PCI Express Compiler's Avalon-MM bridge module to connect the PCI Express link to the system interconnect fabric." Regards, Michele. "Test01" <cpandya@yahoo.com> ha scritto nel messaggio news:89e1a713-32bd-4168-b40d-b9f789f60a6e@d5g2000yqm.googlegroups.com... > For Altera Straix4 GX FPGA, Is there a bridge module available between > the Avalon-ST to Avalon-MM? Trying to use the PCIE endpoint hard IP > using Altera Megawizard software. But this interface generates the > Avalon streaming output. I think for what I am doing I do not need > very high performance bus and Avalon-MM may work. Avalon MM is much > simpler bus The thing is that the PCIE endpoint interface needs to be > connected to several modules with other users trying to design. It > may be much easier in multi-user environment to use the Avalon-MM bus > then to use the Avalon-ST bus. This is why I was just curious if there > is Avalon-ST to Avalon-MM bus bridge? This way the endpoint can use > the Avalon-ST bus but then bridge will have Avalon-MM interface which > will allow numerous devices to be on that bus. > > Any suggestions.Article: 144191
On Nov 18, 4:15=A0pm, "Michele" <a...@a.a> wrote: > Reading from the "PCI Express Compiler User Guide 9.1": > > "The PCI Express Compiler configured using the SOPC Builder design flow u= ses > the > PCI Express Compiler's Avalon-MM bridge module to connect the PCI Express > link to > the system interconnect fabric." > > Regards, > Michele. > > "Test01" <cpan...@yahoo.com> ha scritto nel messaggionews:89e1a713-32bd-4= 168-b40d-b9f789f60a6e@d5g2000yqm.googlegroups.com... > > > > > For Altera Straix4 GX FPGA, Is there a bridge module available between > > the Avalon-ST to Avalon-MM? =A0Trying to use the PCIE endpoint hard IP > > using Altera Megawizard software. =A0But this interface generates the > > Avalon streaming output. I think for what I am doing I do not need > > very high performance bus and Avalon-MM may work. =A0Avalon MM is much > > simpler bus =A0The thing is that the PCIE endpoint interface needs to b= e > > connected to several modules with other users trying to design. =A0It > > may be much easier in multi-user environment to use the Avalon-MM bus > > then to use the Avalon-ST bus. This is why I was just curious if there > > is Avalon-ST to Avalon-MM bus bridge? =A0This way the endpoint can use > > the Avalon-ST bus but then bridge will have Avalon-MM interface which > > will allow numerous devices to be on that bus. > > > Any suggestions.- Hide quoted text - > > - Show quoted text - I understand that SOPC flow provides this capability but here is what I am looking for from the PCIe endpoint Verilog module. - Needs to be verilog module that I can instantiate and synthesize in my Top verilog file. It seems to be generating the verilog output but it also has a lot other things in that file I may not need. The verilog output also has some stuff related to simulation. I guess it is OK to start removing the stuff form this file if I do not need it. For example I may not need the DMA controller module. - Only contains PCIe endpoint that has Avelon-MM interface on the the backside. It will be good to not have other modules. - I use VCS to simulate and Synplify for synthesis. I am not sure how well it fits in this flow. I am sure this is documented somewhere but it is taking some time for me to dig through the information. Any suggestions? ThanksArticle: 144192
Hi All, The latest version of the program is beta version 0.945. Python scripting, improved GUI zooming, and logic function simulations have been the focus in the 0.94X series An application note on the website shows how to automatically generate timing diagrams directly from vhdl. Using file I/O from VHDL or any RTL, you output text files that are python scripts that the TimingAnalyzer executes to build timing diagrams from simulations. One use is automatically generating 100s of timing of timing diagrams from simulations for documentation purposes. Also, I hope you know that the program is now freeWare so this is not a marketing or sales message but just a message to keep others in our business informed about new features. As always, user feedback is welcome and your opinions and suggestions are shaping the look and feel of the program. You can see a list of all the changes at http://www.timing-diagrams.com/dokuwiki/doku.php?id=download Thank you, Dan Fabrizio www.timing-diagrams.comArticle: 144193
"glallenjr" <glallenjr@gmail.com> writes:
> ML 403 evaluation board (Virtex 4)
> Xilinx ISE 11.1
>
> Essentially we are trying to a load a simple program onto our FPGA but we
> have been having a lot of trouble. We have a simple program with two inputs
> a and b and and output y. We are simply trying to execute y <= a OR b. We
> are trying to assign a and b inputs to button switches on the board and the
> output y to an LED. We have looked online for the proper pinouts but are
> getting an error after changing the ucf file to match the pinouts posted
> online. Can someone please offer a step by step process to load this simple
> program onto the virtex 4?
> --------------------------------------------------
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
>
> ENTITY orgate IS
> PORT ( a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
> b : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
> y : OUT_STD_LOGIC_VECTOR (1 DOWNTO 0));
> END orgate;
>
> ARCHITECTURE orgate1 OF orgate IS
> BEGIN
> y <= (a OR b);
> END orgate1;
As has been pointed out, that's not valid VHDL. I suggest you learn to
simulate your design first. You can iterate fixes *much* quicker.
I know it's not as exciting as actually flashing lights, but it really
is the way to go!
As I'm waiting for XPS to compile (yawn), here's a simulator testbench
to get you going.... as I use Emacs vhdl-mode, this took me about 35
secs :) You'll see there's some bits for you to fill in...
library ieee;
use ieee.std_logic_1164.all;
entity tb_orgate is
end entity tb_orgate;
architecture test of tb_orgate is
signal a : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal b : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal y : STD_LOGIC_VECTOR (1 DOWNTO 0);
begin -- architecture test
DUT: entity work.orgate
port map (
a => a,
b => b,
y => y);
WaveGen_Proc: process
begin
a <= "00";
b <= "00";
wait for 0 ns; -- allow gate to propogate result
assert y="Put the answer you expect in here"
report "answer wrong"
severity error;
wait for 10 ns; -- just so the waveforms progress along the time axis!
a <= "01";
b <= "10";
wait for 0 ns; -- allow gate to propogate result
assert y="Put the answer you expect in here"
report "answer wrong"
severity error;
-- Put some more tests in here with different a and b values
-- for extra credit use a pair of nested loops to test all the combinations of inputs,
-- using VHDL to "calculate" the right answer to put in the assert statement
report (time'image(now) & " Finished");
wait;
end process WaveGen_Proc;
end architecture test;
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Article: 144194Dear All Could you help me : How calculate BER far from Shannon Limit ???? "Bit-Error Rate (BER) performance that is within ????? db of the Shannon Limit"? and how calculate gab of degree distribution from the shannon limit ? the degree distributions from LDPC codes, which have performance gap from the Shannon limit, about.........=D8=9F=D8=9F=D8=9F=D8=9F=D8=9F=D8=9F=D8=9F=D8= =9FArticle: 144195
John Speth pisze: > Hi folks- > > I'm in the beginning stages of crafting a high-speed measurement device > which needs to output a floating point value in ASCII string form that > represents the measurement at a rate of 10 kHz. I'm using an Altera FPGA > that runs Nios2. Convenient standard library functions like sprintf() or > ftoa() running as code will be too time-consuming to meet my high throughput > requirements. What I need is an ultrafast float to ASCII conversion > function that can run in code *or* a strategy for implementing a conversion > function in HDL. Altera has a nice tool called C to HDL compiler which I'm > looking at now. > > It seems to me that a fast float to ASCII conversion function would be a > common function of many embedded systems. Rather than me reinventing the > wheel, can anyone point me to a resource (example on the web or a product > for sale) that I can use to achieve my goal? > > Thanks, John Speth. > > Hi John, Which NIOS version are you using ? How fast it should be ? CPU freq ? AdamArticle: 144196
I simulate LDPC code over AWGN channel I need to simulate over fading channel How implement fading channel in matlab ? ad what is the modification require in my code ?Article: 144197
For Altera Straix4 GX FPGA, Is there a bridge module available between the Avalon-ST to Avalon-MM? Trying to use the PCIE endpoint hard IP using Altera Megawizard software. But this interface generates the Avalon streaming output. I think for what I am doing I do not need very high performance bus and Avalon-MM may work. Avalon MM is much simpler bus The thing is that the PCIE endpoint interface needs to be connected to several modules with other users trying to design. It may be much easier in multi-user environment to use the Avalon-MM bus then to use the Avalon-ST bus. This is why I was just curious if there is Avalon-ST to Avalon-MM bus bridge? This way the endpoint can use the Avalon-ST bus but then bridge will have Avalon-MM interface which will allow numerous devices to be on that bus. I understand that SOPC flow provides this capability but here is what I am looking for from the PCIe endpoint Verilog module. - Needs to be verilog module that I can instantiate and synthesize in my Top verilog file. It seems to be generating the verilog output but it also has a lot other things in that file I may not need. The verilog output also has some stuff related to simulation. I guess it is OK to start removing the stuff form this file if I do not need it. For example I may not need the DMA controller module. - Only contains PCIe endpoint that has Avelon-MM interface on the the backside. It will be good to not have other modules. - I use VCS to simulate and Synplify for synthesis. I am not sure how well it fits in this flow. I am sure this is documented somewhere but it is taking some time for me to dig through the information. Any suggestions?Article: 144198
For Altera Straix4 GX FPGA, Is there a bridge module available between the Avalon-ST to Avalon-MM? Trying to use the PCIE endpoint hard IP using Altera Megawizard software. But this interface generates the Avalon streaming output. I think for what I am doing I do not need very high performance bus and Avalon-MM may work. Avalon MM is much simpler bus The thing is that the PCIE endpoint interface needs to be connected to several modules with other users trying to design. It may be much easier in multi-user environment to use the Avalon-MM bus then to use the Avalon-ST bus. This is why I was just curious if there is Avalon-ST to Avalon-MM bus bridge? This way the endpoint can use the Avalon-ST bus but then bridge will have Avalon-MM interface which will allow numerous devices to be on that bus. I understand that SOPC flow provides this capability but here is what I am looking for from the PCIe endpoint Verilog module. - Needs to be verilog module that I can instantiate and synthesize in my Top verilog file. It seems to be generating the verilog output but it also has a lot other things in that file I may not need. The verilog output also has some stuff related to simulation. I guess it is OK to start removing the stuff form this file if I do not need it. For example I may not need the DMA controller module. - Only contains PCIe endpoint that has Avelon-MM interface on the the backside. It will be good to not have other modules. - I use VCS to simulate and Synplify for synthesis. I am not sure how well it fits in this flow. I am sure this is documented somewhere but it is taking some time for me to dig through the information. Any suggestions?Article: 144199
Test01 pisze: > For Altera Straix4 GX FPGA, Is there a bridge module available > between > the Avalon-ST to Avalon-MM? Trying to use the PCIE endpoint hard IP > using Altera Megawizard software. But this interface generates the > Avalon streaming output. I think for what I am doing I do not need > very high performance bus and Avalon-MM may work. Avalon MM is much > simpler bus The thing is that the PCIE endpoint interface needs to > be > connected to several modules with other users trying to design. It > may be much easier in multi-user environment to use the Avalon-MM bus > then to use the Avalon-ST bus. This is why I was just curious if > there > is Avalon-ST to Avalon-MM bus bridge? This way the endpoint can use > the Avalon-ST bus but then bridge will have Avalon-MM interface which > will allow numerous devices to be on that bus. > > I understand that SOPC flow provides this capability but here is what > I am looking for from the PCIe endpoint Verilog module. > > > - Needs to be verilog module that I can instantiate and synthesize in > my Top verilog file. It seems to be generating the verilog output > but > it also has a lot other things in that file I may not need. The > verilog output also has some stuff related to simulation. I guess it > is OK to start removing the stuff form this file if I do not need it. > For example I may not need the DMA controller module. > - Only contains PCIe endpoint that has Avelon-MM interface on the the > backside. It will be good to not have other modules. > - I use VCS to simulate and Synplify for synthesis. I am not sure how > well it fits in this flow. I am sure this is documented somewhere > but > it is taking some time for me to dig through the information. > > > Any suggestions? http://www.altera.com/literature/hb/nios2/qts_qii55013.pdf?GSA_pos=2&WT.oss_r=1&WT.oss=Avalon%20ST%20to%20MM%20bridge Adam
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