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I am using Viertex5 hardip in pcie gen1 x4 configuration. The hard IP has PCI bar register configured for 512K memory space. The Root complex is sending out the memory read request to the V5 end point with valid address (that belongs to 512K memory block). The end point sends a request to the appropriate device behind it. But that device behind the end-point realistically only supports smaller chunk of that 512K memory block. Thus it does not respond with data to the cycle eventhough it belongs to its memory range. Is it OK to send out compelter abort TLP back to the root complex in such a situation? How to gracefully terminate such a cycle? Thanks.Article: 144876
Morppheu <jdemamann@gmail.com> wrote: >Hey guys... > >I need a little help with my E1 interface. >I have an internal clock and the E1 clock. When E1 chip (MT9076B) is >present I use the E1 clock + E1 F0 signals, else I use the internal >clock. Why use the internal clock? Isn't the MT9076 free running when it doesn't see a line-sync? >I know its a very bad design technique, but its an old code from >another guy and I am looking to make the things right. >What is the best way to interface with E1? Many years ago I did a design using the MT9075. I let its internal PLL deal with the E1 clock. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 144877
More venting then seeking help. I got my Diligent Sparta board and I have to say it appears to be a great value. Parts alone are worth the price. The down side is the Xilinx software DVD took up something like 7 gigs of hard drive space. As part of the install it looks for updates on the web site. Near as I can figure the install is broken as it gets to 4% on the 'examining current software configuration' and crashes HARD! Have to bring up Task Manager to kill it. Only took me about 10 times of hitting that 4% to figure out something is wrong. So while I am resting I decide to add up just how much patch they want to add to my distribution DVD: 2.6 gigs. Gee, just got the DVD last week and already 2.6 gigs of patches needed? The sad news is I live in a rural area so I am still on dial up. I could get satelite internet access but it runs something like $100/month last time I checked. At 50k I figure it would take about 8 days to download the patches. This would take a serious chunk out of my 30 day license for the software. I may go to my son's house to see if I can use his DSL to shorten the download time. So without the patch download the installation program didn't finish. Most of the 'software suite' busts with an error message because of the bad install and patch. I do get package to run and it is for the Xilinx embedded core development package. I have no interest in rolling my own embedded processor at this time. I mean it is great that Xilinx gives me free stuff I don't need or ask for but I am so rookie at this I don't even know what software goes with what products yet. Kind of a bummer in that I have to burn hard drive space and download patches for things I don't need or have any intention of using. I will try reinstalling the software. I will send off a polite email to Xilinx suggesting they do small footprint installs specific to hardware vs. kitchen sink suites. The funny thing is 10 years ago I just sat down at a work station and within minutes was placing 74LS type components and designing circuits that could then be compiled to fit in a FPGA or CPLD. Time has passed me by with new tools and techniques. I feel like I am getting into a car and asking "Where are the reins?" There's a certain Rip Van Winkle effect trying to get back into the fray. RickArticle: 144878
Rick wrote:
> So while I am resting I decide to add up just how much patch they want
> to add to my distribution DVD: 2.6 gigs. Gee, just got the DVD last
> week and already 2.6 gigs of patches needed? The sad news is I live in
> a rural area so I am still on dial up. I could get satelite internet
> access but it runs something like $100/month last time I checked. At
> 50k I figure it would take about 8 days to download the patches.
I'll bet brand X would ship you a DVD in less time and for less money.
> The funny thing is 10 years ago I just sat down at a work station and
> within minutes was placing 74LS type components and designing circuits
> that could then be compiled to fit in a FPGA or CPLD. Time has passed
> me by with new tools and techniques. I feel like I am getting into a
> car and asking "Where are the reins?" There's a certain Rip Van Winkle
> effect trying to get back into the fray.
Brand A has a very nice schematic editor with TTL components.
-- Mike Treseler
Article: 144879If the scale of the design has not changed since you were designing with schematics full of 74ls components, then that technique is just as viable today as it was then. But typically, the scale of the designs today renders schematics considerably less desirable than HDL. And once you've learned the HDL for synthesis, using HDL for testing your design is icing on the cake. I started out using Cadence Concept schematics for Xilinx FPGA's in the early 90's (XC3090), and built my own parameterizable library of sizeable arithmetic and data path schematic symbols that worked great. I had recursive schematic implementations (Concept lets you do that) of binary trees, counters, etc. and all was well. I resisted HDL for a short time (SW seemed to be headed in the other direction: from text to pictures), but eventually saw the light and embraced VHDL. And now I would not go back for anything. AndyArticle: 144880
On Jan 11, 2:43=A0pm, Andy <jonesa...@comcast.net> wrote: > If the scale of the design has not changed since you were designing > with schematics full of 74ls components, then that technique is just > as viable today as it was then. But typically, the scale of the > designs today renders schematics considerably less desirable than HDL. > And once you've learned the HDL for synthesis, using HDL for testing > your design is icing on the cake. > > I started out using Cadence Concept schematics for Xilinx FPGA's in > the early 90's (XC3090), and built my own parameterizable library of > sizeable arithmetic and data path schematic symbols that worked great. > I had recursive schematic implementations (Concept lets you do that) > of binary trees, counters, etc. and all was well. I resisted HDL for a > short time (SW seemed to be headed in the other direction: from text > to pictures), but eventually saw the light and embraced VHDL. And now > I would not go back for anything. > > Andy Thanks for the pointers. I killed another day fumbling around to see how much function I could get from the broken install and got to the ttl schematic entry. The device list starts at 74LS138 and goes up to 74LS521. I'm not sure if it is the install or me. The simple logic gates are there so I don't see a problem with picking up and placing a 2 input NAND gate vs. plunking a 74SL00 down. It's just an odd combination of me having senior momments and trying to use a professional tool in a hobbyist capacity. To make it clear, problem is mostly me: I've never met an integrated development environment I liked. I still like to use a text editor with an open DOS window to write and compile my C code from the command line.<grin> I think I will have to make the switch to VHDL. The stuff I want to do like memory mapped hardware I/O is so trivial it shouldn't be too hard to get to that skill level. Things are looking up. My son has a 30 mbyte connection and said we could patch up there in a half hour or so. I'll spend some time studying so I can get to the point of asking questions about VHDL. RickArticle: 144881
In article <05452d8a-9fe9-44d6-9395-1f4b6ae25806@a15g2000yqm.googlegroups.com>, Test01 <cpandya@yahoo.com> writes: >I am using Viertex5 hardip in pcie gen1 x4 configuration. The hard IP >has PCI bar register configured for 512K memory space. The Root >complex is sending out the memory read request to the V5 end point >with valid address (that belongs to 512K memory block). The end point >sends a request to the appropriate device behind it. But that device >behind the end-point realistically only supports smaller chunk of that >512K memory block. Thus it does not respond with data to the cycle >eventhough it belongs to its memory range. Is it OK to send out >compelter abort TLP back to the root complex in such a situation? How >to gracefully terminate such a cycle? If you "fix" your code to return something then you don't have to ask what the PCI stuff will do. 0 is sometimes convenient. Or you could use 0xdeadbeaf to make it conspicious. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 144882
Rick <richardcortese@gmail.com> writes: <snip> >I think I will have to make the switch to VHDL. The stuff I want to do >like memory mapped hardware I/O is so trivial it shouldn't be too hard >to get to that skill level. >Things are looking up. My son has a 30 mbyte connection and said we >could patch up there in a half hour or so. Hate to rain on your parade, but the speed limit is likely to be on the Xilinx end. It took about 12 hours on my DSL line to patch the 11.3 web edition (and then it didn't support the Cyclone 2 on the board I have and I had to downgrade :-)). The upside is that the web edition of ISE is free (although it doesn't support some of the larger FPGAs which may be an issue in your case as I haven't looked at the board you have) so you don't need to worry about the licence running out in 30 days if you download the web edition (and your DVD may have a copy of the web edition on it and may be a more reasonable place to start). >I'll spend some time studying so I can get to the point of asking >questions about VHDL. The folks in here are both knowlegable and helpful (I'm learning a lot just reading the posts flow by :-)). You may also want to have a look at www.fpga4fun.com as they have a variety of beginner level projects and documents that I find helpful (the cyclone2 is on one of their dragon boards). >Rick Peter Van EppArticle: 144883
Hi, when i do post route simulation i get a bunch of error similar to the following ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849 ps, 520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_4 # ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849 ps, 520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_1 # ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):106398 ps, posedge CLK:106849 ps, 520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_2 # ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):106398 ps, posedge CLK:106849 ps, 520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_3 who can tell me how to correct these errors?? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144884
Hi, when i do post route simulation i get a bunch of error similar to the following ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849 ps, 520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_4 # ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849 ps, 520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_1 # ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):106398 ps, posedge CLK:106849 ps, 520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_2 # ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):106398 ps, posedge CLK:106849 ps, 520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_3 who can tell me how to correct these errors?? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144885
> Why use the internal clock? Isn't the MT9076 free running when it
> doesn't see a line-sync?
Yes, the MT goes free running when its not sinced.
But the MT9076 is a module on my hardware. I can mount the backplane
with or without the MT9076 chip.
That is the point, what to do when I have the E1 module installed. How
to interface with it.
My FPGA is an Spartan 3e S100 (almost 100% full):
Logic Utilization:
Total Number Slice Registers: 737 out of 1,920 38%
Number used as Flip Flops: 731
Number used as Latches: 6
Number of 4 input LUTs: 956 out of 1,920 49%
Logic Distribution:
Number of occupied Slices: 959 out of
960 99%
Number of Slices containing only related logic: 959 out of
959 100%
Number of Slices containing unrelated logic: 0 out of
959 0%
*See NOTES below for an explanation of the effects of unrelated
logic
Total Number of 4 input LUTs: 1,910 out of 1,920 99%
Number used as logic: 956
Number used as a route-thru: 181
Number used for Dual Port RAMs: 768
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 5
Number of bonded IOBs: 93 out of 108 86%
IOB Flip Flops: 19
Number of Block RAMs: 4 out of 4 100%
Number of GCLKs: 9 out of 24 37%
Number of DCMs: 2 out of 2 100%
Another thing. How to reduce the area usage??
Thanks!
Article: 144886On Jan 11, 6:38=A0pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > In article <05452d8a-9fe9-44d6-9395-1f4b6ae25...@a15g2000yqm.googlegroups= .com>, > > =A0Test01 <cpan...@yahoo.com> writes: > >I am using Viertex5 hardip in pcie gen1 x4 configuration. =A0The hard IP > >has PCI bar register configured for 512K memory space. =A0The Root > >complex is sending out the memory read request to the V5 end point > >with valid address (that belongs to 512K memory block). =A0The end point > >sends a request to the appropriate device behind it. =A0But that device > >behind the end-point realistically only supports smaller chunk of that > >512K memory block. =A0Thus it does not respond with data to the cycle > >eventhough it belongs to its memory range. =A0Is it OK to send out > >compelter abort TLP back to the root complex in such a situation? =A0How > >to gracefully terminate such a cycle? > > If you "fix" your code to return something then you > don't have to ask what the PCI stuff will do. > > 0 is sometimes convenient. =A0Or you could use 0xdeadbeaf to > make it conspicious. > > -- > These are my opinions, not necessarily my employer's. =A0I hate spam. Thanks for getting back to me so basically if the device behind the end-point does not respond to the cycle then I can simply have a code that does normal PCIe completion cycle with data as ffff_ffff to match the data size. Can I not issue completer abort or some other abort mechanism in such a case? This particular case is not within my control as the device resides behind the FPGA (PCIe endpoint).Article: 144887
I need help on 200 pieces of a Virtex XC2V2000-5FF896C or XC2V2000-6FF896C . I can get these from Avent, but the pricing is way above what I can pay. I don't get the special pricing. If you have any excess on these FPGA's or any others please let me know. Thank you, Jon E. Hansen (949)864-7745Article: 144888
On Jan 11, 11:24=A0am, "morppheu" <morpp...@gmail.com> wrote: > What is the best way to interface with E1? The "best way" to interface to the E1 (a very low speed interface when compared to the operating speed of an FPGA) may be not to use the DCM at all but use a generic higher speed clock and transfer to/from the E1 domain across FIFOs or other asynchronous interfaces right by the I/ O, leaving the main processing to the generic, unlocked clock domain. Changing the clock source for the I/O from external to internal or vice versa can be accomplished through a BUFGMUX (since you appear to be in the Xilinx family) if you want the I/O timing to be on global clock resources.Article: 144889
On Jan 12, 10:12=A0am, jon <j...@pyramidemail.com> wrote: > I need help on 200 pieces of a Virtex XC2V2000-5FF896C or > XC2V2000-6FF896C . I can get these from Avent, but the pricing is way > above what I can pay. I don't get the special pricing. If you have any > excess on these =A0FPGA's or any others please let me know. > > Thank you, > Jon E. Hansen > (949)864-7745 Have you just looked at their online pricing or have you talked directly with your local Avnet office? [rhetorical question]Article: 144890
>Hi, >when i do post route simulation i get a bunch of error similar to the >following > ** Error: >F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( >negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849 ps, >520 ps ); ># Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_4 > who can tell me how to correct these errors?? > >--------------------------------------- >This message was sent using the comp.arch.fpga web interface on >http://www.FPGARelated.com > This error tells you that when you remove your reset signal that the flip flops see it 520 ps before the next rising edge of the clock and that this is not enough time if you wanted to change the flops value on that first clock. You need to redesign your reset distribution to ensure that it meets timing. --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144891
Hi. I'm looking for any .sopc-file example for this board. For example, how correctly connect DRAM, SRAM, "Spansion" flash and ethernet? Altera doesn't offer any examples officially. At least, how to connect QDRII SRAM?Article: 144892
Hi all, I was just about to download the new Xilinx ISE 11.1 evaluation package. However, I was told that the new Xilinx design suite does not support Xilinx Virtex II Pro devices anymore. Does anyone have an idea where I could get hold of an old version (Xilinx ISE 10.1.03) of this package from the web since I need to synthesize the design for a Virtex II Pro board. Many thanks, PhilippArticle: 144893
Morppheu <jdemamann@gmail.com> wrote: >> Why use the internal clock? Isn't the MT9076 free running when it >> doesn't see a line-sync? > >Yes, the MT goes free running when its not sinced. That is not a problem. Just use that clock always. >But the MT9076 is a module on my hardware. I can mount the backplane >with or without the MT9076 chip. I guess the logic is idle when the module is not mounted. Pulling the clock down or up to have a defined logic level should do it. >That is the point, what to do when I have the E1 module installed. How >to interface with it. >My FPGA is an Spartan 3e S100 (almost 100% full): > >Logic Utilization: > Total Number Slice Registers: 737 out of 1,920 38% > Number used as Flip Flops: 731 > Number used as Latches: 6 > Number of 4 input LUTs: 956 out of 1,920 49% >Logic Distribution: > Number of occupied Slices: 959 out of >960 99% > Number of Slices containing only related logic: 959 out of >959 100% > Number of Slices containing unrelated logic: 0 out of >959 0% > *See NOTES below for an explanation of the effects of unrelated >logic >Total Number of 4 input LUTs: 1,910 out of 1,920 99% > Number used as logic: 956 > Number used as a route-thru: 181 > Number used for Dual Port RAMs: 768 > (Two LUTs used per Dual Port RAM) > Number used as Shift registers: 5 > Number of bonded IOBs: 93 out of 108 86% > IOB Flip Flops: 19 > Number of Block RAMs: 4 out of 4 100% > Number of GCLKs: 9 out of 24 37% > Number of DCMs: 2 out of 2 100% > >Another thing. How to reduce the area usage?? Almost half the LUTs are used as dual port rams. Perhaps an inefficient FIFO for audio/D channel? I'd use boundary crossing registers instead of a FIFO. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 144894
Philipp, http://www.xilinx.com/webpack/classics/wpclassic/ AustinArticle: 144895
Philip wrote: > Hi all, > > I was just about to download the new Xilinx ISE 11.1 evaluation package. I am still using webpack 10.1.03. If I ever finish my home project I may upgrade...... webpack 10.1.03 does refer to Virtex2P which I think is what you are referring to. Older versions of software can be downloaded from here. http://www.xilinx.com/webpack/classics/wpclassic/ I don't know whether this is free or not. Try it and report back. Andy > However, I was told that the new Xilinx design suite does not support > Xilinx Virtex II Pro devices anymore. Does anyone have an idea where I > could get hold of an old version (Xilinx ISE 10.1.03) of this package > from the web since I need to synthesize the design for a Virtex II Pro > board. > > Many thanks, > PhilippArticle: 144896
>>Hi, >>when i do post route simulation i get a bunch of error similar to the >>following > >> ** Error: >>F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( >>negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849 >ps, >>520 ps ); >># Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_4 > > >> who can tell me how to correct these errors?? >> >>--------------------------------------- >>This message was sent using the comp.arch.fpga web interface on >>http://www.FPGARelated.com >> > >This error tells you that when you remove your reset signal that the flip >flops see it 520 ps before the next rising edge of the clock and that this >is not enough time if you wanted to change the flops value on that first >clock. You need to redesign your reset distribution to ensure that it meets >timing. >thanks for your reply ,i have set the rst==1 in "initialize inputs" in my test.v .but there are aslo two errors . # .main_pane.signals.interior.cs # ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(113485): $hold( negedge CLK:447545 ps, negedge I &&& in_clk_enable1:447552 ps, 118 ps ); # Time: 447552 ps Iteration: 1 Instance: /test_v/uut/yuv_addr_1_1 # ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(113485): $hold( negedge CLK:863545 ps, negedge I &&& in_clk_enable1:863552 ps, 118 ps ); # Time: 863552 ps Iteration: 1 Instance: /test_v/uut/yuv_addr_1_1 ??????? > > >--------------------------------------- >This message was sent using the comp.arch.fpga web interface on >http://www.FPGARelated.com > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144897
In article <57bd01b2-0d7c-48dd-a925-521eb206fef2@q4g2000yqm.googlegroups.com>, Test01 <cpandya@yahoo.com> writes: >Thanks for getting back to me so basically if the device behind the >end-point does not respond to the cycle then I can simply have a code >that does normal PCIe completion cycle with data as ffff_ffff to match >the data size. Can I not issue completer abort or some other abort >mechanism in such a case? This particular case is not within my >control as the device resides behind the FPGA (PCIe endpoint). You CAN try an abort, but then you have to test and debug another case. What do you mean by "not within my control"? If you know something is broken enough to issue an abort, then you know you could supply dummy data. All I was trying to say is that aborts in the middle of things like cache-read-block seem like asking for troubles. Why go there? Just give it some dummy data instead. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 144898
Dear Veterans,
I have a design for FPGA whose top module includes 15 vhdl modules
a flexible user/client block that interacts with these blocks . I do
not have the source code for the user block. I just have the inputs
and outputs of this block. I instantiated user block as a black box in
my design. We want to integrate user block into my design without
interchanging the source code from both sides. However, the issue is
that "the synthesis should be done in client's side" and I have the
top module. It should be in a way that once I send the files I am
done. To the client, I want to supply the synthesized version of the
code which client will work for 6 months or so on their user block.
During this time, I will not bother generation of a programming file
for them. I want to make sure they have all the necessary files in
this period.
questions
1- Is there a way other than sending my top module and other 15 edifs
to the client.
2- Is it possible for me to insert client's block as a black box, make
a synthesis and send this file with the ucf file to the client and
make sure that client can integrate his user block and can work
further and generate a programming file.
3- Do I have to make a new top module that has two blocks. One of
this block is my previous top module the other is the user block? I
will put all inputs and outputs of user block to my previous top
module's inputs and outputs in a way that that user block
functionality stays the same.
I prefer 2,3,1. I hope option 2 is aplicable.
I am using Xilinx 9.1.03i, XST,VHDL
Article: 144899I'm not sure where this thread started, I don't see a message before Nico's post Jan 11. Did you post your code? Your design is using about 10% of the LUTs as routing, which does tend to happen when your LUT usage rises using up much of the routing resources. The main offender that I can see is the use of almost 50% of the LUTs as DP RAM. I am guessing that these are being used for FIFO buffers. Can you reduce the number of LUTs used for buffering or are they all required? As to the clocking issue, I don't know what the problem is exactly. Why can't you use the E1 clock? What pin is the E1 clock connected to on the S3 part? I would hope it is connected to a DCM or at least a clock input. It is hard to suggest much more without more insight into what your design is doing. Rick On Jan 12, 9:00=A0am, Morppheu <jdemam...@gmail.com> wrote: > > Why use the internal clock? Isn't the MT9076 free running when it > > doesn't see a line-sync? > > Yes, the MT goes free running when its not sinced. > But the MT9076 is a module on my hardware. I can mount the backplane > with or without the MT9076 chip. > That is the point, what to do when I have the E1 module installed. How > to interface with it. > My FPGA is an Spartan 3e S100 (almost 100% full): > > Logic Utilization: > =A0 Total Number Slice Registers: =A0 =A0 =A0 737 out of =A0 1,920 =A0 38= % > =A0 =A0 Number used as Flip Flops: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 73= 1 > =A0 =A0 Number used as Latches: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A06 > =A0 Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A0 =A0 956 out of =A0 1,920 = =A0 49% > Logic Distribution: > =A0 Number of occupied Slices: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0959 out of > 960 =A0 99% > =A0 =A0 Number of Slices containing only related logic: =A0 =A0 959 out o= f > 959 =A0100% > =A0 =A0 Number of Slices containing unrelated logic: =A0 =A0 =A0 =A0 =A00= out of > 959 =A0 =A00% > =A0 =A0 =A0 *See NOTES below for an explanation of the effects of unrelat= ed > logic > Total Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A01,910 out of =A0 1,920 = =A0 99% > =A0 Number used as logic: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0956 > =A0 Number used as a route-thru: =A0 =A0 =A0 =A0 181 > =A0 Number used for Dual Port RAMs: =A0 =A0 =A0768 > =A0 =A0 (Two LUTs used per Dual Port RAM) > =A0 Number used as Shift registers: =A0 =A0 =A0 =A05 > =A0 Number of bonded IOBs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 93 out of =A0 =A0 = 108 =A0 86% > =A0 =A0 IOB Flip Flops: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A019 > =A0 Number of Block RAMs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A04 out of =A0 =A0= =A0 4 =A0100% > =A0 Number of GCLKs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 9 out of =A0= =A0 =A024 =A0 37% > =A0 Number of DCMs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A02 out of = =A0 =A0 =A0 2 =A0100% > > Another thing. How to reduce the area usage?? > > Thanks!
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