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Messages from 145500

Article: 145500
Subject: Re: Test Post
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Fri, 12 Feb 2010 16:48:29 -0000
Links: << >>  << T >>  << A >>
> Google groups sees your post.  Also your thread is still showing
> up there.  It doesn't show your thread as new, but rather as a
> change in subject:
> Board layout for FPGA
> Discussion subject changed to "10 layer stack for 1152 pin BGA routing
> (and decoupling)?" by Nial Stewart


Oh aye, I thought I'd posted a new thread.

Must be working too hard!


Nial. 



Article: 145501
Subject: Re: Synplify out of memory
From: Mike Treseler <mtreseler@gmail.com>
Date: Fri, 12 Feb 2010 09:01:26 -0800
Links: << >>  << T >>  << A >>
Ben Gelb wrote:
> I have a really large lookup table (members of a finite field) encoded
> as a function. This function is only ever invoked with a constant
> argument, so it shouldn't actually be synthesized. Altera's synthesis
> tool seems to handle this with no problem.
> 
> When I try to use Synplify to synthesize my design (particularly this
> constant function), the verilog compiler (c_ver) runs out of memory
> (hits the 4GB limit).
...
> is there a better way to encode a large lookup table like that that
> should really only be used at elaboration time?

I would use Quartus or code the table as a block ROM.


         -- Mike Treseler

Article: 145502
Subject: Re: using an FPGA to emulate a vintage computer
From: "Charlie Gibbs" <cgibbs@kltpzyxm.invalid>
Date: Fri, 12 Feb 2010 09:36:11 -0800
Links: << >>  << T >>  << A >>
In article <7ti2brFp0aU2@mid.individual.net>, Huge@nowhere.much.invalid
(Huge) writes:

> On 2010-02-09, Charles Richmond <frizzle@tx.rr.com> wrote:
>
>> Charlie Gibbs wrote:
>>
>>> In article <1bd40ftplw.fsf@snowball.wb.pfeifferfamily.net>,
>>> pfeiffer@cs.nmsu.edu (Joe Pfeiffer) writes:
>>>
>>>> Al Kossow <aek@bitsavers.org> writes:
>>>>
>>>>> Reviving early computing dinosaurs from the surviving DNA is
>>>>> difficult.
>>>>
>>>> That's a line that deserves to be put above the entrance to a
>>>> computer museum.
>>>
>>> "It's a Unix system!  I know this!"  -- Jurassic Park
>>
>> http://www.youtube.com/watch?v=dFUlAQZB9Ng
>
> Another terrible moment in a deeply terrible movie.
>
> I wanted the dinosaurs to kill them all. And quickly.

You're as much of a curmudgeon as I am.  At the end of
"The Perfect Storm" (one of two movies for which I feel
thoroughly ripped off for the price of admission), my only
thought was: "Good riddance to those stupid people."
(Unfortunately, the screenwriters survived.)

-- 
/~\  cgibbs@kltpzyxm.invalid (Charlie Gibbs)
\ /  I'm really at ac.dekanfrus if you read it the right way.
 X   Top-posted messages will probably be ignored.  See RFC1855.
/ \  HTML will DEFINITELY be ignored.  Join the ASCII ribbon campaign!


Article: 145503
Subject: Re: Synplify out of memory
From: Ben Gelb <ben.gelb@gmail.com>
Date: Fri, 12 Feb 2010 09:39:05 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 11, 4:24=A0pm, rickman <gnu...@gmail.com> wrote:
> On Feb 11, 2:52=A0pm, Ben Gelb <ben.g...@gmail.com> wrote:
>
>
>
>
>
> > I have a really large lookup table (members of a finite field) encoded
> > as a function. This function is only ever invoked with a constant
> > argument, so it shouldn't actually be synthesized. Altera's synthesis
> > tool seems to handle this with no problem.
>
> > When I try to use Synplify to synthesize my design (particularly this
> > constant function), the verilog compiler (c_ver) runs out of memory
> > (hits the 4GB limit).
>
> > Seems like Synplify isn't figuring out that the function doesn't
> > actually need to be synthesized.
>
> > So I guess the question is two-fold:
>
> > 1. is there a better way to encode a large lookup table like that that
> > should really only be used at elaboration time?
> > 2. is it possible to enable c_ver to run in 64-bit mode, so that it
> > can go past the 4G boundary?
>
> When you say the function is only called with a constant argument, is
> it truly a constant in terms of the language? =A0Maybe if you are using
> a variable which is initialized to a value and not changed, this is
> not so well understood. =A0Otherwise, I can't think why the entire
> function would need to be "implemented" rather than just evaluated.
> Which language are you using?
>
> Rick

Hi Rick and all -

Thanks for the replies.

The function is being called with the index from a generate loop. It
does not need to be synthesized. As a comparison, if I build it in
Quartus, the memory usage never peaks higher than ~250MB.

Is there a better way to be doing this? I could probably remove the
generate loops, table and all and just script some Verilog
generation... but would prefer not having to go that route...

I am using Verilog 2001.

Ben

Article: 145504
Subject: Re: using an FPGA to emulate a vintage computer
From: Michael Wojcik <mwojcik@newsguy.com>
Date: Fri, 12 Feb 2010 12:46:51 -0500
Links: << >>  << T >>  << A >>
Huge wrote:
> 
> Another terrible moment in a deeply terrible movie.
> 
> I wanted the dinosaurs to kill them all. And quickly.

At least in _Jurassic Park_ you could root for the dinosaurs. _The
Matrix_ (my candidate for Most Overrated Movie Ever) didn't even have
that.

-- 
Michael Wojcik
Micro Focus
Rhetoric & Writing, Michigan State University

Article: 145505
Subject: Why is following Verilog code snipper considered a Latch
From: Test01 <cpandya@yahoo.com>
Date: Fri, 12 Feb 2010 10:51:20 -0800 (PST)
Links: << >>  << T >>  << A >>
I am not sure why the QuartusII synthesis tool is considering
ReqInFifoDataIn[72] a latch and not a flip-flop?  ReqInFifoData[72] is
clearly defined as part of synchronous always block.  It is getting
used by wTag signal - Here I am anding the D input of the Flip-Flop
and Qn output of the same D flip-flop.  The purpose of this is to
generate one clock wide wTag pulse.

 input [81:0] RxStreamData0,

 wire wTag = RxStreamData0[72] & ~ReqInFifoDataIn[72];

 always @(posedge AppClk or negedge PcieRstN) begin
   if (!PcieRstN) begin
    ReqInFifoDataIn <= 96'b0;
    ReqInFifoDataValid <= 1'b0;
    ReqInFifoDataVal <= 1'b0;
    end
   else begin
    ReqInFifoDataIn[81:0] <= RxStreamData0[81:0];
    ReqInFifoDataValid <= RxStreamValid0;
    ReqInFifoDataVal <= ReqInFifoRd;
    end
 end

Article: 145506
Subject: Re: using an FPGA to emulate a vintage computer
From: Eric Chomko <pne.chomko@comcast.net>
Date: Fri, 12 Feb 2010 12:19:47 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 12, 12:46=A0pm, Michael Wojcik <mwoj...@newsguy.com> wrote:
> Huge wrote:
>
> > Another terrible moment in a deeply terrible movie.
>
> > I wanted the dinosaurs to kill them all. And quickly.
>
> At least in _Jurassic Park_ you could root for the dinosaurs. _The
> Matrix_ (my candidate for Most Overrated Movie Ever) didn't even have
> that.
>

Yes, the Hugo Weaving character was as obnoxious as Neo and the
others...

> --
> Michael Wojcik
> Micro Focus
> Rhetoric & Writing, Michigan State University


Article: 145507
Subject: Re: Why is following Verilog code snipper considered a Latch
From: Gabor <gabor@alacron.com>
Date: Fri, 12 Feb 2010 12:38:35 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 12, 1:51=A0pm, Test01 <cpan...@yahoo.com> wrote:
> I am not sure why the QuartusII synthesis tool is considering
> ReqInFifoDataIn[72] a latch and not a flip-flop? =A0ReqInFifoData[72] is
> clearly defined as part of synchronous always block. =A0It is getting
> used by wTag signal - Here I am anding the D input of the Flip-Flop
> and Qn output of the same D flip-flop. =A0The purpose of this is to
> generate one clock wide wTag pulse.
>
> =A0input [81:0] RxStreamData0,
>
> =A0wire wTag =3D RxStreamData0[72] & ~ReqInFifoDataIn[72];
>
> =A0always @(posedge AppClk or negedge PcieRstN) begin
> =A0 =A0if (!PcieRstN) begin
> =A0 =A0 ReqInFifoDataIn <=3D 96'b0;
> =A0 =A0 ReqInFifoDataValid <=3D 1'b0;
> =A0 =A0 ReqInFifoDataVal <=3D 1'b0;
> =A0 =A0 end
> =A0 =A0else begin
> =A0 =A0 ReqInFifoDataIn[81:0] <=3D RxStreamData0[81:0];
> =A0 =A0 ReqInFifoDataValid <=3D RxStreamValid0;
> =A0 =A0 ReqInFifoDataVal <=3D ReqInFifoRd;
> =A0 =A0 end
> =A0end

I'm not that familiar with Quartus, but in Xilinx tools there
are often messages that reference "flip-flop/latch" which is
the cover-all-cases text to talk about a register.  The only
weird thing in your code is that RegInFifoDataIn would
appear to be 96 bits as evidenced by the reset term, but
only 82 bits are assigned in the clocked term.  That would
tend to make bits 82 and up "latches" but doesn't explain
the problem with bit 72.

Regards,
Gabor

Article: 145508
Subject: Re: Why is following Verilog code snipper considered a Latch
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 12 Feb 2010 22:06:26 +0000
Links: << >>  << T >>  << A >>
On Fri, 12 Feb 2010 10:51:20 -0800 (PST), Test01 <cpandya@yahoo.com>
wrote:

>I am not sure why the QuartusII synthesis tool is considering
>ReqInFifoDataIn[72] a latch and not a flip-flop?  

Hollow and self-mocking laughter.... This is an example
of the error I make more than any other when writing 
RTL code.

>ReqInFifoData[72] is
>clearly defined as part of synchronous always block. 

No, it's not!  You do NOT write to ReqInFifoData[75:82]
in the clocked (else) part of the always block; it's
only written in the reset branch.  The clocked branch
writes only to the lower 82 bits.

It probably doesn't matter; if you don't use those
extra bits, their flip-flops will be removed by
synthesis optimizations.
-- 
Jonathan Bromley

Article: 145509
Subject: Re: Why is following Verilog code snipper considered a Latch
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Fri, 12 Feb 2010 22:46:31 +0000 (UTC)
Links: << >>  << T >>  << A >>
Jonathan Bromley <jonathan.bromley@mycompany.com> wrote:
(snip, someone wrote)
 
>>ReqInFifoData[72] is
>>clearly defined as part of synchronous always block. 
 
> No, it's not!  You do NOT write to ReqInFifoData[75:82]
> in the clocked (else) part of the always block; it's
> only written in the reset branch.  The clocked branch
> writes only to the lower 82 bits.

The usual rule in other newgroups is to post the declarations
of the data along with the code.  As we don't know the width
of RegInFifoData it is hard to say.  It does seem likely to
be ore than 82, though.
 
> It probably doesn't matter; if you don't use those
> extra bits, their flip-flops will be removed by
> synthesis optimizations.

-- glen

Article: 145510
Subject: Re: Why is following Verilog code snipper considered a Latch
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 12 Feb 2010 22:57:01 +0000
Links: << >>  << T >>  << A >>
On Fri, 12 Feb 2010 22:46:31 +0000 (UTC), glen herrmannsfeldt wrote:

>The usual rule in other newgroups is to post the declarations
>of the data along with the code. 

A good plan, for sure.  Maybe a declaration would have
helped me to write "[95:82]", which is what I meant,
instead of "[75:82]", which is what I wrote...

> As we don't know the width
>of RegInFifoData it is hard to say.  It does seem likely to
>be more than 82, though.

I took the line
  ReqInFifoData <= 96'b0;
to be a sufficiently broad hint :-)
-- 
Jonathan Bromley

Article: 145511
Subject: Re: Why is following Verilog code snipper considered a Latch
From: Test01 <cpandya@yahoo.com>
Date: Fri, 12 Feb 2010 17:06:50 -0800 (PST)
Links: << >>  << T >>  << A >>
Thanks for all the replies as it helped resolve the issue.  I need to
be more precise in assignment statements.

Article: 145512
Subject: Re: VHDL vs Verilog
From: Symon <symon_brewer@hotmail.com>
Date: Sat, 13 Feb 2010 01:16:25 +0000
Links: << >>  << T >>  << A >>
On 2/13/2010 12:15 AM, whygee wrote:
> hi,
>
> recently I read a quote about VHDL vs Verilog,
> along the lines of "VHDL is made by SW people who
> don't understand HW and vice versa"...
>
> Does anybody know the exact wording and origin ?
>
> yg

FFS, don't we have enough wasted bandwidth bickering over bypass 
networks? Every hardware engineer _knows_ VHDL is better, but would 
rather kill their mother (if they knew who she was) than admit it. Now 
take your thinly disguised troll post and piss off...

...to comp.lang.vhdl where you will find polite software people. Ask for 
Jonathan, Mike and KJ. Tell them I sent you.

With special love, Syms. xx

p.s.

http://www.googlefight.com/index.php?lang=en_GB&word1=vhdl&word2=verilog


Article: 145513
Subject: Re: Test Post
From: Symon <symon_brewer@hotmail.com>
Date: Sat, 13 Feb 2010 02:04:41 +0000
Links: << >>  << T >>  << A >>
On 2/12/2010 4:48 PM, Nial Stewart wrote:
>> Google groups sees your post.  Also your thread is still showing
>> up there.  It doesn't show your thread as new, but rather as a
>> change in subject:
>> Board layout for FPGA
>> Discussion subject changed to "10 layer stack for 1152 pin BGA routing
>> (and decoupling)?" by Nial Stewart
>
>
> Oh aye, I thought I'd posted a new thread.
>
> Must be working too hard!
>
>
> Nial.
>
>

So, are you gonna repost? I've given up on that last thread, but I'm a 
glutton for religious wars, because when I win/martyr myself, my 
religion promises me a stripper factory and a beer volcano. It's gospel!

Anyway, perhaps when/if you do, you could make clear whether you are 
using a 1152 pin package because you want to use all the I/O or the 
reason is you need so much logic for your application that you need that 
big a package. Are you gonna use any gigabit stuff to the BGA? If so, 
what rate? What are you connecting the 1152 pin part to? Is the 1152 pin 
part an FPGA? How many supplies does the 1152 pin part need?  A power 
budget would be useful for each supply. What rise time are you shooting 
for on the I/O from this BGA? Nial, have you ever been in a Turkish 
prison? Is this board going to be sold? In a metal box? Does it need CE 
approval or somesuch? What are the PCB's dimensions, HxWxD? How much 
time/money have you got? What stackups have you used before? Do you do 
layout yourself?

Anyone who has to regularly cope with a big package, as is my burden, 
knows that these are important parameters.

Cheers then, Syms.

p.s. I nearly posted this with a typoed hereafter boast of a 'bee 
volcano'. Which would not be nearly as good! RAmen.



Article: 145514
Subject: Re: What is the basis on flip-flops replaced by a latch
From: Patrick Maupin <pmaupin@gmail.com>
Date: Fri, 12 Feb 2010 19:26:16 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 11, 8:33=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> In comp.arch.fpga Patrick Maupin <pmau...@gmail.com> wrote:
>
> > But (and this is a big but) FPGAs themselves (not just the design
> > tools) are designed for flop-based design, so if you use latch-based
> > designs with FPGAs you are not only stressing the timing tools, you
> > are also avoiding the nice, packaged, back-to-back dedicated latches
> > they give you called flops.
>
> Well, you could use a sequence of FF's, clocking on different clock
> edges, or the same edge of two clocks. =A0
>

I actually did this in Xilinx FPGAs back in 1999.  The specific
problem I was solving was an insufficient number of global clocks (a
lot of interconnects with source-based clocking).  Xilinx has
solutions for this now (regional clocks), but not back then.  So I
used regular interconnect for clocking, and that was very high skew,
so that you couldn't guarantee that the same edge was, in fact, the
same edge for all the flops on the clock.

The solution was to do as you said -- the inputs to every flop were
from flops clocked on the opposite edge.  That, and reducing the
amount of logic in that clock domain and clock-crossing to a "real"
clock domain as soon as possible.

Article: 145515
Subject: Re: What is the basis on flip-flops replaced by a latch
From: Patrick Maupin <pmaupin@gmail.com>
Date: Fri, 12 Feb 2010 19:35:32 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 12, 10:32=A0am, rickman <gnu...@gmail.com> wrote:

> In the case of using latches in place of registers, the speed gains
> are always usable. =A0But can't the same sort of gains be made by
> register leveling? =A0If you have logic that is slower than a clock
> cycle followed by logic that is faster than a clock cycle, why not
> just move some of the slow logic across the register to the faster
> logic section?

That's a similar technique, to be sure, for speed-gains.  But as I
wrote in an earlier post, I think the primary motivation for latch-
based design was originally cost.  For example, since each flop is
really two latches, if you are going to have logic which ANDs together
the output of two flops, you could replace that with ANDing the output
of two latches, and outputting that result through another latch, for
a net savings of 75% of the latches.


Article: 145516
Subject: Re: VHDL vs Verilog
From: rickman <gnuarm@gmail.com>
Date: Fri, 12 Feb 2010 20:47:07 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 12, 7:15=A0pm, whygee <y...@yg.yg> wrote:
> hi,
>
> recently I read a quote about VHDL vs Verilog,
> along the lines of "VHDL is made by SW people who
> don't understand HW and vice versa"...
>
> Does anybody know the exact wording and origin ?
>
> yg
> --http://ygdes.com/http://yasep.org

Just ignore the troll.  I'd like to get an answer to your question.

Rick

Article: 145517
Subject: Re: VHDL vs Verilog
From: KJ <kkjennings@sbcglobal.net>
Date: Fri, 12 Feb 2010 21:22:42 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 12, 8:16=A0pm, Symon <symon_bre...@hotmail.com> wrote:

> ...to comp.lang.vhdl where you will find polite software people. Ask for
> Jonathan, Mike and KJ. Tell them I sent you.
>

Ooooo...you read my posts and am on your recommended reading list
now!!!

KJ

Article: 145518
Subject: Re: VHDL vs Verilog
From: whygee <yg@yg.yg>
Date: Sat, 13 Feb 2010 06:25:13 +0100
Links: << >>  << T >>  << A >>
hi !

Symon wrote:
> FFS, don't we have enough wasted bandwidth bickering over bypass 
> networks? Every hardware engineer _knows_ VHDL is better, but would 
> rather kill their mother (if they knew who she was) than admit it.
I have no shame to admit that I like VHDL (well, it's more a love/hate
stuff, considering some aspects), but I know that Verilog
exists, and I accept that others like it instead. The phrase
that I partly remember summed up many things about the divergences
between these two major HDL.

> Now take your thinly disguised troll post and piss off...
it's not a troll, it's an informal research for a paper.
I just wanted to know where the humor I read somewhere (here ?)
comes from. Is it attributed ?

> ...to comp.lang.vhdl where you will find polite software people.
does THAT exist ?

> Ask for Jonathan, Mike and KJ. Tell them I sent you.
hehe :-) no thanks, I post here because FPGA are not
tied to one langage, so there are people here who know
both HDLs.

> With special love, Syms. xx
hmmm "special love" is for tomorrow, feb.14th :-)

> p.s.
> 
> http://www.googlefight.com/index.php?lang=en_GB&word1=vhdl&word2=verilog
well, that's not what I'm looking for.
thanks for the off-topic anyway :-)

yg
-- 
http://ygdes.com / http://yasep.org

Article: 145519
Subject: Re: VHDL vs Verilog
From: whygee <yg@yg.yg>
Date: Sat, 13 Feb 2010 06:29:20 +0100
Links: << >>  << T >>  << A >>
KJ wrote:
> On Feb 12, 8:16 pm, Symon <symon_bre...@hotmail.com> wrote:
>> ...to comp.lang.vhdl where you will find polite software people. Ask for
>> Jonathan, Mike and KJ. Tell them I sent you.
> Ooooo...you read my posts and am on your recommended reading list now!!!

I did not know that I would trigger so many strong reactions,
you know, it's just a reference check for a paper,
I have no intention to start a vi vs emacs^W^W^Wnother
pointless flamewar.

regards,

> KJ
yg

-- 
http://ygdes.com / http://yasep.org

Article: 145520
Subject: Re: What is the basis on flip-flops replaced by a latch
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Fri, 12 Feb 2010 23:01:49 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 12, 7:35=A0pm, Patrick Maupin <pmau...@gmail.com> wrote:
> On Feb 12, 10:32=A0am, rickman <gnu...@gmail.com> wrote:
>
> > In the case of using latches in place of registers, the speed gains
> > are always usable. =A0But can't the same sort of gains be made by
> > register leveling? =A0If you have logic that is slower than a clock
> > cycle followed by logic that is faster than a clock cycle, why not
> > just move some of the slow logic across the register to the faster
> > logic section?
>
> That's a similar technique, to be sure, for speed-gains. =A0But as I
> wrote in an earlier post, I think the primary motivation for latch-
> based design was originally cost. =A0For example, since each flop is
> really two latches, if you are going to have logic which ANDs together
> the output of two flops, you could replace that with ANDing the output
> of two latches, and outputting that result through another latch, for
> a net savings of 75% of the latches.

Your method's target and the target used by CPU designers inserting
latches in the pipeline line are totally different.

They use it because a combinational signal time delay is tool long to
fit within one clock cycle and too short within two clock cycles in a
pipeline, not in any places you may want to.

Weng

Article: 145521
Subject: Re: using an FPGA to emulate a vintage computer
From: Huge <Huge@nowhere.much.invalid>
Date: 13 Feb 2010 08:45:57 GMT
Links: << >>  << T >>  << A >>
On 2010-02-12, Charlie Gibbs <cgibbs@kltpzyxm.invalid> wrote:
> In article <7ti2brFp0aU2@mid.individual.net>, Huge@nowhere.much.invalid
> (Huge) writes:

>> I wanted the dinosaurs to kill them all. And quickly.
>
> You're as much of a curmudgeon as I am.  

Why, thank you!


-- 
                             219361311
       email me, if you must, at huge {at} huge (dot) org <dot> uk]

Article: 145522
Subject: Re: VHDL vs Verilog
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Sat, 13 Feb 2010 10:15:34 +0100
Links: << >>  << T >>  << A >>
whygee <yg@yg.yg> writes:

> Does anybody know the exact wording and origin ?

You mean this?

http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 145523
Subject: Re: VHDL vs Verilog
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sat, 13 Feb 2010 09:20:12 +0000
Links: << >>  << T >>  << A >>
On Sat, 13 Feb 2010 10:15:34 +0100, Petter Gustad
<newsmailcomp6@gustad.com> wrote:

>whygee <yg@yg.yg> writes:
>
>> Does anybody know the exact wording and origin ?
>
>You mean this?
>
>http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4

Right, that's it, but the epithet has been around far
longer than that post.
-- 
Jonathan Bromley
whose location in the three-dimensional space
  rude<->polite
  VHDL<->Veriiog
  software<->hardware
continues to vary strongly as a function of weather, 
my employer's demands, what's cool, and other factors.

Article: 145524
Subject: Re: VHDL vs Verilog
From: Eric Smith <spacewar@gmail.com>
Date: Sat, 13 Feb 2010 01:31:14 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 12, 4:15=A0pm, whygee <y...@yg.yg> wrote:
> recently I read a quote about VHDL vs Verilog,
> along the lines of "VHDL is made by SW people who
> don't understand HW and vice versa"...
>
> Does anybody know the exact wording and origin ?

That's a quote by someone who doesn't understand VHDL.



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