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I took a look at Synplify 5.08 on my system. If you select the 4000XL family, it has both XL and XLA devices listed, along with the HQ208 package. You can choose XL and any other package for synthesis. When going to place and route, select the correct part in the Xilinx software. Randy On 4 Feb 1999 19:44:28 GMT, kalavade@tesla.ho.lucent.com (Asawaree Kalavade) wrote: >Synplify/Xilinx4085XLA question > >I am running Synplify 5.06 and I need to target a Xilinx 4085XLA (208 QFP) >device. >I don't see the XLA series under technology. Is there a comparable >technology/part I could use? (There is no 208 package for 4085 XL.) > >What am I missing here? > >thanks, >asa >kalavade@bell-labs.comArticle: 14576
Hi, I'm working with Altera Max+Plus II 8.3 and simulated my AHDL-Code. I was able to avoid an error (wrong outpout for 1 clock period) by adding another FlipFlop. But in real, on my FLEX8000-Chip, the problem is still there. (spikes in PWM...) Does this mean that I can't trust the Simulator for signals < 1 clock period? Bye, LarsArticle: 14577
In article <78sq9h$ljj$1@news-1.news.gte.net>, BuckSavage <wbuckley@transdyn.com> wrote: >If the consequence is that data is processed in a manner to which >I am agreeable, then, by all means, it will be sufficient reason to use >qsort() in a non-standard way. > >Gaby, you are correct. Please make sure that any code you release is clearly described as following this philosophy. I would hate to try to run code written by someone who will do anything that seemed to produce plausible results in testing. -s -- Copyright 1999, All rights reserved. Peter Seebach / seebs@plethora.net C/Unix wizard, Pro-commerce radical, Spam fighter. Boycott Spamazon! Send me money - get cool programs and hardware! No commuting, please. Visit my new ISP <URL:http://www.plethora.net/> --- More Net, Less Spam!Article: 14578
In article <78t8v1$60t$1@news-1.news.gte.net>, BuckSavage <wbuckley@transdyn.com> wrote: >My view is that a programmer should have the ultimate choice in the >use of software, instead of having to "toe-the-line" in some fashion >expected by some other programmer. Software is a tool, and if it >can be used to solve some problem, then by all means use it so. Okay, so... What problem do you claim you are solving by declaring main incorrectly? -s -- Copyright 1999, All rights reserved. Peter Seebach / seebs@plethora.net C/Unix wizard, Pro-commerce radical, Spam fighter. Boycott Spamazon! Send me money - get cool programs and hardware! No commuting, please. Visit my new ISP <URL:http://www.plethora.net/> --- More Net, Less Spam!Article: 14579
Richard Iachetta wrote in message ... >In article <36b899be.0@news.usenetnews.org>, sales@celeritous.com says... >> When synthesized and mapped to a part it takes up some 29-30 CLBs. It >> appears >> to be synthesizing a 32 bit counter to accomplish this relatively simple >> task. I have >> tried all manner of synthesis and implementation options with little impact. >> (Yes I >> know doing it brute force in DOS without using the GUI interface would be >> more >> manly....) >> >> What "obvious-to-the-casual-observer" thing am I missing? > >Allen, > >An integer in VHDL is assumed to be 32-bits. You can constrain it by >defining a subtype that is an integer of range 0 to 3 for example to force >the compiler to only use 2 bits for the counter. However, I use SIGNED and >UNSIGNED variables for counters rather than integers to explicitly declare >the size of the counter. For example, > >signal Count : unsigned (0 to 1); -- 2 bit counter > >The other benefit of this is it its much easier (than with integers) to >pick off the bits of the counter. You can just say Count(0) and Count(1) >to reference the individual bits of the counter. > >For something this simple, you may be able to save gates by doing something >like this instead of using a counter: > >architecture oneshot_arch of oneshot is > >signal temp1, temp2, temp3 : std_logic; > >begin > > process (clk) > begin > if clk'event and clk = '1' then > temp1 <= trig; > temp2 <= temp1; > temp3 <= temp2; > end if; > end process; > > output <= (temp1 or temp2) and not temp3; > >Hope this helps. > >-- >Rich Iachetta >iachetta@us.ibm.com >I do not speak for IBM. Good solution... The only thing I would add is since trig is async, temp1 may show metastable behavior. Personally, I would add another flop and not use temp1 in the output function (but, that depends on what you do with 'output) bruceArticle: 14580
Hi, You can run this command, NGD2VHDL -w -tb input.NGA output.VHD Good luck, Qian C.C. ----------------------- E-mail: ccview@usa.net Shanghai Bell Co., Ltd. -----------------------Article: 14581
Thanks to all. With a slap to the forehead and resounding Doh! specifying the variable range did solve the problem. I am happy, let the debate rage on. A. Litton Hans Lindkvist wrote in message <36B9E10E.42842DE7@ldecs.ericsson.se>... Jamie Sanderson wrote: > This is just my opinion, so take it with a grain of salt... > > I never use variables when synthesizing hardware. My impression is that > people coming into VHDL from a software background use them, hardware types > don't. Variables are meaningless in hardware, everything's a signal. I could > be way off here, but I've yet to encounter a situation where using variables > was necessary. Yes, you're way off. It's mearly a matter of taste. This question pops up every now and then and never reaches to any other conclusion than it is a matter of taste. Regards Hans Lindkvist, M.Sc.and Lic.Tech in Comp.Eng. Senior Staff Engineer, Advanced Studies, Digital ASIC Research and Wideband Terminals Ericsson Mobile Communications AB Tel : Int+46 46 19 38 66 Scheelevägen 15 Fax : Int+46 46 19 34 55 S-221 83 LUND Email: Hans.Lindkvist@ldecs.ericsson.se SWEDENArticle: 14582
"Matthias D. Kistler" wrote: > Hi ! > > I am looking for the VHDL sources for a DES implementation suitable for > an FPGA. > I only need the encryption part, since the eventual goal is a in > implementaion of the UNIX crypt(3) Algorithm in an FPGA. > Any Help is greatly appreciated. > > Matt. Check out "Cracking DES: Secrets of Encryption Research, Wiretap Politics and Chip Design", Electronic Freedom Foundation, an O'Reilly & Associates book. ISBN 1-56952-520-3. There is also some (of my) source in VHDL on Mark Riordan's secure download site, ripem.msu.edu, there should be a copy of vhdl_des.tar.Z. An ftp get should require a non-anonymous login. I haven't heard of the archive getting out of the country, you might ask this gentleman if he was successful: > From usenet.ucs.indiana.edu!vixen.cso.uiuc.edu!howland.reston.ans.net!nntp.coast.net!news00.sunet.se!sunic!news99.sunet.se!nntp-trd.UNINETT.no!nntp.uio.no!Norway.EU.net!usenet Thu Feb 29 12:15:49 1996 > From: enholm@login.eunet.no (Morten Enholm) > Newsgroups: bionet.software > Subject: Help > Date: 29 Feb 1996 12:15:49 GMT > Organization: El Tempo Gigante > Lines: 7 > Message-ID: <4h45dl$65e@oslo-nntp.eunet.no> > NNTP-Posting-Host: pc8.horten-pm2-1.eunet.no > Mime-Version: 1.0 > Content-Type: Text/Plain; charset=US-ASCII > X-Newsreader: WinVN 0.99.7 > > Is ther a Frendly Person out her that can E-mail me a file > that is located at SCSS3.CL.MSU.edu/pub/crypt/des/VHDL_des.tar.z ??? > This Ftp site only let's people from the US in And i Live In Norway...... > Please Help > > Best Regs Morten >Article: 14583
Hi again
Thank you for your help. As in most cases the bug was on mine. Though it
is my opinion, that the compiler should produced an warning instead of
just removing signals from the netlist. I am sorry to have bothered you
with
this, I was just rather annoyed because I had this rather confusing help
twice from Xilinx hotline.
The real problem, that confused the compiler was that after modifying my
code in a totally unrelated part I had a signal, that was declared and used
twice, but never assigned value (what we in the "adjective" old schematic
days used to call a net without driver).
Hope that this piece of information will be able to help somebody in the
future.
Remember:
"You do not live long enough to make all the possible errors
in the world, so you have to learn from errors, others have
made for you"
Best regards
Lars
Lars Fomsgaard <lars_fomsgaard@danfoss.com> wrote in article
<01be502c$28a5f320$83e70b0a@w73131.drives.danfoss.dk>...
> Hi
>
> I have some problems with a design, that I can not make synthesize
properly
> in Xilinx Foundation
> (the code is listed belov). The problem is that the tool removes to
signals
> (swon and t16m)from the
> netlist and from the macro symbol.
>
> Basicly i have a counter (cur_cnt), that is reset whenever a certain
> condition is meet (t16m = '1'), and
> incremented whenever an rising edge occours on the signal swon.
>
> I have sent the design to Xilinx hotline, and their "VHDL-expert" claims
> that the problem is as follows:
>
> I assign the signal swon_d the value of swon, and after this (but in the
> same clocked process) I test
> wheater the condition (swon = '1' AND swon_d = '0') is meet, and this can
> never be the case, so the
> signals swon and t16m can be removed.
>
> I do not agree with this, and so I would like if someone could tell me if
I
> have completely misunderstood
> the principle of VHDL processes. And if someone else have experienced
> similar problems and knows
> a workaround.
>
> Thanks in advance
> Lars Fomsgaard
>
> sync :
> PROCESS (clk, RESET)
> BEGIN
> IF RESET = '1' THEN
> swon_d <= '0' ;
> cur_cnt <= (OTHERS => '0') ;
> -- Some additional lines removed as they
were
> related to other signals.
> ELSIF clk='1' AND clk'EVENT THEN
> swon_d <= swon ;
>
> IF t16m = '1' THEN --
> Counter for counting overcurrents.
> cur_cnt <= (OTHERS => '0') ;
> ELSIF swon = '1' AND swon_d = '0' THEN -- Xlinx
claims
> that this condition can never be meet.
> cur_cnt <= cur_cnt + "0001" ; -- as
> swon is equal to swon_d.
> END IF ;
> END IF;
> -- Some additional lines removed as they
were
> related to other signals.
> END PROCESS sync ;
>
>
Article: 14584Hi I agree with some of your points on synthesistools compared to schematic. However I do think that tests like the one previously mentioned in this thread is quite relevant. I have seen similar things on simple schematics, that I have tried to optimize just to ensure the buffering with increases in area of 30-50%, and my point is that if the optimizer can not handle the simple cases, how is it going to handle the big designs. After having seen this on the simple designs I started to carefully examine some of the less simple designs I found that here I had similar problems. Unfortunatly we never catch the tool in messing up the big designs, because they are to complex for us to cope with. But in the end it all comes down to chip size, and I do NOT want to pay 30% extra. Lars ems@riverside-machines.com.NOSPAM wrote in article <36b8d495.12902640@news.dial.pipex.com>... > I haven't had a chance to look at Don's data, but I'd like to ask a > question that seems to have been overlooked: is this a fair test? It > seems to me that this is somewhat like comparing a bicycle and a car > at traffic lights. > > From the description in the original post, and the fact that it > synthesises to ~40 CLBs, it seems obvious that this is pretty > straightforward hardware. It's a good bet that Don originally produced > a schematic that was close to optimal, and it's likely that most > people reading this could also produce a very efficient schematic. > > In other words, we're comparing a synthesiser against the best that > can be produced by a human, on a very limited problem. > > It may be possible to get a synthesiser to produce a description that > is as good as Don's schematic, but it's not very likely. If I had a > job to produce an optimal synthesised version of this circuit, I'm > sure that at least 90% of my time would be spent in examining the > resulting netlist or schematic, and messing with the synthesiser, the > constraints, and the source code. By the time I'd finished I could > almost certainly have produced an optimal schematic, or maybe two of > them. > > But, in the real world, people don't use HDLs to synthesise an optimal > 40-CLB design. If you want a realistic test, start with something that > requires 400, or 4,000, or 40,000 CLBs. A single human is going to > have a major problem producing an optimal design that contains 400 > random-logic CLBs (and it would be a brave person who claimed that > they could do even this better than a synthesiser, within a reasonable > timeframe), let alone 40,000 CLBs - *that's* why we use synthesisers. > If you've got a large design team and a lot of money, then sure, you > could get each of your engineers to spend a couple of months producing > their own optimal 400-CLB block. You might get a shock, of course, > when you try to verify your design, at which point you might start to > think about using.... > VHDL? Surely not. > > Evan > >Article: 14585
Actually I would too be very interested in any reply that you receive. In my humble opinion many companies are today looking att FPGA as a good alternative to ASIC, since they are getting faster, bigger and cheaper, so the trend is that they are to stay and to compete with ASIC. Only few companies are involved with ASIC-design today compared to the ones dealing with fpga, so I guess it is hard to say which one is more lucrative, but it sure takes a longer time to build up experience in ASIC, cause the design often has to undergo thorough verification and then ofcourse there are other aspects, like power and area. Sincerely Reza grcook@my-dejanews.com skrev i meddelandet <79bjo1$vf9$1@nnrp1.dejanews.com>... >Hi, > >The situation is that I have a choice of taking an ASIC design contract >(well, an extension actually) and possibly a Digital/FPGA contract with >the `possibility' of some ASIC work (both contracts are in the UK). > >Now, I would like to stay in ASIC and build up my experience there, but >the Digital/FPGA job is 5 minutes from where I live, as opposed to a >1 hour drive. Can anyone give me some advice as to the relative merits >of doing either contract ... my gut feeling is to stay as close to >ASIC as possible, as I believe it to be more lucrative, but need >convincing. > >Any help would be greatly appreciated ... and reply via email to take >this off the newsgroups if required. > >Cheers, > >Gary Cook. >Oxford, UK. > >-----------== Posted via Deja News, The Discussion Network ==---------- >http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14586
Lars Freund wrote: > > Hi, > > I'm working with Altera Max+Plus II 8.3 and simulated my AHDL-Code. I > was able to avoid an error (wrong outpout for 1 clock period) by adding > another FlipFlop. > > But in real, on my FLEX8000-Chip, the problem is still there. (spikes in > PWM...) > > Does this mean that I can't trust the Simulator for signals < 1 clock > period? > > Bye, > > Lars have you got the clock period in the simulator set to be the same as your real clock period? Normally it will default to something like 100ns, I think. JamesArticle: 14587
"Austin Franklin" <austin@dark9room.com> wrote: > Unless you either type REALLY fast, and make NO mistakes in your HDL, and > the tools behave right on (for the hour) AND the person you are competing > against with schematics draws them with stone and chisel, drinks heavily, > and bashes his/her thumb with the hammer, this just isn't how it's gonna > play out. And your 'cost reduction' can take from a lot more time to > never. Sure, you make fun of my design methodology now, but the next release of Stone and Chisel will support multiple chisel sizes. Then I'll be able to keep up with VHDL.Article: 14588
http://home-3.worldonline.nl/~696/index.htm eidlzskcujoufusdegkgtcqtopjvvlwhrtueiyzqdmbtfeszvixnzrqgtdilounldppuguyjcvezootbfqxttcoewftvcvgoypekookvedpogiyvpzzywnpbhrjckxfeonfygmnotfzmdtmxmfvdjhvmjisfigpuifhmfxmcfvzudcntgzcizrnxowofvenyrjcchdkwztiArticle: 14589
I just have to ask... Why is someone who works for Lucent using a Xilinx part in a design? Asawaree Kalavade wrote: > > Synplify/Xilinx4085XLA question > > I am running Synplify 5.06 and I need to target a Xilinx 4085XLA (208 QFP) > device. > I don't see the XLA series under technology. Is there a comparable > technology/part I could use? (There is no 208 package for 4085 XL.) > > What am I missing here? > > thanks, > asa > kalavade@bell-labs.com -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 14590
Did you do a timing simulation after the fitter or a functional simulation before synthesis? Lars Freund wrote: > > Hi, > > I'm working with Altera Max+Plus II 8.3 and simulated my AHDL-Code. I > was able to avoid an error (wrong outpout for 1 clock period) by adding > another FlipFlop. > > But in real, on my FLEX8000-Chip, the problem is still there. (spikes in > PWM...) -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 14591
Dave Fuhriman (dpf6@email.byu.edu) wrote:
: Hi, I've been researching reconfigurable computing for an article, and I
: have found some good explanations of how it works. What I lack is a
: solid analogy to give to other people to help them understand how it
: works and how it's an improvement over what we had before. Something
: like general purpose computing is like a Yugo, and reconfigurable
: computing like a 'Vette -- something that explains why it's better. Has
: anyone heard such an analogy that explains this concept to people like
: me who use computers but don't know how to make them? Any help would be
: appreciated. Thanks!
How about:
An ASIC is like a prima-donna / rock star / some other analogy??
- it just does what it was made to do, and doesn't take
instructions from anybody.
A reconfigurable computing system is like a soldier
- You tell it what to do, and it keeps doing that till you tell it
to do something different
A CPU is like a small child
- You have to tell it what to do continously...
And which one would you rather have working for you??
Best regards,
Alan Marshall
Article: 14592Hi, I'm using Lattice ISP Synario Starter Ver 5.1B, and is trying to make a bidirectional opendrain I/O pin on a ispLSI 2032V. (Have to, thanks to the limited number of OE product terms....) The Lattice documentation states that you can use the new open drain feature on the 2000V series on both outputs and bidirectional pins, but even after it compiles without errors, I can only do output, NOT input from the pin, so somehow it's being set as an output only pin. The ispDS fitter report also show it as an output pin. Have anybody seen this, or know how to do it ? Thanks, SorenArticle: 14593
James Kellar <james.kellar@nospamplease.quantel.com> wrote: > have you got the clock period in the simulator set to be the same as > your real clock period? Normally it will default to something like > 100ns, I think. yes, 100ns. And the error was after 15ns, so far away as the real clock will be 60ns. But there was another reason: I only simulated a part of the code (30% of LC's used) but in reality I had 95% LCs used... I added a FlipFlop to sychronize my AND-Gate and now it works. Thanks for your help, LarsArticle: 14594
Matthias D. Kistler (recomp@satie.ee.ethz.ch) wrote:
: Hi !
:
: I am looking for the VHDL sources for a DES implementation suitable for
: an FPGA.
: I only need the encryption part, since the eventual goal is a in
: implementaion of the UNIX crypt(3) Algorithm in an FPGA.
: Any Help is greatly appreciated.
Due to export rules, we can not give VHDL code out. However, we
studied DES on FPGAs in detail and our findings might be of
help. Here is an overview of our result:
encr. rate CLBs used chip
99Mbit/s 262 XC4008
184Mbit/s 433 XC4013
402Mbit/s 741 XC4028
The first one is a plain DES architecture, the other ones have two
and four pipeline stages, respectively. All designs were done using
a VHDL description.
For more details, please refer to our SAC '98 paper which
can be found as postscript file on our web site. Go to
http://ece.wpi.edu/Research/crypt
and click on the "Recent Publications" link.
Check also Jens-Peter Kaps' MS thesis which is on the web too.
Regards,
Christof
--
>>> WORKSHOP ON CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS (CHES) <<<
>>> WPI, August 12 & 13, 1999 <<<
>>> check http://ece.wpi.edu/Research/crypt/ches <<<
***********************************************************************
Christof Paar, Assistant Professor
Cryptography and Information Security (CRIS) Group
ECE Dept., WPI, 100 Institute Rd., Worcester, MA 01609, USA
fon: (508) 831 5061 email: christof@ece.wpi.edu
fax: (508) 831 5491 www: http://ee.wpi.edu/People/faculty/cxp.html
***********************************************************************
Article: 14595Complete FAQ at http://home-3.worldonline.nl/~696/index.htm jvosdovrzqgpbktenwwitdlddhrmwjjrxblkcqswhmvlopudmkbsttrtdnejnwrlngsgwksumvfhkfyvmeqfssjjldwqduwrbbjcvbkyiijzuhwsfxqqycyjurxhwipufdlwfrirrqinbbzemgcztbcecwiefpheudzngmzkikdtlpwoduzeksfezkbfgumfqrcxhpynyiuphfbjvilbeivtjvfikbtjlnqzogsmmykyuxbxmjlohypkxxtkwnpycguqkmvpocxshxjrtrzodvylmguiykomgnntbnvkbhlvckpbnvezxcmhumhbztfiuzwhumffrgyekmglnoyuxvqkshimevzvljxcxoolgpnqnjvfnllvmhzdxjxmvtmmzfpcsxjmozeetdxuifqzvodwhhczgrgqggzelreukdwqkzyqsmnghvndotwxrttszeArticle: 14596
As most of you know, I prefer schematics for the type of designs I am usually involved in (heavily data path, high data rate DSP designs). I think a few additions to the HDL tools would make them alot more attractive in cases like mine. See the problem is in many cases, I already know what the optimal subcircuit is and what its placement needs to be. I'd like to use that circuit as a macro in an HDL, which I can do now by instantiating it as a black box. That doesn't buy me much though. What I really need is to be able to use a generate to create a parameterizable macro including a hierarchical relative placement. For example, I might want to create a CORDIC block which consists of a pair of cross-coupled adder-subtractor chains. I know from past experience how it needs to be laid out to get the maximum performance and density. The algorithm for the placement is fairly simple. I can code it structurally in the HDL and put no-touch attributes on it so I get the logic I want, but now I have to go into the floorplanner everytime I use the macro (including on different designs) to lay it out. Then I find I need to increase the width by a bit and I have to start all over. If the HDL folks would just give me the ability to do this low level design AND HIERARCHICAL placement, it would make HDLs alot more attractive in applications like these. The overwhelming response from the vendors: That is not the spirit of synthesis. How 'bout it guys, it seems like the hooks are there to do this, and it certainly would not have to be used by those who don't think they need it. Don Husby wrote: > thor@sm.luth.se (Jonas Thor) wrote: > > On Fri, 29 Jan 1999 22:05:42 GMT, husby@fnal.gov (Don Husby) wrote: > > Does really the synthesizer provide any information about where to > > place the flip-flops? From my experience the synthesizer only produces > > a netlist with primitives or macros. Then it is up to the placer to > > place the primitives/macros. > > You're right. Apparently what happened is that Synpicity generated > "replicated logic" and so had two flip-flops per signal. The Lucent > mapper had to place both flip flops in separate blocks. Replicated > logic was clearly uncalled for here, since the fanout was only 2-3 > loads. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 14597
Hello
I've implemented a simple parallel to serial converter, but I had
some problems to synthesize it.
The idea is simple (see VHDL code bellow):
1 - When the signal CLK_LD_IN changes to '0', a new data (DATA_IN) is
loaded;
2 - When the signal CLK_SHIFT_IN changes to '1', the DATA_IN bits are
sent to DATA_OUT.
The two VHDL versions bellow were simulated (behavioural simulation)
without any problems. The first one generated the circuit wrong2.ps,
and the second one the circuit correct2.ps, that can be downloaded
from http://www.sussex.ac.uk/Users/tapu9/par2ser
What I want to know is why the synthesis tool doesn't understand the
elsif
in the version 1? and Why do I need to implement the tests for signal
transitions in two separated processes?
Many thanks
Eduardo.
P.S. I use Active-VHDL and Synplify.
--
-- Version 1: Simulation is ok, but has problems to synthesize
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
entity PAR2SER_HF is
port( CLK_LD_IN : in std_logic;
CLK_SHIFT_IN : in std_logic;
DATA_IN : in std_logic_vector( 7 downto 0 );
DATA_OUT : out std_logic
);
end PAR2SER_HF;
architecture PAR2SER_HF_BEH of PAR2SER_HF is
signal AUXIN : std_logic_vector( 7 downto 0 );
begin
PAR2SER_HF_PRO: process (CLK_LD_IN, CLK_SHIFT_IN)
begin
if CLK_LD_IN'event and CLK_LD_IN = '0' then -- Load new data
AUXIN <= DATA_IN;
elsif CLK_SHIFT_IN'event and CLK_SHIFT_IN = '1' then -- convert
and output data
AUXIN <= '0' & AUXIN(7 downto 1);
DATA_OUT <= AUXIN(0);
end if;
end process PAR2SER_HF_PRO;
end PAR2SER_HF_BEH;
--
-- Version 2: Simulation and synthesis are ok
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use work.SVAL_PKG.all;
entity PAR2SER_HF is
port( CLK_LD_IN : in std_logic;
CLK_SHIFT_IN : in std_logic;
DATA_IN : in std_logic_vector( 7 downto 0 );
DATA_OUT : out std_logic
);
end PAR2SER_HF;
architecture PAR2SER_HF_BEH of PAR2SER_HF is
signal AUXIN : std_logic_vector( 7 downto 0 );
signal AUXOUT : std_logic;
signal NEXT_STATE, FLAG1_NEXT, FLAG2_NEXT : STATES_TYP;
begin
DATA_OUT <= AUXOUT;
NEXT_STATE <= FLAG1_NEXT when CLK_LD_IN = '0' else
FLAG2_NEXT when CLK_SHIFT_IN = '1' else
NEXT_STATE;
PAR2SER_HF_PRO: process (CLK_LD_IN)
begin
if CLK_LD_IN'event and CLK_LD_IN = '0' then -- Load new data
AUXIN <= DATA_IN;
FLAG1_NEXT <= S1_C;
end if;
end process PAR2SER_HF_PRO;
process (CLK_SHIFT_IN)
begin
if CLK_SHIFT_IN'event and CLK_SHIFT_IN = '1' then -- convert and
output data
case NEXT_STATE is
when S1_C =>
AUXOUT <= AUXIN(0);
FLAG2_NEXT <= S2_C;
when S2_C =>
AUXOUT <= AUXIN(1);
FLAG2_NEXT <= S3_C;
when S3_C =>
AUXOUT <= AUXIN(2);
FLAG2_NEXT <= S4_C;
when S4_C =>
AUXOUT <= AUXIN(3);
FLAG2_NEXT <= S5_C;
when S5_C =>
AUXOUT <= AUXIN(4);
FLAG2_NEXT <= S6_C;
when S6_C =>
AUXOUT <= AUXIN(5);
FLAG2_NEXT <= S7_C;
when S7_C =>
AUXOUT <= AUXIN(6);
FLAG2_NEXT <= S8_C;
when S8_C =>
AUXOUT <= AUXIN(7);
FLAG2_NEXT <= S1_C;
when others =>
FLAG2_NEXT <= S1_C;
end case;
end if;
end process;
end PAR2SER_HF_BEH;
--
Eduardo Augusto Bezerra
e-mail: E.A.Bezerra@
sussex.ac.uk
Article: 14598Hello, I am using Xilinx's Design Manager M1.4.12. Can somebody explain to me the Place and Route Report output? Are there any other sources where I can get info on this output? (Should PAR be the sum of Place and Route or not?) Thank you in advance, Bill Balabanos balab@rice.edu ECE Dpt. Rice University 6100 Main Houston TX 77005 ---------------------------------------------------------------------------- -------------- Sample output: Total REAL time to Placer completion: 12 secs Total CPU time to Placer completion: 8 secs ... Total REAL time to Router completion: 17 secs Total CPU time to Router completion: 13 secs ... Total REAL time to PAR completion: 19 secs Total CPU time to PAR completion: 14 secsArticle: 14599
I've been doing exactly what you describe for the last two years, using Exemplar Leonardo, and I know other people are doing it too. I've posted on this issue before, as have other people. In fact, a few months back Evan from Riverside-machines posted the web address of some VHDL examples he created for Synplicity, with a short tutorial. Which vendors have you approached ?. I gather FPGA Express can't cope, due to poor old Synopsis only implementing a rather lame subset of the VHDL language. It is ridiculous for these features to only be available on high'ish-end Synthesis tools, when in fact no actual synthesis is involved. The tools don't need to understand much, just pass attributes through to the EDIF/XNF file. (though the ability to pass strings and booleans via Generics helps). My commiserations on having to use the floorplanner, anyway. ****** The floor is now open for people to step in and tell me I should be using schematics, even though I am completely happy with my approach, and happier still that other people (ie competitors) haven't cottoned on to its advantages. In article <36BB769C.6D41556E@ids.net>, Ray Andraka <randraka@ids.net> wrote >As most of you know, I prefer schematics for the type of designs I am >usually involved in (heavily data path, high data rate DSP designs). I >think a few additions to the HDL tools would make them alot more attractive >in cases like mine. See the problem is in many cases, I already know what >the optimal subcircuit is and what its placement needs to be. I'd like to >use that circuit as a macro in an HDL, which I can do now by instantiating >it as a black box. That doesn't buy me much though. What I really need is >to be able to use a generate to create a parameterizable macro including a >hierarchical relative placement. For example, I might want to create a >CORDIC block which consists of a pair of cross-coupled adder-subtractor >chains. I know from past experience how it needs to be laid out to get the >maximum performance and density. The algorithm for the placement is fairly >simple. I can code it structurally in the HDL and put no-touch attributes >on it so I get the logic I want, but now I have to go into the floorplanner >everytime I use the macro (including on different designs) to lay it out. >Then I find I need to increase the width by a bit and I have to start all >over. If the HDL folks would just give me the ability to do this low level >design AND HIERARCHICAL placement, it would make HDLs alot more attractive >in applications like these. The overwhelming response from the vendors: >That is not the spirit of synthesis. How 'bout it guys, it seems like the >hooks are there to do this, and it certainly would not have to be used by >those who don't think they need it. > >Don Husby wrote: > >> thor@sm.luth.se (Jonas Thor) wrote: >> > On Fri, 29 Jan 1999 22:05:42 GMT, husby@fnal.gov (Don Husby) wrote: >> > Does really the synthesizer provide any information about where to >> > place the flip-flops? From my experience the synthesizer only produces >> > a netlist with primitives or macros. Then it is up to the placer to >> > place the primitives/macros. >> >> You're right. Apparently what happened is that Synpicity generated >> "replicated logic" and so had two flip-flops per signal. The Lucent >> mapper had to place both flip flops in separate blocks. Replicated >> logic was clearly uncalled for here, since the fanout was only 2-3 >> loads. > > > >-- >-Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email randraka@ids.net >http://users.ids.net/~randraka > > -- Edward Moore
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