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On Apr 28, 11:55=A0am, Usama <usama...@gmail.com> wrote: > On Apr 28, 11:48=A0am, maverick <sheikh.m.far...@gmail.com> wrote: > > > > > On Apr 28, 11:24=A0am, Usama <usama...@gmail.com> wrote: > > > > On Apr 28, 2:41=A0am, d_s_klein <d_s_kl...@yahoo.com> wrote: > > > > > On Apr 27, 6:28=A0am, Usama <usama...@gmail.com> wrote: > > > > > > Hi, > > > > > > I am implementing BMD design as explained in xapp1052(v2.5). Have > > > > > implemented the design on AvnetV5LXT/SXT PCIe Development Board u= sing > > > > > the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 usin= g ISE > > > > > 10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am us= ing > > > > > to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am usin= g > > > > > only x1 lane of PCIe in my application. on both the machines i am > > > > > facing different problems. > > > > > > Problem on S5000XVN > > > > > =A0 =A0 =A0 =A0 =A0 =A0 on this machine i have 2 x4 slots and 1 x= 16 slot. wen i > > > > > plug in a card on the one of the x4 slot my application runs perf= ectly > > > > > fine but when i plug it on the other x4 slot the data which i get= is > > > > > not a valid data there is some garbage value shown in the data. W= hat > > > > > could b the problem over here? Any idea ? > > > > > > Problem on S3210SHLC > > > > > =A0 =A0 =A0 =A0 =A0 =A0on this machine i am facing the problem th= at when i plug in > > > > > one of Avnet V5LXT/SXT PCIe Development Board the computer detect= s the > > > > > cards. but i put any other Avnet V5LXT/SXT PCIe Development Board= the > > > > > system is unable to detect it. i don't understand this strange > > > > > behavior why is it showing such a behavior. dose anyone know the > > > > > solution to this problem > > > > > The PCIe link is not working, (probably) because the lane aggregati= on > > > > isn't happening properly. > > > > > Until you know enough about PCIe, and especially how lanes become > > > > links, no one will be able to help you. > > > > > RK > > > > Thanks for the reply RK, > > > I guess I was not very clear in the problem description. Let me try t= o > > > put more details and may be it will help others out to help me solve > > > this problem. > > > =A0I have three motherboards. > > > 1. D945GCCR =A0 (reference motherboard) > > > 2. S5000XVN > > > 3. S3210SHLC > > > > Th FPGA board that I have supports x8 mechanical connector. The Xilin= x > > > BMD design that I have implemented just uses single lane so actually > > > it is configured to operate in x1 mode. > > > > The S5000XVN motherboard has three PCIe slots. Two are with x8 > > > mechanical slots supporting x4 mode and the one is with x16 mechanica= l > > > slot supporting upto x16 mode. > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > > > Total =A0 =A0 =A0 =A0 =A0 Mechanical =A0 =A0 =A0 =A0 =A0 =A0 =A0Mode > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > > > 2 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 x4 > > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0x16 > > > > The x16 slot houses NVidia VGA card on the motherboard. So we are lef= t > > > with the remaining two slots. Theoretically, my BMD design should wor= k > > > on all these slots as it is supported both mechanically and mode wise > > > as well (only implemented x1 mode on the FPGA board). However, the > > > problems that I have mentioned remain the same. On this particular > > > motherboard, I get garbage data mixed with actual data. So I am able > > > to get expected data but there are few locations read out as garbage > > > values. Interestingly, when I use the same FPGA board on reference > > > machine with intel motherboard (D945GCCR) with x16 mechanical > > > connector supporting upto x16 mode, the same FPGA board behaves as > > > expected with NO garbage values. > > > > Now lets have a look at the second mother board which is S3210SHLC. > > > This particular motherboard has the following PCIe slots with > > > mechanical slots and lane modes supported. > > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > > > Total =A0 =A0 =A0 =A0 =A0 Mechanical =A0 =A0 =A0 =A0 =A0 =A0 =A0Mode > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 x4 > > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 x8 > > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 x8 > > > > On this particular motherboard, the behavior is totally different. I > > > have four identical Avnet FPGA boards, all loaded with the same > > > bitstreams. All these boards are successfully detected on S5000XVN > > > motherboard and on a reference motherboard but the strange thing abou= t > > > the subject motherboard (S3210SHLC) is, there is only one FPGA board > > > out of those four FPGA boards which gets detected on this motherboard= , > > > the rest of the FPGA boards are not detected on OS bootup. The other > > > problem which is common in this motherboard and the previous > > > motherboard is, when the same FPGA board is plugged into the x8 > > > mechanical slot supporting x4 lanes, I get garbage values coming out > > > of the FPGA along with actual data. But when plugged in x8 and x16 > > > mechanical slots supporting x8 modes on both the slots, the data is > > > read out perfectly. > > > > I have been able to establish one common thing in all these tests. Al= l > > > those PCIe slots which mechanically support x8 PCIe cards but > > > downgraded to support upto x4 lanes create problems. All those slots > > > which mechanically support x8 connector FPGA card and support x8 lane > > > mode works fine. The other FPGAs not getting detected and only one > > > getting detected is still confusing. > > > > I hope I am very clear this time in adding details and I am hopeful t= o > > > get more help on this. > > > > Thanks > > > UBA- Hide quoted text - > > > > - Show quoted text - > > > So if I summarize your motherboard problem having spitting garbage > > values and map it on the same table you provided, is this how it will > > look like? > > > S5000XVN motherboard > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > =A0Total =A0 =A0 =A0=A0 Mechanical =A0 =A0=A0Mode =A0 =A0 =A0 Test Rsul= ts > > =A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > =A02 =A0 =A0 =A0 =A0 =A0 =A0=A0 =A0 x8 =A0 =A0 =A0=A0 =A0 =A0 x4 =A0 = =A0 =A0 FAIL(garbage values) > > =A01 =A0 =A0 =A0 =A0 =A0 =A0=A0 =A0 x16 =A0 =A0 =A0 =A0 =A0=A0x16 =A0= =A0 =A0slot not available > > > S3210SHLC motherboard > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > =A0Total =A0 =A0 =A0 Mechanical =A0 =A0 =A0Mode =A0 =A0 =A0Test Rsults > > > =A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > =A0=A01 =A0 =A0 =A0 =A0 =A0=A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0=A0 x4 = =A0 =A0 =A0 FAIL(garbage values) > > > =A01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 = =A0 PASS > > =A01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0=A0 =A0 =A0 x8 =A0 =A0 = =A0 PASS > > > D945GCCR =A0 (reference motherboard) > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > =A0Total =A0 =A0 =A0 =A0 =A0 Mechanical =A0 =A0 =A0 =A0 =A0Mode =A0 =A0= =A0 =A0Test Rsults > > > =A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > =A01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0x16 =A0 =A0 =A0 =A0 =A0 PASS > > > maverick > > Thats absolutely right. > > The other problem is the unsuccessful detection of few Avnet FPGA > boards. > UBA We just carried out more tests regarding the problem in which we are unable to detect the FPGA boards on one particular motherboard. We took out three signals from the BMD design onto the Avnet board LEDs. 1. trn_lnk_up_n 2. trn_reset_n 3. sys_rst_n We observed the following behaviour: PCIe Slot 1 (x8 mechanical, x4 electrical): On system boot up, sys_rst_n and trn_reset_n are asserted and then deasserted. The trn_lnk_up is also asserted (active low) showing successful link establishment. Board is detected on this slot by the OS. PCIe Slot 2 (x8 mechanical, x8 electrical): On system boot up, sys_rst_n and trn_reset_n are asserted. sys_rst_n is deasserted but trn_reset_n kept asserted. The trn_lnk_up does not get asserted, obviously because of trn_reset_n still asserted. Board is not detected on this slot by the OS. PCIe Slot 3 (x16 mechanical, x8 electrical): On system boot up, sys_rst_n and trn_reset_n are asserted. sys_rst_n is deasserted but trn_reset_n kept asserted. The trn_lnk_up does not get asserted, obviously because of trn_reset_n still asserted. Board is not detected on this slot by the OS. We tried changing the jumper on JP5 to show the lane width but it did not help out as well (BTW should it help?). The other problem is somehow related to the slot which is electrically downgraded than the mechanical slot provided e.g. problem on a PCIe slot with x8 mechanical and x4 electrical. We have verified the same behavior on the two motherboards and whenever we plug in the FPGA board with different electrical and mechanical specs(only happens with x4 electrical and x8 mechanical slots), the problem of getting garbage data (or misalligned data !! so that it appears as if it is a garbage) happens. Anything to do with setting the DMA TLP size? At the same time, when we plug the same FPGA board on a PCIe slot with x8 electrical and x16 mechanical the problem disappears and things work perfectly fine (may be the board supports x8 mode so does the slot !). UBAArticle: 147476
>I've been trying out the Icarus Verilog compiler/simulator. It >looks nice so far. Any views on it? > >Also, it claims that it can generate code to load onto real >FPGA's. Can it really do that? Has anyone tried it? I'm >interested in Altera devices. > I tried its VPI (c interface) and it works well. I put my work on: http://bknpk.no-ip.biz/my_web/IP_STACK/sync_wr_VPI_memory.html --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147477
Brian Drummond wrote:
> Where there are combinatorial outputs to be described, I agree, I'll
> describe them outside the main process.
>
> But I can't remember the last time I had one so complex it needed a
> process of its own.
In my code, multiplexers (e.g. a number of registers driving the same bus)
end up as process of their own. It is possible to get around that by using
a wire array, though, so
always @*
begin
bus_data = 0;
if(bus_enable)
case(bus_addr)
0: bus_data = xxx;
1: bus_data = yyy;
...
15: bus_data = zzz;
esac
end
converts to
wire [x:0] bus_data_array [0:15];
assign bus_data_array[0] = xxx;
assign bus_data_array[1] = yyy;
...
assign bus_data_array[15] = zzz;
assign bus_data = bus_enable ? bus_data_array[bus_addr] : 0;
but this has a severe simulation disadvantage (the simulator has to
recalculate all bus_data_array elements when the dependencies change, even
when the bus is not used at all).
--
Bernd Paysan
"If you want it done right, you have to do it yourself!"
http://www.jwdt.com/~paysan/
Article: 147478
On Apr 28, 5:56=A0am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> then you must surely allow similar expressions with other enumerations,
> for instance:
> ---------------------------------
> Type NTSC_Color is (red, green, blue); =A0
> Signal Channel_Color : NTSC_Color;
> Signal Channel_Gain =A0: real;
>
> Channel_Gain <=3D Channel_Color ? 0.11 : 0.55 : 0.34; =A0
> -- nice and compact, but descending order to remain compatible with Boole=
an
> ---------------------------------
>
> Now I believe that ascending order, like every other positional list in t=
he
> language (port lists, argument lists, etc), would be less surprising:
>
> Channel_Gain <=3D Channel_Color ? 0.34 : 0.55 : 0.11; =A0
The problem with this approach is that the action depends not only on
the enumerated values defined in the type, but also on their order of
definition. Especially when the type is often defined in a package,
not immediately visible to the user/reviewer, I would much prefer a
more explicit (yes, verbose!) coding of what action is desired. Using
an array indexed by the enumerated type, or using the aforementioned
function, we can do this already, without the conditional operator
(I'm probably in the minority, but this was not a wise addition to the
language in 2008).
By adding such ambiguous shortcut features to the language, we are
only deterring the use of a universally accepted solution to code
complexity: subprograms (functions and/or procedures).
Consistently inconsistent here too...
BTW, WRT combinatorial outputs of clocked processes, many synthesis
tools now support the following:
process (clk, rst) is
variable myvar : ...
begin
if rst then
myvar :=3D ...
elsif rising_edge(clk) then
myvar :=3D myfunc(inputs);
end if;
combout <=3D outfunc(myvar);
end process;
Combout is then the combinatorial output of outfunc() applied to the
output of the register inferred by the access to myvar.
This gives us the ability to describe combinatorial output logic
without the simulation penalty, latches, and signal overhead
associated with a separate combinatorial process, implied or explicit.
Andy
Article: 147479On Apr 28, 3:03=A0am, Antti <antti.luk...@googlemail.com> wrote: > http://press.xilinx.com/phoenix.zhtml?c=3D212763&p=3Dirol-newsArticle&ID= =3D... > > years and years of talk, now going public :) > > Antti Could someone translate this from Marketing into Tech? Is this a hard- core ARM that will appear in the V7? Thanks, StephenArticle: 147480
Stephen, Yes. (Sorry, I am not in Marketing, but I think you are more likely to believe me regardless...) Oh, and we don't know if it will be called "V7." As soon as an engineer names a product, Marketing changes the name (so it is 'bad luck' to name anything until it is officially named by the Marketing folks. Who knows, maybe "7" is an unlucky number in Argentina...naming things is a really convoluted, and an art. AustinArticle: 147481
Thank you very much for your replies - they are very helpful!Article: 147482
On Apr 28, 4:58=A0am, Usama <usama...@gmail.com> wrote: > On Apr 28, 11:55=A0am, Usama <usama...@gmail.com> wrote: > > > > > On Apr 28, 11:48=A0am, maverick <sheikh.m.far...@gmail.com> wrote: > > > > On Apr 28, 11:24=A0am, Usama <usama...@gmail.com> wrote: > > > > > On Apr 28, 2:41=A0am, d_s_klein <d_s_kl...@yahoo.com> wrote: > > > > > > On Apr 27, 6:28=A0am, Usama <usama...@gmail.com> wrote: > > > > > > > Hi, > > > > > > > I am implementing BMD design as explained in xapp1052(v2.5). Ha= ve > > > > > > implemented the design on AvnetV5LXT/SXT PCIe Development Board= using > > > > > > the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 us= ing ISE > > > > > > 10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am = using > > > > > > to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am us= ing > > > > > > only x1 lane of PCIe in my application. on both the machines i = am > > > > > > facing different problems. > > > > > > > Problem on S5000XVN > > > > > > =A0 =A0 =A0 =A0 =A0 =A0 on this machine i have 2 x4 slots and 1= x16 slot. wen i > > > > > > plug in a card on the one of the x4 slot my application runs pe= rfectly > > > > > > fine but when i plug it on the other x4 slot the data which i g= et is > > > > > > not a valid data there is some garbage value shown in the data.= What > > > > > > could b the problem over here? Any idea ? > > > > > > > Problem on S3210SHLC > > > > > > =A0 =A0 =A0 =A0 =A0 =A0on this machine i am facing the problem = that when i plug in > > > > > > one of Avnet V5LXT/SXT PCIe Development Board the computer dete= cts the > > > > > > cards. but i put any other Avnet V5LXT/SXT PCIe Development Boa= rd the > > > > > > system is unable to detect it. i don't understand this strange > > > > > > behavior why is it showing such a behavior. dose anyone know th= e > > > > > > solution to this problem > > > > > > The PCIe link is not working, (probably) because the lane aggrega= tion > > > > > isn't happening properly. > > > > > > Until you know enough about PCIe, and especially how lanes become > > > > > links, no one will be able to help you. > > > > > > RK > > > > > Thanks for the reply RK, > > > > I guess I was not very clear in the problem description. Let me try= to > > > > put more details and may be it will help others out to help me solv= e > > > > this problem. > > > > =A0I have three motherboards. > > > > 1. D945GCCR =A0 (reference motherboard) > > > > 2. S5000XVN > > > > 3. S3210SHLC > > > > > Th FPGA board that I have supports x8 mechanical connector. The Xil= inx > > > > BMD design that I have implemented just uses single lane so actuall= y > > > > it is configured to operate in x1 mode. > > > > > The S5000XVN motherboard has three PCIe slots. Two are with x8 > > > > mechanical slots supporting x4 mode and the one is with x16 mechani= cal > > > > slot supporting upto x16 mode. > > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > > Total =A0 =A0 =A0 =A0 =A0 Mechanical =A0 =A0 =A0 =A0 =A0 =A0 =A0Mod= e > > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > > 2 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 x4 > > > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0x16 > > > > > The x16 slot houses NVidia VGA card on the motherboard. So we are l= eft > > > > with the remaining two slots. Theoretically, my BMD design should w= ork > > > > on all these slots as it is supported both mechanically and mode wi= se > > > > as well (only implemented x1 mode on the FPGA board). However, the > > > > problems that I have mentioned remain the same. On this particular > > > > motherboard, I get garbage data mixed with actual data. So I am abl= e > > > > to get expected data but there are few locations read out as garbag= e > > > > values. Interestingly, when I use the same FPGA board on reference > > > > machine with intel motherboard (D945GCCR) with x16 mechanical > > > > connector supporting upto x16 mode, the same FPGA board behaves as > > > > expected with NO garbage values. > > > > > Now lets have a look at the second mother board which is S3210SHLC. > > > > This particular motherboard has the following PCIe slots with > > > > mechanical slots and lane modes supported. > > > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > > Total =A0 =A0 =A0 =A0 =A0 Mechanical =A0 =A0 =A0 =A0 =A0 =A0 =A0Mod= e > > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 x4 > > > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 > > > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 x8 > > > > > On this particular motherboard, the behavior is totally different. = I > > > > have four identical Avnet FPGA boards, all loaded with the same > > > > bitstreams. All these boards are successfully detected on S5000XVN > > > > motherboard and on a reference motherboard but the strange thing ab= out > > > > the subject motherboard (S3210SHLC) is, there is only one FPGA boar= d > > > > out of those four FPGA boards which gets detected on this motherboa= rd, > > > > the rest of the FPGA boards are not detected on OS bootup. The othe= r > > > > problem which is common in this motherboard and the previous > > > > motherboard is, when the same FPGA board is plugged into the x8 > > > > mechanical slot supporting x4 lanes, I get garbage values coming ou= t > > > > of the FPGA along with actual data. But when plugged in x8 and x16 > > > > mechanical slots supporting x8 modes on both the slots, the data is > > > > read out perfectly. > > > > > I have been able to establish one common thing in all these tests. = All > > > > those PCIe slots which mechanically support x8 PCIe cards but > > > > downgraded to support upto x4 lanes create problems. All those slot= s > > > > which mechanically support x8 connector FPGA card and support x8 la= ne > > > > mode works fine. The other FPGAs not getting detected and only one > > > > getting detected is still confusing. > > > > > I hope I am very clear this time in adding details and I am hopeful= to > > > > get more help on this. > > > > > Thanks > > > > UBA- Hide quoted text - > > > > > - Show quoted text - > > > > So if I summarize your motherboard problem having spitting garbage > > > values and map it on the same table you provided, is this how it will > > > look like? > > > > S5000XVN motherboard > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > =A0Total =A0 =A0 =A0=A0 Mechanical =A0 =A0=A0Mode =A0 =A0 =A0 Test Rs= ults > > > =A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > =A02 =A0 =A0 =A0 =A0 =A0 =A0=A0 =A0 x8 =A0 =A0 =A0=A0 =A0 =A0 x4 =A0 = =A0 =A0 FAIL(garbage values) > > > =A01 =A0 =A0 =A0 =A0 =A0 =A0=A0 =A0 x16 =A0 =A0 =A0 =A0 =A0=A0x16 =A0= =A0 =A0slot not available > > > > S3210SHLC motherboard > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > =A0Total =A0 =A0 =A0 Mechanical =A0 =A0 =A0Mode =A0 =A0 =A0Test Rsult= s > > > > =A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > =A0=A01 =A0 =A0 =A0 =A0 =A0=A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0=A0 x4= =A0 =A0 =A0 FAIL(garbage values) > > > > =A01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 = =A0 =A0 PASS > > > =A01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0=A0 =A0 =A0 x8 =A0 = =A0 =A0 PASS > > > > D945GCCR =A0 (reference motherboard) > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > =A0Total =A0 =A0 =A0 =A0 =A0 Mechanical =A0 =A0 =A0 =A0 =A0Mode =A0 = =A0 =A0 =A0Test Rsults > > > > =A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > =A01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0x16 =A0 =A0 =A0 =A0 =A0 PASS > > > > maverick > > > Thats absolutely right. > > > The other problem is the unsuccessful detection of few Avnet FPGA > > boards. > > UBA > > We just carried out more tests regarding the problem in which we are > unable to detect the FPGA boards on one particular motherboard. We > took out three signals from the BMD design onto the Avnet board LEDs. > > 1. trn_lnk_up_n > 2. trn_reset_n > 3. sys_rst_n > > We observed the following behaviour: > PCIe Slot 1 (x8 mechanical, x4 electrical): On system boot up, > sys_rst_n and trn_reset_n are asserted and then deasserted. The > trn_lnk_up is also asserted (active low) > showing successful link establishment. Board is detected on this slot > by the OS. > > PCIe Slot 2 (x8 mechanical, x8 electrical): On system boot up, > sys_rst_n and trn_reset_n are asserted. sys_rst_n is deasserted but > trn_reset_n kept asserted. The trn_lnk_up =A0does not get asserted, > obviously because of trn_reset_n still asserted. Board is not detected > on this slot by the OS. > > PCIe Slot 3 (x16 mechanical, x8 electrical): On system boot up, > sys_rst_n and trn_reset_n are asserted. sys_rst_n is deasserted but > trn_reset_n kept asserted. The trn_lnk_up =A0does not get asserted, > obviously because of trn_reset_n still asserted. Board is not detected > on this slot by the OS. > > We tried changing the jumper on JP5 to show the lane width but it did > not help out as well (BTW should it help?). > > The other problem is somehow related to the slot which is electrically > downgraded than the mechanical slot provided e.g. problem on a PCIe > slot with x8 mechanical and x4 electrical. We have verified the same > behavior on the two motherboards and whenever we plug in the FPGA > board with different electrical and mechanical specs(only happens with > x4 electrical and x8 mechanical slots), the problem of getting garbage > data (or misalligned data !! so that it appears as if it is a garbage) > happens. Anything to do with setting the DMA TLP size? At the same > time, when we plug the same FPGA board on a PCIe slot with x8 > electrical and x16 mechanical the problem disappears and things work > perfectly fine (may be the board supports x8 mode so does the slot !). > > UBA You still need to understand the *whole* link/lane "stuff" during initialization. The problem is staring you in the face, telling you that! Start with how lane presence is detected. Work up to link aggregation from there. Miss-aligned data would not be from DMA TLP size. You have a lot of reading to do. RKArticle: 147483
Presently there is no easy way to measure the time difference between two markers. You need to display all markers and manually calculate the time difference. Until an easy delta time difference option is supported the following script can help. Also there is no easy way to add multiple cursors which are constant time step apart from the very last marker. http://bknpk.no-ip.biz/my_web/netlistConversion/gtkWaveMarkerAdd.html http://bknpk.no-ip.biz/my_web/netlistConversion/gtkWaveMarkerTimeDelta.html enjoy --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147484
>Hi, >Is anyone aware of a design controlling the 'I2C_controller_core' from >www.opencores.org? I read very good review of this core, but it needs to be >controlled by either a state machine or a small processor. The current core >only works at the 'byte' level. > >I'd like to be able to tell it: write those 37 bytes to that slave >address...or read 48 bytes from that slave address... > >I thought I'd ask before starting to write the state machine! > >Thanks, >Diego > >--------------------------------------- >This message was sent using the comp.arch.fpga web interface on >http://www.FPGARelated.com > this night be interesting to you This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter is done in order to test the core and its new APB interface with LEON processor. LEON is written in VHDL therefor the core's VHDL RTL design is tested. The core also contains a test bench and simulation model for I2C slave, written in VERILOG. From the VERILOG test bench only the initialization procedure is taken and the I2C slave model is translated to VHDL. http://bknpk.no-ip.biz/my_web/I2C/leon_2.html --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147485
On 4/28/2010 3:53 PM, austin wrote: > Stephen, > > Yes. > > (Sorry, I am not in Marketing, but I think you are more likely to > believe me regardless...) > > Oh, and we don't know if it will be called "V7." > > As soon as an engineer names a product, Marketing changes the name (so > it is 'bad luck' to name anything until it is officially named by the > Marketing folks. Who knows, maybe "7" is an unlucky number in > Argentina...naming things is a really convoluted, and an art. > > Austin > I wonder what will happen if Apple buy ARM? http://www.thisislondon.co.uk/standard-business/article-23826703-city-aflame-with-takeover-talk-of-arm-and-xstrata.do “A deal would make a lot of sense for Apple,” said one trader. “That way, they could stop ARM's technology from ending up in everyone else's computers and gadgets.” Syms.Article: 147486
"Symon" <symon_brewer@hotmail.com> wrote in message news:hr9nai$9rp$1@news.eternal-september.org... > I wonder what will happen if Apple buy ARM? There would be an interesting symmetry to that. IIRC the original ARM (by Acorn RISC Machines) owed quite a bit of its architecture to the 6502 used in the BBC micro (and also in early Apples).Article: 147487
On Apr 28, 4:25=A0am, Berk <berkgura...@gmail.com> wrote: > On 27 Nisan, 17:31, Bryan <bryan.fletc...@avnet.com> wrote: > > > Although based on an older version of ISE and MIG, you may find the > > MIG designs posted by Avnet to be helpful. > > >www.em.avnet.com/spartan3a-dsp--> Support Files & Downloads. > > > Bryan > > Thanks for the responses guys. I have come across very interesting > problems. > > @Gabor: I checked the pad report and I saw that wrong pins were being > assigned for use. (ie: In the UCF file, NET "N5" is used, but the pad > report uses a different pin and not N5) I don't know why this happens. > Is there something wrong with timing constraints, etc? I have no idea! > > @RCIngham: I don't have any of the software mentioned on that thread. > I am just trying to use, Xilinx ISIM (ISE Simulator), but I'm having > trouble because it doesn't launch. > > @Bryan: I checked those designs, keeping in mind that I could use the > UCF file. However, those designs use DCM and differential clock, so > the UCF files are different. I tried using the UCF file from the Avnet > design on my project, but as I mentioned before, in the pad report > different pins are being used! > > Overall, I think the problem is with the UCF file. If your pinout doesn't match the UCF file, I would suggest two things: 1) look at the place and route report to see if it is reporting 100% LOCed IOB's. This is near the top of the report and should be right after the number of IOB's used by the design. If not, you should check the UCF to be sure the net names match the design. 2) if it looks like the UCF is being ignored, I have found that cleaning up the project files can sometimes help this. The ISE project keeps some precompiled bits & pieces in an attempt to save time when re-building. My experience has been that the overall time savings is negligible, both with respect to the overall project build time, and especially with respect to the additional time and aggravation tracing down stuff like this. HTH, GaborArticle: 147488
On Wed, 28 Apr 2010 17:21:33 +0100, Symon <symon_brewer@hotmail.com> wrote: >I wonder what will happen if Apple buy ARM? > >http://www.thisislondon.co.uk/standard-business/article-23826703-city-aflame-with-takeover-talk-of-arm-and-xstrata.do > >“A deal would make a lot of sense for Apple,” said one trader. “That >way, they could stop ARM's technology from ending up in everyone else's >computers and gadgets.” The agreements signed before the acquisition survive the acquisition and if the licensees had any legal sense, there would be a clause which states if the new owner couldn't support the licensees, they would get a full rights perpetual license (in case ARM went bankrupt and/or got acquired by someone who doesn't want to support the license business anymore) -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 147489
Symon <symon_brewer@hotmail.com> wrote: >On 4/28/2010 3:53 PM, austin wrote: >> Stephen, >> >> Yes. >> >> (Sorry, I am not in Marketing, but I think you are more likely to >> believe me regardless...) >> >> Oh, and we don't know if it will be called "V7." >> >> As soon as an engineer names a product, Marketing changes the name (so >> it is 'bad luck' to name anything until it is officially named by the >> Marketing folks. Who knows, maybe "7" is an unlucky number in >> Argentina...naming things is a really convoluted, and an art. >> >> Austin >> >I wonder what will happen if Apple buy ARM? > >http://www.thisislondon.co.uk/standard-business/article-23826703-city-aflame-with-takeover-talk-of-arm-and-xstrata.do > >“A deal would make a lot of sense for Apple,” said one trader. “That >way, they could stop ARM's technology from ending up in everyone else's >computers and gadgets.” Apple buying ARM makes no sense at all. Why bother if you can get a license for almost nothing. What Apple wants at this moment is to be able to design their own SoCs for a tighter fit to their wishes in order to reduce power consumption. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 147490
austin <austin@xilinx.com> wrote: >Stephen, > >Yes. > >(Sorry, I am not in Marketing, but I think you are more likely to >believe me regardless...) Austin, Pleeeeeaase have lunch with marketing tomorrow and convince them to get a cortex-M3 or cortex-M0 in a Spartan! -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 147491
Nico, How many will you buy? How many will everyone buy? Putting anything in an FPGA device has to be backed by 1+ billion ($) in 2+ years for the family ... or I can't even afford to get a water glass at the table in the marketing restaurant. Mask sets at 22nm, and development costs, are completely out of this world. We may be making a FPGA device that can be programmed to do what you want, but we still have to serve the broadest market possible, so we can afford to do it at all, and still make a profit (reasonable ROI). Imagine putting something in the FPGA device, and getting it wrong...it could damage the company so severely that we could lose out on one, or more technology cycles to our competition. Tough world out there! The only reason why I enjoy the semi business at all is that I was in the telecom business for 20+ years, and that was so horrible that it (still) makes this look like a fun, exciting, and rewarding business to be in. I can't even imagine how grim the telecom business must be today. Of course, it doesn't hurt to work for one of the "best in class" semi fabless firms. AustinArticle: 147492
On Wed, 28 Apr 2010 07:02:00 -0700 (PDT), Andy <jonesandy@comcast.net> wrote: >On Apr 28, 5:56 am, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> Channel_Gain <= Channel_Color ? 0.11 : 0.55 : 0.34; >> -- nice and compact, but descending order to remain compatible with Boolean >> --------------------------------- >> >> Now I believe that ascending order, like every other positional list in the >> language (port lists, argument lists, etc), would be less surprising: >> >> Channel_Gain <= Channel_Color ? 0.34 : 0.55 : 0.11; > >The problem with this approach is that the action depends not only on >the enumerated values defined in the type, but also on their order of >definition. Especially when the type is often defined in a package, >not immediately visible to the user/reviewer, I would much prefer a >more explicit (yes, verbose!) coding of what action is desired. I agree; that's why I also suggested an associative version (snipped here) which I would prefer in practice. But that might not be a selling point to those who think VHDL too verbose! >By adding such ambiguous shortcut features to the language, we are >only deterring the use of a universally accepted solution to code >complexity: subprograms (functions and/or procedures). Exactly. >Consistently inconsistent here too... > >BTW, WRT combinatorial outputs of clocked processes, many synthesis >tools now support the following: > >process (clk, rst) is > variable myvar : ... >begin > if rst then > myvar := ... > elsif rising_edge(clk) then > myvar := myfunc(inputs); > end if; > combout <= outfunc(myvar); >end process; > >Combout is then the combinatorial output of outfunc() applied to the >output of the register inferred by the access to myvar. Neat. And with variables for parameters, it probably doesn't suffer from XST's longstanding bug passing signals as parameters to procedures. - Brian.Article: 147493
> @Bryan: I checked those designs, keeping in mind that I could use the > UCF file. However, those designs use DCM and differential clock, so > the UCF files are different. I tried using the UCF file from the Avnet > design on my project, but as I mentioned before, in the pad report > different pins are being used! > > Overall, I think the problem is with the UCF file. Use the UCF that comes with the "> S3A1800DSP DDR2 MIG Simplified Verilog User Logic" archive. It has a single-ended clock, LOC-ed to site F13, which matches the 1800A board. That design was hardware tested on an 1800A board, so the UCF is correct. The default pinout from MIG does not match the 1800A board. However, the 1800A board pinout is considered MIG-compliant -- meaning it adheres to all the rules required for the MIG-generated controller. The UCF has to be manually updated to match the board, including Pin Locations as well as some Slice locations. The UCF that I mention above has already had this manual editing performed, as well as having the Verilog user logic code modified with more consistent variable naming and comments. BryanArticle: 147494
On Wed, 28 Apr 2010 14:29:47 +0200, Bernd Paysan <bernd.paysan@gmx.de> wrote: >Brian Drummond wrote: > >> Where there are combinatorial outputs to be described, I agree, I'll >> describe them outside the main process. >> >> But I can't remember the last time I had one so complex it needed a >> process of its own. > >In my code, multiplexers (e.g. a number of registers driving the same bus) >end up as process of their own. I *think* I see why you do that, but I can't see the need for the array, just one intermediate signal. Then your process becomes (assuming suitable declarations) ------------------------------------------------------------------- with bus_addr select bus_data_internal <= xxx when 0, yyy when 1, ... zzz when others; bus_data <= bus_data_internal when bus_enable else 0; ------------------------------------------------------------------- - BrianArticle: 147495
On Wed, 28 Apr 2010 10:04:48 -0700 (PDT), Gabor <gabor@alacron.com> wrote: >On Apr 28, 4:25 am, Berk <berkgura...@gmail.com> wrote: >> Overall, I think the problem is with the UCF file. > >If your pinout doesn't match the UCF file, I would suggest two >things: > >1) look at the place and route report to see if it is reporting >100% LOCed IOB's. This is near the top of the report and should be >right after the number of IOB's used by the design. If not, you >should check the UCF to be sure the net names match the design. > >2) if it looks like the UCF is being ignored, I have found that >cleaning up the project files can sometimes help this. The ISE >project keeps some precompiled bits & pieces in an attempt to >save time when re-building. My experience has been that the >overall time savings is negligible, both with respect to the >overall project build time, and especially with respect to the >additional time and aggravation tracing down stuff like this. > Also check the "Translate" report (.bld file). Sometimes NGDbuild has its own reasons for rejecting a constraint, either because of a clash with another constraint, or some other reason (some constraints are apparently case-sensitive, and some signal names seem to get translated into lower-case during synthesis!) - BrianArticle: 147496
austin wrote: > Tough world out there! The only reason why I enjoy the semi business > at all is that I was in the telecom business for 20+ years, and that > was so horrible that it (still) makes this look like a fun, exciting, > and rewarding business to be in. I can't even imagine how grim the > telecom business must be today. Just ask Motorola! JonArticle: 147497
Nico Coesel wrote: > Austin, > Pleeeeeaase have lunch with marketing tomorrow and convince them to > get a cortex-M3 or cortex-M0 in a Spartan! Nico, you're asking for troubles ! Noone should let the marketing dept. create a product on a napkin, Austin should ask the real engineers ;-) yg -- http://ygdes.com / http://yasep.orgArticle: 147498
That is one long reply... On Apr 28, 6:56 am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Tue, 27 Apr 2010 15:56:57 -0700 (PDT), rickman <gnu...@gmail.com> wrote: > >On Apr 27, 6:05 am, Brian Drummond <brian_drumm...@btconnect.com> > >wrote: > >I don't agree that the two process model is inherently less > >desirable. Or maybe I should say that I don't think describing > >combinatorial logic outside of clocked processes is inherently less > >desirable. > > Where there are combinatorial outputs to be described, I agree, I'll describe > them outside the main process. No, I am talking about logic that drives the registers. For example, I have a PLL circuit which has a few registers, but several adders and a few shift operations (mult/div). I give each a separate concurrent statement to facilitate debugging. I could put it all inside the register process, but I can do things with signals I can't do with variables, such as bring them to the outside world. By giving each one a separate concurrent assignment it is very easy to monitor and debug each one individually. Yeah, it may look more verbose, but I just don't see that as a problem. The control signals for the registers get evaluated in concurrent logic. I could add more conditionals (ifs) to the clocked process to incorporate the full expression as the enable on the register, but by keeping it external, it is more clear what the evaluation is doing and again, I have a separate signal I can more easily debug it in the simulator and in the chip. Maybe this is a reflection of how we think differently for both design and debug. I am an old school hardware designer and I think in terms of registers and logic blocks. So my design reflects that I guess. > But I can't remember the last time I had one so complex it needed a process of > its own. > > > I seldom put a lot of combinatorial logic in processes, > >clocked or unclocked, mainly because the structures in processes and > >combinatorial logic are rather weighty (a synonym for verbose I > >guess). But it always depends on the logic. Lacking the conditional > >expression, VHDL concurrent logic can be a PITB to write complex > >expressions in a clear manner. This means sometimes I put > >combinatorial in unclocked processes because it is more clear. Simple > >logic goes in with the clocked process, but when possible, I put > >combinatorial logic in concurrent statements. > > I think you are referring to the ?: conditional operator inherited from C? Yes, Verilog and C I believe. > I just use VHDL's conditional signal assignments for that purpose. As it's > purely combinational, I have never found the need for an equivalent that I can > use inside a process. Heck, that is very limited. You can't even use in inside of a separate signal assignment. Try combining the conditional signal assignment with anything else. I would like to be able to use it inside the conditional for an if (sometimes) or combine it is ways that allows the assignment to more directly state the logic of the problem rather than my having to convert the logic to suit the flow of the structure. > I eventually figured out what I heartily detest about that (?:) - it's the ONE > construct across all the languages I've encountered that expects the list of > choices in descending order. > > (And does so implicitly as opposed to explicitly, with a "downto" or "step -1" > or "when true else..." or some visible indication that it's doing something > quaint) > > If VHDL is to adopt a conditional operator I hope it can do better than that! > Something less surprising, and generalisable to other discrete types or at least > other enums. > > If you are going to allow > --------------------------------- > Signal Flag : Boolean := True; > Signal Int_val : Integer; > > Int_val <= Flag?1:0; > --------------------------------- > then you must surely allow similar expressions with other enumerations, > for instance: > --------------------------------- > Type NTSC_Color is (red, green, blue); > Signal Channel_Color : NTSC_Color; > Signal Channel_Gain : real; > > Channel_Gain <= Channel_Color ? 0.11 : 0.55 : 0.34; > -- nice and compact, but descending order to remain compatible with Boolean > --------------------------------- I think this is a rather trivial example. Why not use the selected signal assignment? It may be more verbose, but it *is* explicit. The mnemonic for a boolean conditional operator is pretty simple, it is the same as an IF statement. But to extrapolate that to descending order for other data types is a bit of a reach. I guess this makes some sense for an enumerated type, but where else could you use the conditional operator? An integer range type would be a possible use, but potentially difficult to use effectively, or maybe I should say, seldom useful. I think the utility of the conditional operator is that it can be used in many places and allows a better expression of the logic (closer to the problem) as well as more compact. > Now I believe that ascending order, like every other positional list in the > language (port lists, argument lists, etc), would be less surprising: > > Channel_Gain <= Channel_Color ? 0.34 : 0.55 : 0.11; > > There would of course be an associative form of the expression > Channel_Gain <= Channel_Color ? red =>0.34 : green =>0.55 : blue=>0.11; > to make the bugs harder to bury. Isn't this just a selected signal assignment? > In this context, is anyone still happy with the C-compatible version? > > However... > > in today's VHDL, if I ever needed ?: I would resort to a trivial function, and > replace > > Int_val <= Flag?1:0; > with > Int_val <= cond(Flag,1,0); > or even > Int_val <= cond( test=>Flag, T=>1, F=>0 ); > > YMMV but for the sake of keeping the language relatively free of warts, I don't > mind typing six extra characters. > > It's precisely that wart-free-ness that lets you extend it (e.g. by adding > functions) in simple ways that actually work, instead of frustrating you. I don't get why you think the conditional operator would be a wart. It is just an operator. It is a trinary operator rather than uniary or binary, but it is still an operator and would violate nothing about VHDL. > And it's precisely the remaining warts that limit the ability to extend it > further. For example, the closed set of operators (a wart shared with most > not-quite-object-oriented languages like C++) stops you naming the > above function "?:" and writing > Int_val <= "?:"( Flag,1, 0 ); > to look that little bit more like Verilog or C. > > Or a better example: if you allowed types as generics, as Ada does, you could > write the "?:" function once and use it to return different types. (Newer > versions of C++ have this, as the template). > > >A foolish consistency is the hobgoblin of little minds, but there are > >times when consistency is a good thing in engineering, other times > >not. I guess I'm consistently inconsistent. > > Oh I'm inconsistent too, just not consistently so. > > I like "consistently inconsistent" - I suspect it would make the best > description of the underlying design principles of C. > (I don't know Verilog at all well, so won't extend the same courtesy to it!) I've been warned about verilog, mostly in this thread, and I've been told once I try it I won't go back. We'll see later this summer... maybe. RickArticle: 147499
On 4/28/2010 6:11 PM, Muzaffer Kal wrote: > On Wed, 28 Apr 2010 17:21:33 +0100, Symon<symon_brewer@hotmail.com> > wrote: >> I wonder what will happen if Apple buy ARM? >> >> http://www.thisislondon.co.uk/standard-business/article-23826703-city-aflame-with-takeover-talk-of-arm-and-xstrata.do >> >> “A deal would make a lot of sense for Apple,” said one trader. “That >> way, they could stop ARM's technology from ending up in everyone else's >> computers and gadgets.” > > The agreements signed before the acquisition survive the acquisition > and if the licensees had any legal sense, there would be a clause > which states if the new owner couldn't support the licensees, they > would get a full rights perpetual license (in case ARM went bankrupt > and/or got acquired by someone who doesn't want to support the license > business anymore) Wow, we have a lawyer posting. On CAF, no less. Can I claim my first amendment rights if I use hyperbole on you? Or will you use Justice Eady on me?
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