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Messages from 14750

Article: 14750
Subject: Re: Problems with Xilinx F1.5 & latchs
From: ems@riverside-machines.com.NOSPAM
Date: Sun, 14 Feb 1999 22:51:52 GMT
Links: << >>  << T >>  << A >>
On Fri, 12 Feb 1999 20:38:33 +0100, Tximo <jgracia@disca.upv.es>
wrote:

your first problem is that 'load' has both an async reset and an async
preset on it:

>       if reset='1' then
>          load <= '0';
>       elsif bus_libre='1' then
>          load <= '1';

since 4K's don't have a f/f with both a preset and a reset, the
synthesiser will complain. the only fix is to recode for the correct
f/f.

>Warning: Latch inferred in design 'generar_stuff_bis' read with
>'hdlin_check_no_latch' (HDL-307)
>
>My problems are that I am not using any latch, I don't know how to
>access 'hdlin_check_no_latch' variable, and I don't know
>the use of the inferred latch.

you don't want to turn this variable off. it provides very useful
(probably the most useful) error checking you can get. try to find out
which signal the latch is on - this should be in the report somewhere.

some possible coding problems leading to latches:

1) combinatorial code, incomplete if's - not the problem here
2) multiple drivers on a signal - a common problem, reported by
synopsys as a latch
3) check your clocked processes. make sure that the clock edge
detection is in the last elsif branch. if you have any further
lower-priority branches, then you may get latches (in this case you're
asking for hardware that responds to a clock edge, but which also does
something, at a lower priority, when there's no clock edge).
4) maybe the problem on 'load' above is giving you the latch error?

evan

Article: 14751
Subject: Re: Xilinx de-compiler
From: Achim Gratz <gratz@ite.inf.tu-dresden.de>
Date: 15 Feb 1999 12:16:55 +0100
Links: << >>  << T >>  << A >>
timolmst@cyberramp.net writes:

> I may be wrong, but I believe that Orcad Express has a function to
> read an XNF file in, and generate VHDL from it. It's been awhile since
> I had that package loaded, but that's what I seem to remember. Don't
> know how complex a design it can handle. I do know that Orcad Express
> can import ABEl and turn it into VHDL.

XNF - Xilinx Netlist File
XNF != Bitstream


Achim Gratz.

--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW:    http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone:  +49 351 463 - 8325
Article: 14752
Subject: xnf de-compiler
From: "Sergio A. Cuenca Asensi" <sergio@dtic.ua.es>
Date: Mon, 15 Feb 1999 12:42:54 +0100
Links: << >>  << T >>  << A >>
Hello
somebody knows any tool to get a schematic from a xnf netlist?. I am
using FPGA Express  in a digital design course and
this tool could be very useful for my students (and for me).
Thanks

--
===================================================================
Sergio A. Cuenca Asensi
Dept. Tecnologia Informatica y Computacion (TIC)
Escuela Politecnica Superior, Campus de San Vicente
Universidad de Alicante
Ap. Correos 99, E-03080 ALICANTE
ESPAŅA (SPAIN)
email   : sergio@dtic.ua.es
Phone : +34 96 590 39 34
Fax     : +34 96 590 39 02
===================================================================


Article: 14753
Subject: Xilinx Spartan and pin-locking
From: sja@world.std.com (Stuart J Adams)
Date: Mon, 15 Feb 1999 15:11:04 GMT
Links: << >>  << T >>  << A >>
Anyone have any experience with how pin-locking
friendly the SpartanXL series is. We are
a spinning up a board with an XCS05XL on it and 
have not done the FPGA design for it yet. In the
past we have used Altera 6K and 10K and not had nay
problems droping in a design after the board is
finished.

Thanks,
  Stuart

Article: 14754
Subject: Re: comp.arch.fpga Archives
From: Markus Wannemacher <markus.wannemacher@fernuni-hagen.de>
Date: Mon, 15 Feb 1999 16:13:57 +0100
Links: << >>  << T >>  << A >>
"T. Franklin" schrieb:
> 
> Where can I find the archives for this newsgroup?

http://www.fernuni-hagen.de/IT/FPGA/news    Feb. 1997 - now
http://www.dejanews.com                     April 1995 - now
ftp://www.super.org/pub/www/FPGA/caf.html   Juli 1994 - August 1996
  (wrong links, be sure to stay on ftp://www.super.org/pub/www/FPGA/)

Markus Wannemacher

Article: 14755
Subject: FPGA array computers
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Mon, 15 Feb 1999 09:53:18 -0800
Links: << >>  << T >>  << A >>
Greg Pfister wrote in message <36C5D127.2096E5F7@usNOSPAM.ibm.com>...
>Anybody wanna bet that this sucker is SIMD?

If it is an array of FPGAs, it can be SIMD one moment, MIMD another, and
zero-instruction-multiple data (parallel hardwired datapaths) the next.  Or
a hybrid, a SIMD or MIMD where each datapath also has problem specific
function units.  See www.optimagic.com/research.html for links to some
FPGA computing research.


How about some numbers?  What might one build from (say) 256 Xilinx XCV300
Virtex FPGAs, each of which has 32x48 4-bit configurable logic blocks + 16
256x16 dual-ported block SRAMs?  Let's consider some examples -- blue sky,
back of the envelope numbers based solely upon available FPGA resources.

(Disclaimers: I build homebrew FPGA RISC uniprocessors but my MP designs are
paper tigers.  Any numbers are approximate, best case, will not exceed,
peak numbers.  Actual numbers may underwhelm.  Machines may be very
difficult to program.  These design sketches may prove unroutable.  Etc.)


1. 0IMD (hardwired datapaths): array of 16-bit adders:
256 * 32*48*4 / 16 = 256 * 384 = 98000 adders at 100 MHz = 10e12 adds/s

array of 16-bit adders + 16-word reg files:
256 * 32*48*4 / 32  = 256 * 192 = 49000 adders at 100 MHz = 5e12 adds/s


2. SIMD: array of 16-bit datapaths.

Assume each 16-bit datapath has:
* 16 word register file
* add/sub, logic unit
* operand mux
* SIMD control logic (conditionally suppress result writeback, etc.)
* shared access to long-line operand/result broadcast bus
-----
8R*3C=24 Virtex CLBs

Assume 80% of FPGA area is datapath tiles and 20% is interconnect, memory
interface, and control.

256 * 32*48 / 24 * 0.8 = 16384 * 0.8 = 13000 datapaths at 50 MHz = 600e9
ops/s


3. MIMD: array of 32-bit RISC processors suitable for straightforward
targeting from a C or FORTRAN compiler:

Assume each 32-bit processor has:
* 4-stage pipeline (IF/RF/EX/WB)
* 16-bit instructions
* 2R-1W 16 word x 32-bit register file
* result forwarding (reg file bypass mux)
* immediate operand mux
* add/sub, logic unit, <<, >> 1, 4 (at least)
* PC, PC incrementer, relative branches, conditional branches
* jump, jump and link
* memory address mux and register
* pipelined control unit
* 32-entry x 8 halfword-line i-cache (e.g. 256 instruction L1 i-cache)
* no d-cache and no floating point
----
16R*8C CLBs = 128 CLBs, + 1 256x16 block RAM

This gives 8 processors per XCV300 and leaves 1/3 of chip area (32*16 CLBs)
and half the block RAMs free for memory interface and interconnect.

256 FPGAs * 8 CPUs/FPGA = 2000 32-bit processors at 50 MHz = 100e9 MIMD
32-bit ops/s

See also my old FPGA MP-on-chip discussion thread at
http://dejanews.com/getdoc.xp?AN=277216882.  (Note, CLBs there are the 2-bit
CLBs of the XC4000 family, not the 4-bit CLBs of the Virtex family.)


Other comments.

Interconnect?  Memory bandwidth?  Consider a hypothetical "XYZ" machine
using a simple 3D mesh of 16 boards of 4x4 XCV300s.  Give each FPGA 128 bits
of SDRAM -- 2 DIMM sockets w/ 64 MB each for a total of 256*2*64 MB = 32 GB.

Add a 17th XCV300+SDRAM per board for configuration and control.

Configure each FPGA with 6 (NSEWUD) 16-bit channels, for 400 MB/s/chan at
200 MHz.  (Virtex datasheet says 200 MHz chip-to-chip using "HSTL class IV"
signaling.)  The FPGA at (x,y,z) transmits E to (x+1,y,z), N to (x,y+1,z), U
to (x,y,z+1) and receives W from (x-1,y,z), S from (x,y-1,z) and D from
(x,y,z-1).  Assume the cross-board up/down channels only run at 50 MHz for
100 MB/s/chan.

Peak bisection bandwidth of 4*4*100MB/s = 1.6 GB/s "sliced between boards"
and 4*16*400 MB/s = 25 GB/s sliced vertically.

Peak external memory bandwidth of 256 * 128/8 * 100 MHz = 400 GB/s.  Peak
internal memory bandwidth to block RAMs = 256 FPGAs * 16 blocks * 2-ports *
2B/port * 100 MHz = 1.6 TB/s.

While these point-to-point meshes have excellent bandwidth, they have
relatively high latency and seem complex and expensive to implement if
communication is irregular.  For interconnecting a few hundred FPGAs in a
scalable shared memory MIMD, I prefer a simpler 2D or 3D meerkat-like
interconnect with multiple buses in the X, Y, and Z dimensions such that
FPGA at (x,y,z) interconnects to (*,y,z) on the X[y][z] bus, (x,*,z) on the
Y[x][z] bus, and (x,y,*) on the Z[x][y] bus.

(See "The Meerkat Multicomputer: Tradeoffs in Multicomputer Architecture",
Robert Bedichek Ph.D. thesis --
http://cag-www.lcs.mit.edu/~robertb/thesis.ps.)

Latency: For the MIMD sketched above, each processor has a local 256
halfword i-cache.  I-cache misses and all data accesses are from uncached
RAM.  Local references to uncached RAM access local SDRAM in < 100 ns, much
less if reference hits an open page.  Non-local load/store transactions
would issue through the interconnect to a distant FPGA.  Fortunately memory
latency is less of an issue when each processor is single issue and has a
slow 20 ns clock.

Cost?  The raw IC cost of this hypothetical machine is very approximately:

272 XCV300-4BG352C at $344 each per Avnet web site at quantity 25 discount
544 64MB (8Mx64) PC100 SDRAM DIMMs at $88 each per chip merchant.
-------
~$150,000

Jan Gray



Article: 14756
Subject: Re: M1 error message
From: Bob Sefton <rsefton@home.com>
Date: Mon, 15 Feb 1999 17:56:18 GMT
Links: << >>  << T >>  << A >>
Xilinx doesn't have an element called "DFF" that I know of. The
Xilinx name would be "FD" I think. It sure sounds to me like
you've got a library problem and ngdbuild doesn't recognize the
name "DFF". You can either fix the library or put a .xnf or .ngo
description of "DFF" in the directory where you're running the
Xilinx tools. If ngdbuild sees a file that tells it what "DFF" is
it will use it. Obviously it would be cleaner to fix the library.

Bob S.

Hamish Moffatt wrote:
> 
> Hamish Moffatt <hamish@rising.com.au> wrote:
> > Can somebody help me out with the following error message from M1.4's
> > NGDBUILD?
> 
> > Running Logical Design DRC...
> > ERROR:basnu:93 - logical block "cell_dln/overview/I$5576" of type "DFF" is
> >    unexpanded.
> 
> > I have approximately 400 of these :-)
> 
> So Xilinx's web site explains that this could be due to pin contention
> (nothing in the bld file about that) or missing library files (no
> complaints about that either). $XACT is set to the top of our
> M1.4 installation; $LCA is set to $XACT/mentor/data off the top of my
> head. Is there something else I need to set? I get this error about
> DFFs, AND3s, all sorts of stuff.
> 
> Having just spent about 7 hours porting a design from XACT 5.2 and XC4010
> (obselete libraries) to M1 and XC4028EX (unified libraries) (completely by
> hand) I am a bit frustrated!
> 
> thanks
> Hamish
> --
> Hamish Moffatt       Mobile: +61 412 011 176       hamish@rising.com.au
> 
> Rising Software Australia Pty. Ltd.
> Developers of music education software including Auralia & Musition.
> 31 Elmhurst Road, Blackburn, Victoria Australia, 3130
> Phone: +61 3 9894 4788  Fax: +61 3 9894 3362  USA Toll Free: 1-888-667-7839
> Internet: http://www.rising.com.au/
Article: 14757
Subject: Verilog FAQ
From: rajesh52@hotmail.com
Date: Mon, 15 Feb 1999 18:17:29 GMT
Links: << >>  << T >>  << A >>
Greetings
This is semimonthly announcement of Verilog FAQ.

Verilog FAQ is located at
http://www.angelfire.com/in/verilogfaq/

Alternate Verilog FAQ is an attempt to gather the answers to most
Frequently Asked Questions about Verilog HDL in one place.
It also  contains list of publications, services, and products.

Alternate Verilog FAQ is divided into three logical parts.

Part 1 : Introduction and misc. questions
Part 2 : Technical Topics
Part 3 : Tools and Services

What's New section outlines the changes in different versions and
announcements. Links connects you to related informative links in internet.


Rajesh Bawankule
(Also Visit Verilog & EDA Page :
http://www.angelfire.com/in/rajesh52/verilog.html )

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 14758
Subject: Re: Problems with Xilinx F1.5 & latchs
From: Bob Sefton <rsefton@home.com>
Date: Mon, 15 Feb 1999 18:36:25 GMT
Links: << >>  << T >>  << A >>
Tximo wrote:
> 
> Hi all,
> I'm trying to synthesize in an XC4010E the module shown below, but F1.5
> gives me next message:
> 
> Error: Sequential mapping has detected that the cell
> '/ver1-Optimized/load_reg' uses both asynchronous
> 'set' and 'clear' pins. The target architecture does not support both on
> the same sequential device (FE-SEQMAP-2)
> 
> After a lot of tests, if sentences with "-- ******" are commented, the
> error dissappears, and from time to time I get next warning:
> 
> Warning: Latch inferred in design 'generar_stuff_bis' read with
> 'hdlin_check_no_latch' (HDL-307)
> 
> My problems are that I am not using any latch, I don't know how to
> access 'hdlin_check_no_latch' variable, and I don't know
> the use of the inferred latch.
> 
> Suggestions and ideas are welcome.  Thanks in advance
> 
> My e-mail: jgracia@disca.upv.es


You commented out all of the assignments to the only two outputs
of your design, so most of your design was probably optimized
away. It's not surprising this got rid of the first error message
(the "load" register got ripped out). Then with most of the
registers optimized away you must have been left with a
combinational signal assignment that inferred a latch. Don't worry
about this warning because it's bogus and was caused by you
commenting out all of your logic. Instead you need to solve the
async clear/preset problem. You'll have to find another way to
code it.

I'm surprised the synthesis tool got past an initial syntax check
with bus_libre not listed in the sensitivity list of the process.
That should have been flagged first. Incomplete if-then-else
conditions aren't a problem in a clocked process. It's not
possible to infer latches in a clocked process unless the
synthesis tool doesn't recognize it as a clocked process. Again,
don't start chasing the warning message, just fix the coding of
the async clear/preset.

Bob S.
Article: 14759
Subject: Re: Xilinx Spartan and pin-locking
From: "Austin Franklin" <austin@dark0room.com>
Date: 15 Feb 1999 18:52:15 GMT
Links: << >>  << T >>  << A >>
Stuart,

If you do your floorplanning before choosing your pinout, you should have
no problems.  I strongly recommend that you don't let the tools choose the
pinout for you!  I don't know what frequency you are running, but I pinlock
all the time.  By understanding the architecture of the FPGA, you can
figure out how your design can best be placed in the design.  Also,
registering the I/Os in the IOB helps dramatically too ;-)

Austin Franklin
austin@darkroom.com


Stuart J Adams <sja@world.std.com> wrote in article
<F77BIG.IDK@world.std.com>...
> Anyone have any experience with how pin-locking
> friendly the SpartanXL series is. We are
> a spinning up a board with an XCS05XL on it and 
> have not done the FPGA design for it yet. In the
> past we have used Altera 6K and 10K and not had nay
> problems droping in a design after the board is
> finished.
> 
> Thanks,
>   Stuart
> 
> 
Article: 14760
Subject: Re: Problems with Xilinx F1.5 & latchs
From: Tximo <jgracia@disca.upv.es>
Date: Mon, 15 Feb 1999 19:55:56 +0100
Links: << >>  << T >>  << A >>
I have solved the problem.  It was a signal that was latched and changed its
valor in the same time (different delta).  That is, the set and clear pins of
a latch were active at the same time.

Thanks to all for your help.

Bob Sefton escribiķ:

> Tximo wrote:
> >
> > Hi all,
> > I'm trying to synthesize in an XC4010E the module shown below, but F1.5
> > gives me next message:
> >
> > Error: Sequential mapping has detected that the cell
> > '/ver1-Optimized/load_reg' uses both asynchronous
> > 'set' and 'clear' pins. The target architecture does not support both on
> > the same sequential device (FE-SEQMAP-2)
> >
> > After a lot of tests, if sentences with "-- ******" are commented, the
> > error dissappears, and from time to time I get next warning:
> >
> > Warning: Latch inferred in design 'generar_stuff_bis' read with
> > 'hdlin_check_no_latch' (HDL-307)
> >
> > My problems are that I am not using any latch, I don't know how to
> > access 'hdlin_check_no_latch' variable, and I don't know
> > the use of the inferred latch.
> >
> > Suggestions and ideas are welcome.  Thanks in advance
> >
> > My e-mail: jgracia@disca.upv.es
>
> You commented out all of the assignments to the only two outputs
> of your design, so most of your design was probably optimized
> away. It's not surprising this got rid of the first error message
> (the "load" register got ripped out). Then with most of the
> registers optimized away you must have been left with a
> combinational signal assignment that inferred a latch. Don't worry
> about this warning because it's bogus and was caused by you
> commenting out all of your logic. Instead you need to solve the
> async clear/preset problem. You'll have to find another way to
> code it.
>
> I'm surprised the synthesis tool got past an initial syntax check
> with bus_libre not listed in the sensitivity list of the process.
> That should have been flagged first. Incomplete if-then-else
> conditions aren't a problem in a clocked process. It's not
> possible to infer latches in a clocked process unless the
> synthesis tool doesn't recognize it as a clocked process. Again,
> don't start chasing the warning message, just fix the coding of
> the async clear/preset.
>
> Bob S.



Article: 14761
Subject: Re: comp.arch.fpga Archives
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Mon, 15 Feb 1999 12:22:40 -0800
Links: << >>  << T >>  << A >>
You can find links to the various archives for this group on The
Programmable Logic Jump Station at
http://www.optimagic.com/newsgroups.html#FPGA.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

T. Franklin wrote in message <36BF4E8C.5FF0F72C@nospam.harris.com>...
>Where can I find the archives for this newsgroup?
>
>--
>To reply please remove the nospam
>from the reply address.
>
>regards,
>
>Ted
>
>


Article: 14762
Subject: Re: Xilinx Spartan and pin-locking
From: "Steve" <reply.through.newsgroup@paranoid.com>
Date: Mon, 15 Feb 1999 21:30:57 GMT
Links: << >>  << T >>  << A >>
My understanding is that pin locking is mainly a routing issue, and
that the smaller the part, the less of an issue.  So I suspect your
lack of problems in Altera were in the smaller parts.  Having chosen
the smallest Spartan part I expect you will see similar results.

If you do have a problem and have money to upgrade, the XL/XLA
parts have more routing resources, as would a larger Spartan, like
the XCS10XL.  ie you are probably not painting yourself into the
proverbial corner, unless of course you didn't assign the dedicated
pins correctly!


Steve

Stuart J Adams wrote in message ...
>Anyone have any experience with how pin-locking
>friendly the SpartanXL series is. We are
>a spinning up a board with an XCS05XL on it and
>have not done the FPGA design for it yet. In the
>past we have used Altera 6K and 10K and not had nay
>problems droping in a design after the board is
>finished.
>
>Thanks,
>  Stuart
>


Article: 14763
Subject: orcad
From: moshe moalem <moshem@easx.co.il>
Date: Tue, 16 Feb 1999 00:00:39 +0200
Links: << >>  << T >>  << A >>
Hi evrybody

does enybody know about any utility converting from Altera report file
to Orcad and creating a symbol?


Thanks in advance
Moshe
Article: 14764
Subject: Re: orcad
From: "Steve" <reply.through.newsgroup@paranoid.com>
Date: Mon, 15 Feb 1999 23:21:01 GMT
Links: << >>  << T >>  << A >>
Check under Orcad Express Tools/Generate Part
I found it to be a bit buggy, but it's worth trying.  I think it reads
your edif file from Altera, although VHDL might work too.

Make sure you use the file with the pin info!


Steve


moshe moalem wrote in message <36C89907.6661@easx.co.il>...
>Hi evrybody
>
>does enybody know about any utility converting from Altera report file
>to Orcad and creating a symbol?
>
>
>Thanks in advance
>Moshe


Article: 14765
Subject: Anyone experience with Aptix?
From: Richard Hogers <Richard.Hogers@nym.sc.philips.com>
Date: Tue, 16 Feb 1999 11:22:24 GMT
Links: << >>  << T >>  << A >>
Hello,

Maybe a bit off topic, but is there anyone out there
who has experience with the System Explorer product
line from Aptix?
I would like to hear what you think about it.


Best regards

Richard


-- 

  Richard Hogers
  Philips Semiconductors Nijmegen
  Business Line Cellular
  Building FB-3, room 070
  Gerstweg 2
  6534 AE Nijmegen, The Netherlands
  
  Tel. +31 24 3534374
  Fax. +31 24 3533589,
  
  E-mail: Richard.Hogers@nym.sc.philips.com
Article: 14766
Subject: Re: Synplify resource usage report for Virtex devices
From: Eduardo Augusto Bezerra <E.A.Bezerra@sussex.ac.uk>
Date: Tue, 16 Feb 1999 15:22:48 +0000
Links: << >>  << T >>  << A >>

Utku Ozcan wrote:
> 
> Ooo, your design seems to be very big!
> 
>    1. Which version of Synplify are you using? The version you are using
>       might result false reports, maybe a never version is correct.
> 

Synplify 5.0.7

>    2. Have you controlled all the codes to be targetted carefully?
>       Maybe you have unknowingly added a big core. Or duplicated source.
> 

No, I'm not using any cores. All my VHDL code is hand made.

>    3. The process time of Synplify is very long. From there I get you
>       tried a very complex device to FPGA. Maybe a predesigned ASIC core?

I think it is because my design is not exactly suitable for FPGA
architectures. It is an experiment I'm doing. I've got a lot of
memory in this design.

> 
>    Maybe your design is extremely big to fit into aFPGA. Maybe you
>    have been using plenty of macros (RAMs, for example). Then you can divide
>    the core into two chips, if possible. Maybe there is a coding style problem.
>    The amount is extremely big.
> 

There are no macros in my design. But coding style might be a problem.
I'm not a VHDL for synthesis expert. My original design was quite big,
so
I've divided it in two parts. One of them fitted in an XC40150, but the
other part (the reports I sent in the first message) didn't, that is
why I tried the Virtex device.

Thanks a lot for the suggestions. I'll analyse better my design, and
try some alterations.

Eduardo.
Article: 14767
Subject: Re: Synplify resource usage report for Virtex devices
From: Eduardo Augusto Bezerra <E.A.Bezerra@sussex.ac.uk>
Date: Tue, 16 Feb 1999 17:07:42 +0000
Links: << >>  << T >>  << A >>

Philip Freidin wrote:
> 
> You seem to be using an insane number of flip flops, given the amount of
> logic you are implementing. Over 11000 flipflops and over 8000 muxF5/F6,
> almost no I/O, and almost no logic, ( I am asuming the Luts are doing
> route thru or more muxes, as there is no reported logic in the
> " Resource Usage Report" section.) Are you implementing a huge shifter,
> or maybe a memory, and it is being implemented in FFs????
> 
> Imagine how much more help people could give you, if you had actually
> described you application!
> 
> Philip.
> 

Ok. I'll try to describe my application.

It's an ACF (auto correlation function) implemented in VHDL.
The reports I post in my first message were from the low frequency
module that basically:

- receive data from IP1_IN and IP2_IN inputs (see entity
  definition bellow);
- store the data in two FIFOs (256x5 bits each one);
- read the FIFOs and build a histogram in an 1 Kbytes memory
  (the memory addresses are selected according to the
   LAST_ENERGY_IN input);
- transfer blocks of data from the 1 Kbytes memory to an 128 bytes
  memory and put them in a specific format, according to a 
  protocol, in order to the telemetry data be sent to the Earth
  by the LIMBO_OUT output (it is a space application);
- read the 128 bytes memory, convert the data from the parallel
  to the serial format and send them to the LIMBO_OUT output.

As you said, there is almost no I/O, and almost no logic. It is
really a memory transfer application. Why do we want to use FPGAs?
Because we want to change (reconfigure) the on-board hardware from
the Earth.

I've included bellow some definitions I used in my design.

But what I really want to know is if my design fits in the V1000
Virtex. The synplify report for the XC40150XV FPGA gave me the
follow information:

> Logic Mapping Summary:
> FMAPs: 31017 of 10952 (284%)
> HMAPs: 14037 of 5476 (257%)
> Total packed CLBs: 15509 of 5476 (284%)
 
I don't know if it is possible to get this information for
the V1000 Virtex FPGA. I'm interested in the % data.

Eduardo.


entity SVALHF is

  port ( CLK_IN          : in  std_logic;  -- Global clock
         RESET_NEG_IN    : in  std_logic;  -- Global reset
         NEW_STEP_NEG_IN : in  std_logic;  -- New energy step pulse
         LAST_ENERGY_IN  : in  std_logic_vector(3 downto 0);
         IP1_IN          : in  std_logic;  -- Input1
         IP2_IN          : in  std_logic;  -- Input2
         TELEMTRY_CLK_IN : in  std_logic;  -- Telemetry clock
         NEXT_OP_BIT_IN  : in std_logic;   -- Next O/P request
         LIMBO_OUT       : out std_logic   -- Output data
       );

end SVALHF;

architecture SVALHF_BEH of SVALHF is

   component FSM_HF
      port ( CLK_IN          : in  std_logic;
             RESET_NEG_IN    : in  std_logic;
             IP_IN           : in  std_logic;
             WR_NEG_FIFO_OUT : out std_logic;
             DATA_OUT        : out std_logic_vector (4 downto 0)
           );
   end component;

   component FIFO_HF
      port ( RESET_NEG_IN   : in  std_logic;
             RD_NEG_IN      : in  std_logic;
             WR_NEG_IN      : in  std_logic;
             DATA_IN        : in 
std_logic_vector(WORD_LENGTH_FIFO_HF_C-1 downto 0);
             DATA_OUT       : out
std_logic_vector(WORD_LENGTH_FIFO_HF_C-1 downto 0);
             FIFO_HALF_OUT  : out std_logic;
             FIFO_EMPTY_OUT : out std_logic;
             FIFO_FULL_OUT  : out std_logic
           );
   end component;

   component PAR2SER_HF
      port( CLK_LD_IN    : in  std_logic;
            CLK_SHIFT_IN : in  std_logic;
            DATA_IN      : in  std_logic_vector( SIZE_OF_PAR2SER_HF_C -
1 downto 0 );
            DATA_OUT     : out std_logic
           );
   end component;

   -- declarations for component FSM1_HF
   signal CLK_FSM1_HF, RESET_NEG_FSM1_HF,
          IP_FSM1_HF                      : std_logic;
   signal WR_NEG_FIFO_FSM1_HF             : std_logic;
   signal DATA_FSM1_HF                    : std_logic_vector (4 downto
0);

   -- declarations for component FSM2_HF
   signal CLK_FSM2_HF, RESET_NEG_FSM2_HF,
          IP_FSM2_HF                      : std_logic;
   signal WR_NEG_FIFO_FSM2_HF             : std_logic;
   signal DATA_FSM2_HF                    : std_logic_vector (4 downto
0);

   -- declarations for component FIFO1_HF
   signal RESET_NEG_FIFO1,
          RD_NEG_FIFO1, WR_NEG_FIFO1      : std_logic;
   signal DATA_OUT_FIFO1, DATA_IN_FIFO1   :
std_logic_vector(WORD_LENGTH_FIFO_HF_C-1 downto 0);
   signal FIFO1_HALF_FULL, FIFO1_EMPTY,
          FIFO1_FULL                      : std_logic;

   -- declarations for component FIFO2_HF
   signal RESET_NEG_FIFO2,
          RD_NEG_FIFO2, WR_NEG_FIFO2      : std_logic;
   signal DATA_OUT_FIFO2, DATA_IN_FIFO2   :
std_logic_vector(WORD_LENGTH_FIFO_HF_C-1 downto 0);
   signal FIFO2_HALF_FULL, FIFO2_EMPTY,
          FIFO2_FULL                      : std_logic;

   -- declarations for component PAR2SER_HF
   signal CLK_LD_PAR2SER,
          CLK_SHIFT_PAR2SER               : std_logic;
   signal DATAIN_PAR2SER                  : std_logic_vector(
SIZE_OF_PAR2SER_HF_C - 1 downto 0 );
   signal DATAOUT_PAR2SER                 : std_logic;

   -- declarations for TELEMETRY_HF
   signal DATA_TELEMETRY                  : std_logic_vector(
SIZE_OF_PAR2SER_HF_C - 1 downto 0 );

   -- declarations for SVALHF
   signal MEM1                            : RAM1K_TYP;     -- SRAM
memory (1K bytes)
   signal M1_PTR                          : std_logic_vector(9 downto
0);
   signal AUX_M1_PTR                      : std_logic_vector(9 downto
0);
   signal MEM2                            : RAM68_TYP;     -- SRAM
memory (32 bytes)
   signal M2_PTR                          : std_logic_vector(6 downto
0);
   signal AUX_DATA                        :
std_logic_vector(WORD_LENGTH_FIFO_HF_C-1 downto 0);
   signal FLAG_POWERUP                    : std_logic;
   signal FLAG_WHICH_IP, DATA_READY       : std_logic;
   signal OP_BLK_ENERGY                   : std_logic;
   signal FLAG_NEW_NEXT_OP,
          FLAG_NEXT_OP_REQ                : std_logic;
   signal FLAG_NEW_ESTEP,
          FLAG_NEW_ESTEP_OLD              : std_logic;
Article: 14768
Subject: Any FREE soft for XC5000 series ?
From: "Sagaert Johan" <sagaert.johan@usa.net>
Date: 16 Feb 1999 17:39:38 GMT
Links: << >>  << T >>  << A >>
Hello ,

I am looking for any free soft to use it on XC5202 devices from XILINX ,
i don't need schamatic entry ,but would already happy to receive something
that i can use
to program equitions,state machine and lookup tables ,text version
compiler.

What is available ?
  
Sagaert Johan sagaert.johan@usa.net

Article: 14769
Subject: Verilog FAQ
From: rajesh52@hotmail.com
Date: Tue, 16 Feb 1999 18:49:45 GMT
Links: << >>  << T >>  << A >>
Greetings
This is semimonthly announcement of Verilog FAQ.

Verilog FAQ is located at
http://www.angelfire.com/in/verilogfaq/

Alternate Verilog FAQ is an attempt to gather the answers to most Frequently
Asked Questions
about Verilog HDL in one place. It also  contains list of publications,
services, and products.

Alternate Verilog FAQ is divided into three logical parts.

Part 1 : Introduction and misc. questions
Part 2 : Technical Topics
Part 3 : Tools and Services

What's New section outlines the changes in different versions and
announcements. Links connects you to related informative links in internet.


Rajesh Bawankule
(Also Visit Verilog & EDA Page :
http://www.angelfire.com/in/rajesh52/verilog.html )

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 14770
Subject: Flex6016 config. problem.
From: "Anthony Ellis - LogicWorks" <aelogic@iafrica.com>
Date: Tue, 16 Feb 1999 20:58:56 +0200
Links: << >>  << T >>  << A >>
On a new design (there are at least half a dozen similar designs working
using the same devices and configuration setup) I am having problems
configuring a Flex6016 using EPC1441 or EPC1. The device starts the config.
cycle but aborts after about 6000 bits. (~6us at 140ns/bit) presumable
because of a detected CRC error. Why just this one design I don't know. No
other pins toggle during the config process although there are many unused
floating pins????

Any ideas?


Article: 14771
Subject: Re: xnf de-compiler
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Tue, 16 Feb 1999 11:11:24 -0800
Links: << >>  << T >>  << A >>
Viewlogic used to draw schematics from xnf.


Sergio A. Cuenca Asensi wrote in message <36C8083D.F9EAFAE8@dtic.ua.es>...
>Hello
>somebody knows any tool to get a schematic from a xnf netlist?. I am
>using FPGA Express  in a digital design course and
>this tool could be very useful for my students (and for me).
>Thanks
>
>--
>===================================================================
>Sergio A. Cuenca Asensi
>Dept. Tecnologia Informatica y Computacion (TIC)
>Escuela Politecnica Superior, Campus de San Vicente
>Universidad de Alicante
>Ap. Correos 99, E-03080 ALICANTE
>ESPAŅA (SPAIN)
>email   : sergio@dtic.ua.es
>Phone : +34 96 590 39 34
>Fax     : +34 96 590 39 02
>===================================================================
>
>


Article: 14772
Subject: Re: AHDL & VHDL
From: ali Benkhalil <akbenkha@bradford.ac.uk>
Date: Tue, 16 Feb 1999 11:18:58 -0800
Links: << >>  << T >>  << A >>



Yes, good question. Simply I nearly finished writing the code I need
using
the AHDL which took me 18 months.
So it is impossible for me now to change to VHDL. That why I want to do
this.

HAVE FUN TOO!!!!!!!!!!

A.K.

Nick wrote:

>  Just a question.  Why would you want to do that?  If you have VHDL
> capapility then use it.  Why lock yourself into a tool set by using
> AHDL?
>
> HAVE FUN!!
> Nick
>
> ali Benkhalil wrote:
>
>>  Hi,
>>  I am using MAX+plusII Ver. 8.2.
>> I want to know is it possible to write a mixed code AHDL (Altera
>> HDL) and VHDL
>> and compile it using MAX+plusII. (e.g. Call VHDL function from AHDL
>> code)
>>
>> Thanks.
>>
>> A.K.
>>
>




Article: 14773
Subject: Re: Flex6016 config. problem.
From: "Pascal Dornier" <pdornier@pcengines.com>
Date: Tue, 16 Feb 1999 11:32:44 -0800
Links: << >>  << T >>  << A >>
Anthony Ellis - LogicWorks wrote in message
<7acf3t$1hug$1@nnrp01.iafrica.com>...
>On a new design (there are at least half a dozen similar designs working
>using the same devices and configuration setup) I am having problems
>configuring a Flex6016 using EPC1441 or EPC1. The device starts the config.
>cycle but aborts after about 6000 bits. (~6us at 140ns/bit) presumable
>because of a detected CRC error. Why just this one design I don't know. No
>other pins toggle during the config process although there are many unused
>floating pins????


I once had configuration problems with a 144 pin EPF6016, which was fixed
by downloading their latest software.

--------------------------------------------------------------------
Pascal Dornier   pdornier@pcengines.com     http://www.pcengines.com
Your Spec      + PC Engines            = Custom Embedded PC Hardware
--------------------------------------------------------------------


Article: 14774
Subject: Re: orcad
From: bob elkind <eteam@aracnet.com>
Date: Tue, 16 Feb 1999 12:17:27 -0800
Links: << >>  << T >>  << A >>
Here's a tool that I've used, and I'm very happy with it...

See http://members.tripod.com/~ma_gm/al2or.html

precis description (from the webpage):

Altera to OrCAD Rev 1.00 is a simple utility that allows you to create a symbol for OrCAD, based on the
contents of an Altera Max-Plus II Configuration File (ACF).

It requires the utility COMP16.EXE, available in OrCAD for DOS and for Windows versions, to compile the
library created by this utility. Once compiled, both OrCAD for DOS and OrCAD Capture/Express for Windows
are able to read it automatically.

It also includes a librarian capability that allows you to re-use the definition of power pins and some other
dedicated pins in every part. So you need to enter them only once, and everything else will be automatic !!

Save time and increase the reliability of your schematics avoiding error prone manual conversions.

moshe moalem wrote:

> Hi evrybody
>
> does enybody know about any utility converting from Altera report file
> to Orcad and creating a symbol?
>
> Thanks in advance
> Moshe

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****




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