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On 10/04/2010 01:12 PM, Alexander Kane wrote: > On Oct 5, 6:50 am, Mike Treseler<mtrese...@gmail.com> wrote: >> Suggestions: >> >> 1. Learn C++ also to write/debug drivers interfacing to the FPGA. >> 2. Learn scripting to verify the FPGA and drivers at the system level. >> Bash, python and tcl to start with. >> 3. Develop your your own project to demonstrate the above skills. >> Exercise popular interfaces on your FPGA demo board: >> GigE, SDRAM3, USB3 etc. >> >> Notes: >> >> 1. Unless you work for an FPGA manufacturer, >> few jobs involve FPGA work all day long. >> 2. Most tough FPGA bugs are at the interfaces to other chips. >> 3. Fixing an "FPGA" bug may not require any changes to the VHDL or >> Verilog code. Often the problem is a bad register setting on >> some other chip -- but one that only the FPGA guy can find. >> >> Good luck. >> >> -- Mike Treseler > > Thanks for the pointers Mike. I realise that most jobs won't involve > working with an FPGA all day long (I don't necessarily want to be "the > FPGA guy"), but I would like to work on projects that involved them. > In my studies I've done quite a bit of hardware design as well as > software, it sounds from your post that software skills are much more > important than hardware skills when working with FPGAs, is that > right? Not necessarily -- good FPGA guys have to understand digital logic and it's embodyment with an HDL, they have to understand some analog to really grok the timing issues and chip interface issues, and they are often -- even in large groups -- called upon to design the boards on which the FPGA resides, so they have to be good with board-level design as well. Knowing software, too, is just a huge plus. > And, I guess, I was also wondering what publications/websites > or whatever might be good places to start looking for jobs. Anyway, > I'll try follow up on your suggestions. Pick a city or some cities and start looking at want ads, or go to company web sites and read the "Jobs offered" section. Rarely will you find a company advertising for a new college hire, particularly in this economy. Instead, look for companies that are hiring experienced guys that do what you want to do in 5-10 years, and apply there in hopes that they need to hire a junior guy as well. Even though you're in NZ, get a copy of "What Color is your Parachute". It's aimed at folks in the US who are changing careers, but there is lots of the material that's pertinent to anyone considering any job change -- and you're thinking of changing from a student to a professional, so that counts. Much will be irrelevant to your situation, but much will matter, so get a copy and sort it out. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 149151
On 10/03/2010 05:11 PM, Alexander Kane wrote: > Hello. > I'm currently coming to the end of my last semester of my four year > engineering degree in electronics and computer systems engineering. > I've really enjoyed working with FPGAs as part of my degree and am now > tutoring the FPGA course. Basically I want to start a career working > with FPGAs, but am not sure how to go about it. I live in New > Zealand, but as the job market here is so small I'm looking at Europe > (as I speak both English and German I figure that opens up several > countries I could work in). Does anyone have any suggestions or > advice as to how I go about entering such a career, or what kind of > options are out there, or even websites I can look for jobs on? > Thanks in advance. These days "digital designer", unless it's a chip company, either means "motherboard design" or "FPGA design". Start with "digital designer" and read the job posting -- you'll find lots of FPGA work. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 149152
On Oct 4, 7:27=A0pm, rickman <gnu...@gmail.com> wrote: > > Peter Alfke > > At least the US knows how to use a decimal POINT! =A0Who came up with > the decimal comma??? > > Rick > In defense of the decimal comma: Graphically, the comma is a much more visible delimiter than the point. The difference between 25 and 2.5 can be so tiny (in certain typefaces) that I have used a magnifying glass to find out. There are many habits one has to change when one moves over the big pond: months/days, points/commas, billions/ milliards, banking methods, driving rules, etc Makes life interesting... PeterArticle: 149153
rickman wrote: > The Xilinx/ARM announcement may end up being much more interesting, I'm not sure why to expect it to be any more interesting than the Altera/ARM stuff was, or for that matter, the Xilinx/IBM stuff. As in, not very interesting at all. EricArticle: 149154
On 10/4/2010 1:12 PM, Alexander Kane wrote:
> Thanks for the pointers Mike. I realise that most jobs won't involve
> working with an FPGA all day long (I don't necessarily want to be "the
> FPGA guy"), but I would like to work on projects that involved them.
> In my studies I've done quite a bit of hardware design as well as
> software, it sounds from your post that software skills are much more
> important than hardware skills when working with FPGAs, is that
> right?
Hardware skills are just as important.
The point is that in most systems there
are CPUs and other complex interface chips attached to
to the FPGA, and that the FPGA work is not done
until all the modes and interfaces are working.
> And, I guess, I was also wondering what publications/websites
> or whatever might be good places to start looking for jobs.
For a new graduate, internships are best, if you can get one.
Otherwise, work on your own and socialize with others who share your
interests.
-- Mike Treseler
Article: 149155"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:5d75194a-716f-4baf-86dc-c3da49fd084e@k22g2000prb.googlegroups.com... On Oct 4, 7:27 pm, rickman <gnu...@gmail.com> wrote: >There are many habits one has to change when one moves over the big pond: > months/days, points/commas, billions/ milliards, banking methods,driving > rules, etc >Makes life interesting... And expensive.. Im thinking of technology 'bleepers'... :)Article: 149156
On Oct 4, 4:13=A0pm, Santosh <santos...@gmail.com> wrote: > On Oct 4, 5:42=A0pm, Santosh <santos...@gmail.com> wrote: > > > On Oct 4, 5:00=A0pm, Anssi Saari <a...@sci.fi> wrote: > > > > radarman <jsham...@gmail.com> writes: > > > > Those boards are made by Digilent. You might check and see if they > > > > have a breadboard with the Hirose connector on it. > > > > They do, for $30. Also a wirewrap and module interface board (for > > > Pmods) which are both cheaper at $20. > > > There are a lot of Pmods there. I need to input and output digital > > data from FPGA board. Please suggest me the exact name. Also, except > > Hirose port aren't there any ports to connect external circuit? > > San. > > Hi, > I found this board. -- =A0http://www.digilentinc.com/Data/Products/FX2BB/= FX2BB_%20rm.pdf > =A0Is it the same you people mentioned? And do I need a bus to connect > the board with FPGA? Or the Hirose in the daughter board directly > couples with the Hirose on FPGA? I didn't found any bus or cables in > their site. This board fits to your expansion connector on spartan 3e starter kit. You don't need any bus, cable etc.Article: 149157
On Oct 4, 4:13=A0pm, Santosh <santos...@gmail.com> wrote: > On Oct 4, 5:42=A0pm, Santosh <santos...@gmail.com> wrote: > > > On Oct 4, 5:00=A0pm, Anssi Saari <a...@sci.fi> wrote: > > > > radarman <jsham...@gmail.com> writes: > > > > Those boards are made by Digilent. You might check and see if they > > > > have a breadboard with the Hirose connector on it. > > > > They do, for $30. Also a wirewrap and module interface board (for > > > Pmods) which are both cheaper at $20. > > > There are a lot of Pmods there. I need to input and output digital > > data from FPGA board. Please suggest me the exact name. Also, except > > Hirose port aren't there any ports to connect external circuit? > > San. > > Hi, > I found this board. -- =A0http://www.digilentinc.com/Data/Products/FX2BB/= FX2BB_%20rm.pdf > =A0Is it the same you people mentioned? And do I need a bus to connect > the board with FPGA? Or the Hirose in the daughter board directly > couples with the Hirose on FPGA? I didn't found any bus or cables in > their site. This board fits to your expansion connector on spartan 3e starter kit. You don't need any bus, cable etc.Article: 149158
On Oct 4, 3:18=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Ok, i assigned a fixed level to reset so that it comes in a known state a= nd > still the problem persists. I actually placed an internal pull down on > reset, reset is active high. And i couldn't find any warning related to > reset. > > And well yes i guess i'll have to reduce the number of warnings to make i= t > work. > Today i also migrated to xilinx 12.1 to make sure the older version wasn'= t > making it a big deal for me but same result only synthesis takes less tim= e > which is a relief =3D) > > I'll keep you updated so that if someone else faces this problem, he can > take reference from here. =3D) > > thanks mate > > regards > SalimBaba =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I echo the importance of checking to see if anything was optimized out. In FPGA editor--or simply check the PAD report--verify that every input and output port of your top-level file is present. Make sure any black boxes you are using (e.g. embedded ram and fifos) are satisfactorily filled during par (typically need proper NGC file in project directory and/or search path. I don't think you mention anything about timing closure. Are you defining period constraint for your clock(s)? Does static timing analysis report that design passes all timing constraints? Good luck. JohnArticle: 149159
>I echo the importance of checking to see if anything was optimized >out. In FPGA editor--or simply check the PAD report--verify that every >input and output port of your top-level file is present. Make sure any >black boxes you are using (e.g. embedded ram and fifos) are >satisfactorily filled during par (typically need proper NGC file in >project directory and/or search path. > >I don't think you mention anything about timing closure. Are you >defining period constraint for your clock(s)? Does static timing >analysis report that design passes all timing constraints? > >Good luck. >John > Hi John, I haven't defined any timing constraints and my design passes the timing constraints test. Now i am looking at the warnings if anything is getting optimized out. And i didn't know that these black boxes can create problems, i am using many fifos and embedded rams.i'll have to check on them. Thanks John =) regards SalimBaba --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149160
On Oct 5, 1:36=A0am, Eric Smith <space...@gmail.com> wrote: > rickman wrote: > > The Xilinx/ARM announcement may end up being much more interesting, > > I'm not sure why to expect it to be any more interesting than the > Altera/ARM stuff was, or for that matter, the Xilinx/IBM stuff. =A0As > in, not very interesting at all. > > Eric Why was the Altera/ARM stuff not interesting? It failed because it was so expensive, in my opinion. I expect we'll never find out from Altera. The Actel Fusion part is also a bit pricey. You forgot to mention the Atmel FPSLIC part (Atmel FPGA/AVR). I'm not sure if that is still around, but it has become inconsequential because of the price and the lack of advancement of the development tools. The Xilinx/ARM stuff might be interesting if they actually tap the full potential of providing a range of products to match the range of CPUs that are available from ARM. If Xilinx just repeats what they did with the PPC and just makes one limited line of devices then I don't see that being especially successful either. Actually, I shouldn't say that. Knowing Xilinx, I expect they will identify the markets with the most potential and design a small number of FPGA/ARM devices tailored to those apps. One might be cell phones. That is a potentially HUGE market and SiBlue is currently trying to break into that area. If Xilinx combines an ARM with a low end FPGA like the SiBlue parts, they could beat them at their own game. Or perhaps a larger FPGA (if it is cheap enough and low power enough) could replace some of the custom logic in a cell phone? But mostly, Xilinx understands their core market, network comms. For them a large FPGA combined with one or more high end ARM cores (a la Virtex- II Pro) is what we can expect. If you were combining an FPGA with a CPU in a market where a number of companies were doing that, how would you differentiate your product? RickArticle: 149161
On Oct 5, 2:49=A0am, Mike Treseler <mtrese...@gmail.com> wrote: > On 10/4/2010 1:12 PM, Alexander Kane wrote: > > > Thanks for the pointers Mike. =A0I realise that most jobs won't involve > > working with an FPGA all day long (I don't necessarily want to be "the > > FPGA guy"), but I would like to work on projects that involved them. > > In my studies I've done quite a bit of hardware design as well as > > software, it sounds from your post that software skills are much more > > important than hardware skills when working with FPGAs, is that > > right? > > Hardware skills are just as important. > The point is that in most systems there > are CPUs and other complex interface chips attached to > to the FPGA, and that the FPGA work is not done > until all the modes and interfaces are working. The number of hardware related jobs is steadily declining compared to the number of software related jobs. FPGA design can be considered a software job and in fact, at the last company I worked for full time, was organized under software and the entire hardware design was considered subservient to the software design. You very much can work in FPGAs and spend 95% of your time banging a keyboard writing and simulating code. I build boards and spend maybe a max of 20% of my time in the lab. Software is by far the dominant portion of electronic design for now and the foreseeable future. Embedded software is currently a hot area of work (mostly C code rather than HDLs) but may become less so as systems become more capable and embedded software becomes more like programming a PC. Another trend, although still in its infancy, is the merger of HDL with standard programming languages. It seems to be making slow headway, but there is a lot pushing it along. The idea of writing one program which can flexibly be partitioned into hardware and software is a highly prized goal. RickArticle: 149162
Thomas and Rick, thanks a lot for clarifying the last parts for me. With your and the others' help I'm now confident with what the requirements are and have presented this to my client, we'll see which solution we'll end up persuing. 1) Put into evidence that there always is enough time _between_ reads to perform a scratch refresh. When measuring timing on the original machine this seems OK but this needs firm evidence. 2) Using dual SDRAMs 3) Using a 4x size SDRAM, and toggle between banks 4) Using NOR-flash 5) Using SRAM (already out because of the price) Solutions involving changing the original CPU is out of the question, and the same applies to changing the original software. This since the application is medical, and any changes on that level would require re- validations and certifications, costs for that are unreasonable. Again, thanks a lot for your efforts! /JohannesArticle: 149163
>2. Learn scripting to verify the FPGA and drivers at the system level. > Bash, python and tcl to s Just a question... what kind of important tasks can be done with script that the vendor synthesiser (as QUartus II or ISE) cant handle?Article: 149164
Un bel giorno rickman digitň: > I had not heard of the Intel/Altera union. That appears to be > oriented to creating a device that can be responsive to rapidly > changing I/O requires of the market. I think it's more likely that they are looking for a way to crunch numbers faster and close the gap with GPUs: http://blogs.nvidia.com/ntersect/2010/06/gpus-are-only-up-to-14-times-faster-than-cpus-says-intel.html -- emboliaschizoide.splinder.comArticle: 149165
On 10/5/2010 7:47 AM, Luís Rossi wrote:
>> 2. Learn scripting to verify the FPGA and drivers at the system level.
>> Bash, python and tcl to s
> Just a question... what kind of important tasks can be done with
> script that the vendor synthesiser (as QUartus II or ISE) cant handle?
Run my new image overnight in the system,
while executing a certain driver command in a loop,
and send me an email if anything unexpected happens.
-- Mike Treseler
Article: 149166I am listening to the Xilinx webinar on partial reconfiguration and they say the Artix 7 will be the first "spartan" type device that will be supported under the ISE software for partial reconfiguration. Anyone heard when the Artix 7 devices are supposed to be in production? Are we talking about a practical time frame such as 6 to 9 months or is it being stated as a year or more? Or have they only talked about when they will be shipping "samples"? I know there can be quite a difference.Article: 149167
rickman <gnuarm@gmail.com> wrote: > I am listening to the Xilinx webinar on partial reconfiguration and > they say the Artix 7 will be the first "spartan" type device that will > be supported under the ISE software for partial reconfiguration. > Anyone heard when the Artix 7 devices are supposed to be in > production? Are we talking about a practical time frame such as 6 to > 9 months or is it being stated as a year or more? Or have they only > talked about when they will be shipping "samples"? I know there can > be quite a difference. Are you talking about some types in ES availability or about general availability? ES sample might be 9 month, GA much longer. Even S6 I wouldn't call general available... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 149168
I doubt they will be available in any numbers if at all in your practical timescales. Spartan-6 is the practical choice for that timescale given the availability has now improved vastly. As a time mark we are now heading towards 2 years since Spartan-6 was announced.and it is just being available in serious numbers now. John Adair Enterpoint Ltd. On 5 Oct, 20:43, rickman <gnu...@gmail.com> wrote: > I am listening to the Xilinx webinar on partial reconfiguration and > they say the Artix 7 will be the first "spartan" type device that will > be supported under the ISE software for partial reconfiguration. > Anyone heard when the Artix 7 devices are supposed to be in > production? =A0Are we talking about a practical time frame such as 6 to > 9 months or is it being stated as a year or more? =A0Or have they only > talked about when they will be shipping "samples"? =A0I know there can > be quite a difference.Article: 149169
On Oct 5, 3:30=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > On 10/5/2010 7:47 AM, Lu=EDs Rossi wrote: > > >> 2. Learn scripting to verify the FPGA and drivers at the system level. > >> =A0 =A0 Bash, python and tcl to s > > Just a question... what kind of important tasks can be done with > > script that the vendor synthesiser (as QUartus II or ISE) cant handle? > > Run my new image overnight in the system, > while executing a certain driver command in a loop, > and send me an email if anything unexpected happens. > > =A0 =A0 =A0 =A0 =A0 -- Mike Treseler I am very noob to FPGAs.... started 2 months ago. What you mean about image and driver? Thank youArticle: 149170
On Oct 5, 12:43=A0pm, rickman <gnu...@gmail.com> wrote: > I am listening to the Xilinx webinar on partial reconfiguration and > they say the Artix 7 will be the first "spartan" type device that will > be supported under the ISE software for partial reconfiguration. > Anyone heard when the Artix 7 devices are supposed to be in > production? =A0Are we talking about a practical time frame such as 6 to > 9 months or is it being stated as a year or more? =A0Or have they only > talked about when they will be shipping "samples"? =A0I know there can > be quite a difference. There is no announced date for Artix-7 device availability at this time. Ed McGettigan -- Xilinx Inc.Article: 149171
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: ... > There is no announced date for Artix-7 device availability at this > time. Is there something announced for S6? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 149172
On Oct 5, 3:12=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > ... > > > There is no announced date for Artix-7 device availability at this > > time. > > Is there something announced for S6? > > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- With the exception of the XC6SLX4 and XC6SLX9 all devices are in production and in stock at Avnet for small quantities and 6-8 weeks times for larger quantities. http://avnetexpress.avnet.com/store/em/EMController?action=3Dproducts&N=3D0= &&term=3DXC6SLX Ed McGettigan -- Xilinx Inc.Article: 149173
On Oct 5, 5:50 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Oct 5, 12:43 pm, rickman <gnu...@gmail.com> wrote: > > > I am listening to the Xilinx webinar on partial reconfiguration and > > they say the Artix 7 will be the first "spartan" type device that will > > be supported under the ISE software for partial reconfiguration. > > Anyone heard when the Artix 7 devices are supposed to be in > > production? Are we talking about a practical time frame such as 6 to > > 9 months or is it being stated as a year or more? Or have they only > > talked about when they will be shipping "samples"? I know there can > > be quite a difference. > > There is no announced date for Artix-7 device availability at this > time. Ok, so if I understand what was said in the presentation today, there is no support for partial reconfiguration in any of the available Spartan devices, right? I remember looking into PR for quite a while some years back and had been told that Xilinx "was committed" to supporting PR in Spartan parts. That was literally 8 years ago. A lot of the presentation talked to the cost savings that was possible using PR. But that only makes sense to me if it can be used with low cost parts. Reducing the cost of using a more expensive part by using a complex process is a poor substitute to just using a part that costs less. But if I can use the less expensive part and cut my costs further by using PR, that can make a number of projects practical that otherwise wouldn't be. I don't even want to do "dynamic" PR, I just want to have the flexibility of configuring the modules when I configure the full part initially. Would that be "static" PR? This makes a huge difference in the exact scenario they described for a product with multiple interface modules, but the number of possible modules larger than just three. Instead of a 100,000 LUT Spartan, I would be able to use a 10,000 LUT device and have room to spare. This could be such a enabler of projects. RickArticle: 149174
>>2. Learn scripting to verify the FPGA and drivers at the system level. >> Bash, python and tcl to s > > >Just a question... what kind of important tasks can be done with >script that the vendor synthesiser (as QUartus II or ISE) cant handle? > > The synthesizer simply compiles the rtl into gates. You still have to verify the gates. You never build production code using a gui. You always script it. That way you can start a job before leaving and it will be done when you come back tomorrow without you having to sit there and click a mouse every few hours. It also means that you never have to worry that you forgot to check the "fix hold times" box on your final run. You will open a new design using a gui and from then on you take the command log and edit that if you need to change anything. Your verification suite should also be scripted for the same reason. --------------------------------------- Posted through http://www.FPGARelated.com
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