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I didn't even try to download it (I had enough problems downloading the smaller Altera package) so I ordered it on a DVD. It took about three weeks to arrive but installed without any problems.Article: 149226
Peter Alfke skrev: > On Oct 4, 7:27 pm, rickman <gnu...@gmail.com> wrote: >> >> Rick >> >> PS I use the computer format for dates 20101004 or preferred 101004, >> at least in my code. > > Rick, your sequence is also the official method used in Sweden. Yes, but it is actually an International Standard (ISO 8601). You would normally write "2010-10-04" for readability. "10-10-04" risk wraparound problems. All Swedish citizens (and Companies) get a personal number: "YYMMDD-XXXX" where YYMMDD is birthdate, and XXXX makes the number unique. We have elderly people that get advertisement for baby stuff after they reach 100+, since year is only two numbers. The system copes with that, since your number changes to "YYMMDD+XXXX" once you'r past 100, but it is rarely used and many/most applications does not allow you to feed in the "+" sign. > It puts the MSD at the left edge, and the LSD on the right edge, the > way we write numbers normally. > But perhaps it is too radical for the rest of the world. > Peter > Best Regards Ulf SamuelssonArticle: 149227
rickman skrev: > On Oct 5, 1:36 am, Eric Smith <space...@gmail.com> wrote: >> rickman wrote: >>> The Xilinx/ARM announcement may end up being much more interesting, >> I'm not sure why to expect it to be any more interesting than the >> Altera/ARM stuff was, or for that matter, the Xilinx/IBM stuff. As >> in, not very interesting at all. >> >> Eric > > Why was the Altera/ARM stuff not interesting? It failed because it > was so expensive, in my opinion. I expect we'll never find out from > Altera. The Actel Fusion part is also a bit pricey. You forgot to > mention the Atmel FPSLIC part (Atmel FPGA/AVR). I'm not sure if that > is still around, but it has become inconsequential because of the > price and the lack of advancement of the development tools. The FPSLIC is still in production, but since no shrink has been made, there is no long term migration path. Many of people working with the FPSLIC left and started at Actel, so mayube the Fusion stuff is really FPSLIC-2... It certainly addresses many of the concerns of the FPSLIC. 1) No Analog 2) No Flash 3) VERY limited code space (32kB max) I have seen what appears to be the perfect application for the Fusion, and it can be solved at 50% of the Fusion cost using 2 micros. If you want mixed signal CPU/FPGA devices, then you have to use the same processes as the standard micros. This makes the part too expensive. If you want to go for low cost, you go real aggressive pure digital CMOS and have to use external memory, or large SRAMs. Most companies I see that is looking for 32 bit MCUs require 256 kB - 1 MB code memory, which has to be implemented as SRAM on the chip, if you do not have a flash capable process. I think that you either have to go for application processors like ARM9 or above, or limit the FPGA to a small part of the chip for the cost to be acceptable. One problem that you face when you design such a chip, is that you need to make a family, for people to accept. You have memory size in one dimension and FPGA size in another dimension. If you have 4 different memory sizes and 3 different FPGA sizes, you will have to create 12 different masksets. This will be very expensive in 28 nm... > > The Xilinx/ARM stuff might be interesting if they actually tap the > full potential of providing a range of products to match the range of > CPUs that are available from ARM. If Xilinx just repeats what they > did with the PPC and just makes one limited line of devices then I > don't see that being especially successful either. > > Actually, I shouldn't say that. Knowing Xilinx, I expect they will > identify the markets with the most potential and design a small number > of FPGA/ARM devices tailored to those apps. One might be cell > phones. That is a potentially HUGE market and SiBlue is currently > trying to break into that area. If Xilinx combines an ARM with a low > end FPGA like the SiBlue parts, they could beat them at their own > game. Or perhaps a larger FPGA (if it is cheap enough and low power > enough) could replace some of the custom logic in a cell phone? But > mostly, Xilinx understands their core market, network comms. For them > a large FPGA combined with one or more high end ARM cores (a la Virtex- > II Pro) is what we can expect. > > If you were combining an FPGA with a CPU in a market where a number of > companies were doing that, how would you differentiate your product? > > Rick Best Regards Ulf SamuelssonArticle: 149228
It been over a year since we produced our first Spartan-6 board and we now have 3 main products, Raggedstone2, Drigmorn3 and Drigmorn4 based on Spartan-6 and now ramping up into serious volumes. Spartan-6 has become available in large numbers in lot's of variants and we are start to make other die size variants of these products available. Not to forget our customer base in the Virtex markets our Broaddown3 and Broaddown5 products are finally heading towards being available now that silicon availability in Virtex-6 is improving also. We have some plans for new products this area as well and mor n that later. The question what I would like to ask group is what you would like to see us do next in the Spartan-6 arena? John Adair Enterpoint Ltd.Article: 149229
"John Adair" <g1@enterpoint.co.uk> wrote in message news:b692dabf-22ec-4d19-aa33-79f43e6298ea@v23g2000vbi.googlegroups.com... > It been over a year since we produced our first Spartan-6 board and we > now have 3 main products, Raggedstone2, Drigmorn3 and Drigmorn4 based > on Spartan-6 and now ramping up into serious volumes. Spartan-6 has > become available in large numbers in lot's of variants and we are > start to make other die size variants of these products available. > > Not to forget our customer base in the Virtex markets our Broaddown3 > and Broaddown5 products are finally heading towards being available > now that silicon availability in Virtex-6 is improving also. We have > some plans for new products this area as well and mor n that later. > > The question what I would like to ask group is what you would like to > see us do next in the Spartan-6 arena? > > John Adair > Enterpoint Ltd. Is this y'all, here? I only had the above to go on. 8^) http://www.enterpoint.co.uk/ BillArticle: 149230
Hi,all I'm Paul Ham in Korea and have some difficulties in using ASMI_PARALLEL altera ip core. Anyone who knows well this problem could advice to me. I've used both single-byte write and page write. My problem is on "busy" signal after write operation. First, when I used page write(256 bytes) operation, the "busy" signal from ip core kept "high" during 30 us. Second I tried to use single byte write operation, however, the ip core gave me the "busy" signal during 300 us !! It's unbelievable and different from the asmi_parallel data sheet. The data sheet shows that only 3 us is needed after single byte write operation. So, I'd like to get some advice here what makes unexpected result. The signals I give asmi_parallel ip core, the write/wren/addr/data are exact. Thanks in advanced Regards Paul --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149231
On Oct 10, 8:25=A0am, John Adair <g...@enterpoint.co.uk> wrote: > It been over a year since we produced our first Spartan-6 board and we > now have 3 main products, Raggedstone2, Drigmorn3 and Drigmorn4 based > on Spartan-6 and now ramping up into serious volumes. Spartan-6 has > become available in large numbers in lot's of variants and we are > start to make other die size variants of these products available. > > Not to forget our customer base in the Virtex markets our Broaddown3 > and Broaddown5 products are finally heading towards being available > now that silicon availability in Virtex-6 is improving also. We have > some plans for new products this area as well and mor n that later. > > The question what I would like to ask group is what you would like to > see us do next in the Spartan-6 arena? I know you've expressed some concerns in the past over integrating FMC connectors on to your boards, but I'd personally put a vote in for this, especially on something like your Raggedstone2 and Broaddown boards. There is a hole in the FPGA board market right now, where it is hard to find a reasonably priced FPGA board with a PCIe interface + an FMC interface that would easily fit into a PC (i.e., doesn't come off the top of the PCB as it does on the SP605, ML605, and most of the other FMC-based FPGA boards available today). (warning: minor advertising ahead, but just for the purpose of clarifying my interests). Our company, Epiq Solutions, has finally moved our Bitshark FMC-1RX software-defined radio FMC card into production, and we've had several inquiries from folks looking for a PCIe host board solution that will easily fit into a PC (and that doesn't cost an arm and a leg). So the i/o portion of the FMC board would be positioned where the i/o side is typically oriented on a PCIe board. In our case, this would provide access to the RF inputs from outside of the host PC when the PC case is closed up. To clarify, a picture of our board can be found here (website is still in the process of being updated, but you get the idea): http://www.epiq-solutions.com/product_detail.php?line=3DBitshark&product=3D= Bitshark%20FMC So, my vote is for including FMC, at least the low-pin count variant. The connectors aren't that pricey any more, and both Samtec and Molex (I think) have them available. Regards, John www.epiq-solutions.comArticle: 149232
Hi Mike, I had assigned timing constraints for the incoming clocks. I thought you were asking about the pad to pad and FFS timing constraints. Also, i switched to xilinx 12.1 and the same design worked =) i have no idea why wasn't it working on xilinx 9.1 . But life is good now with a little problem though. When i add few signals in chipscope, my FPGA doesn't get programmed. I delete those signals and it gets programmed but now i can't debug my design =\ . It has been happening with me for quite some time now and i haven't been able to figure it out. Have you ever faced this sort of problem ? Thanks Regards SalimBaba --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149233
I'm new in FPGA field, so i have a problem.... I need a low cost FPGA able to drive a sensor with 5 LVDS DDR data sensor->FPGA 1 LVDS Clock at 300MHz sensor->FPGA 1 LVDS Clock at 300Mhz FPGA->sensor SPI FPGA->sensor in sensor evaluation board, a Virtex5 XC5VLX50T-1FFG1136C is used. I need a low cost fpga, so i thought about Spartan6 family (for example XC6SLX150T-3FGG676C). What do you think? Is it possible to obtain a 300MHz clock output from a differential IO? Any suggestion? Thanks in advanceArticle: 149234
"Indie Tinde" <indietinde@gmail.com> wrote in message news:f3b6b185-465d-487f-9bf9-4d4c57680a2d@c21g2000vba.googlegroups.com... > I'm new in FPGA field, so i have a problem.... > I need a low cost FPGA able to drive a sensor with > > 5 LVDS DDR data sensor->FPGA > 1 LVDS Clock at 300MHz sensor->FPGA > 1 LVDS Clock at 300Mhz FPGA->sensor > SPI FPGA->sensor > > in sensor evaluation board, a Virtex5 XC5VLX50T-1FFG1136C is used. I > need a low cost fpga, so i thought about Spartan6 family (for example > XC6SLX150T-3FGG676C). What do you think? Is it possible to obtain a > 300MHz clock output from a differential IO? Any suggestion? > Thanks in advance Look at Lattice XP3 - might be cheaper. Whatever you use other than just cloning the eval board will be hard work. Michael KellettArticle: 149235
On Oct 11, 5:28=A0am, "john.orla...@gmail.com" <john.orla...@gmail.com> wrote: > On Oct 10, 8:25=A0am, John Adair <g...@enterpoint.co.uk> wrote: > > > It been over a year since we produced our first Spartan-6 board and we > > now have 3 main products, Raggedstone2, Drigmorn3 and Drigmorn4 based > > on Spartan-6 and now ramping up into serious volumes. Spartan-6 has > > become available in large numbers in lot's of variants and we are > > start to make other die size variants of these products available. > > > Not to forget our customer base in the Virtex markets our Broaddown3 > > and Broaddown5 products are finally heading towards being available > > now that silicon availability in Virtex-6 is improving also. We have > > some plans for new products this area as well and mor n that later. > > > The question what I would like to ask group is what you would like to > > see us do next in the Spartan-6 arena? > > I know you've expressed some concerns in the past over integrating FMC > connectors on to your boards, but I'd personally put a vote in for > this, especially on something like your Raggedstone2 and Broaddown > boards. =A0There is a hole in the FPGA board market right now, where it > is hard to find a reasonably priced FPGA board with a PCIe interface + > an FMC interface that would easily fit into a PC (i.e., doesn't come > off the top of the PCB as it does on the SP605, ML605, and most of the > other FMC-based FPGA boards available today). > > (warning: minor advertising ahead, but just for the purpose of > clarifying my interests). =A0Our company, Epiq Solutions, has finally > moved our Bitshark FMC-1RX software-defined radio FMC card into > production, and we've had several inquiries from folks looking for a > PCIe host board solution that will easily fit into a PC (and that > doesn't cost an arm and a leg). So the i/o portion of the FMC board > would be positioned where the i/o side is typically oriented on a PCIe > board. In our case, this would provide access to the RF inputs from > outside of the host PC when the PC case is closed up. =A0To clarify, a > picture of our board can be found here (website is still in the > process of being updated, but you get the idea): > > http://www.epiq-solutions.com/product_detail.php?line=3DBitshark&produc..= . > > So, my vote is for including FMC, at least the low-pin count variant. > The connectors aren't that pricey any more, and both Samtec and Molex > (I think) have them available. > > Regards, > Johnwww.epiq-solutions.com I definitely vote for PCI-e plus ethernet. If the FPGA have transceivers for PCI-e - its a sin not to use it! I like having many places to connect additional wires/boards, but this is for ADC/DAC/VGA/ etc addition - most of the basic things have to be on the board. Kind regards, Tomas D.Article: 149236
John One of the things that we do with the Raggedstone family are customer derivative products. We actual do a lot of customer specific derivates of these boards that the general engineering community don't get to see. The DIL Headers are not just an easy low tech connection standard but a source of FPGA I/O if we need them for something else. The relatively clear areas of PCB under the headers are also not a coincidence. Have a look at the difference between the central area and under the DIL Headers of RS1 and RS2. RS3 will offer the same as well. If you have enough serious customers, and that doesn't need to be very many, we can cut and make a derivative of RS2 in a few weeks if I can make enough space in our extremely loaded assembly line. Our record for doing something more complicated that this is 18 days to handing working boards to a customer so it's very viable if we have the silicon as we already have with RS2. The RS2 LHS DIL Header has 68 I/O in it which is just about enough for a proper implementation of a LPC FMC so it sould be easy to do a derivative where we remove the LHS DIL Header and replace with a LPC FMC. There are also 3 high speed connections currently linked to SATA connectors that can also be easily canibalised and even on the right side of the Spartan-6 for routing. Cost wise there wouldn't be a hugh increase on unit cost as most parts share with the main RS2. Might be a little to cover tooling and setup etc. but that just depends on numbers. Our line can typically make batches from 1-1000 units so no problem doing a low volume run ecconomically. If this is of interest to you, or anyone else, it's worth emailing me directly. Use our general "boardsales" email and it will get to me. John Adair Enterpoint Ltd. On 11 Oct, 03:28, "john.orla...@gmail.com" <john.orla...@gmail.com> wrote: > On Oct 10, 8:25=A0am, John Adair <g...@enterpoint.co.uk> wrote: > > > It been over a year since we produced our first Spartan-6 board and we > > now have 3 main products, Raggedstone2, Drigmorn3 and Drigmorn4 based > > on Spartan-6 and now ramping up into serious volumes. Spartan-6 has > > become available in large numbers in lot's of variants and we are > > start to make other die size variants of these products available. > > > Not to forget our customer base in the Virtex markets our Broaddown3 > > and Broaddown5 products are finally heading towards being available > > now that silicon availability in Virtex-6 is improving also. We have > > some plans for new products this area as well and mor n that later. > > > The question what I would like to ask group is what you would like to > > see us do next in the Spartan-6 arena? > > I know you've expressed some concerns in the past over integrating FMC > connectors on to your boards, but I'd personally put a vote in for > this, especially on something like your Raggedstone2 and Broaddown > boards. =A0There is a hole in the FPGA board market right now, where it > is hard to find a reasonably priced FPGA board with a PCIe interface + > an FMC interface that would easily fit into a PC (i.e., doesn't come > off the top of the PCB as it does on the SP605, ML605, and most of the > other FMC-based FPGA boards available today). > > (warning: minor advertising ahead, but just for the purpose of > clarifying my interests). =A0Our company, Epiq Solutions, has finally > moved our Bitshark FMC-1RX software-defined radio FMC card into > production, and we've had several inquiries from folks looking for a > PCIe host board solution that will easily fit into a PC (and that > doesn't cost an arm and a leg). So the i/o portion of the FMC board > would be positioned where the i/o side is typically oriented on a PCIe > board. In our case, this would provide access to the RF inputs from > outside of the host PC when the PC case is closed up. =A0To clarify, a > picture of our board can be found here (website is still in the > process of being updated, but you get the idea): > > http://www.epiq-solutions.com/product_detail.php?line=3DBitshark&produc..= . > > So, my vote is for including FMC, at least the low-pin count variant. > The connectors aren't that pricey any more, and both Samtec and Molex > (I think) have them available. > > Regards, > Johnwww.epiq-solutions.comArticle: 149237
On 11 Ott, 10:42, "Michael Kellett" <nos...@nospam.com> wrote: > "Indie Tinde" <indieti...@gmail.com> wrote in message > > news:f3b6b185-465d-487f-9bf9-4d4c57680a2d@c21g2000vba.googlegroups.com... > > > I'm new in FPGA field, so i have a problem.... > > I need a low cost FPGA able to drive a sensor with > > > 5 LVDS DDR data sensor->FPGA > > 1 LVDS Clock at 300MHz sensor->FPGA > > 1 LVDS Clock at 300Mhz FPGA->sensor > > SPI FPGA->sensor > > > in sensor evaluation board, a Virtex5 XC5VLX50T-1FFG1136C is used. I > > need a low cost fpga, so i thought about Spartan6 family (for example > > XC6SLX150T-3FGG676C). What do you think? Is it possible to obtain a > > 300MHz clock =A0output from a differential IO? Any suggestion? > > Thanks in advance > > Look at Lattice XP3 - might be cheaper. Whatever you use other than just > cloning the eval board will be hard work. Thanks for infos, i'll take a look...you're right, but i think could be an harder work if i use an fpga of another factory with another ise,ecc...Virtex5 is expensive, so i look for Virtex6 or Spartan6 (more cheaper), but i'm not really sure that a Spartan6 can be used with this sensor..any help?Article: 149238
To some extent we can already do this with our Ethernet add-on modules. There is a plan for a Gigabit add-on module as well but no timescale on that as yet. In the higher performance area our Broaddown3 and Broaddown5 that are just going into production have Gigabit capability built in. John Adair Enterpoint Ltd. On 11 Oct, 10:09, Socrates <mail...@gmail.com> wrote: > On Oct 11, 5:28=A0am, "john.orla...@gmail.com" <john.orla...@gmail.com> > wrote: > > > > > On Oct 10, 8:25=A0am, John Adair <g...@enterpoint.co.uk> wrote: > > > > It been over a year since we produced our first Spartan-6 board and w= e > > > now have 3 main products, Raggedstone2, Drigmorn3 and Drigmorn4 based > > > on Spartan-6 and now ramping up into serious volumes. Spartan-6 has > > > become available in large numbers in lot's of variants and we are > > > start to make other die size variants of these products available. > > > > Not to forget our customer base in the Virtex markets our Broaddown3 > > > and Broaddown5 products are finally heading towards being available > > > now that silicon availability in Virtex-6 is improving also. We have > > > some plans for new products this area as well and mor n that later. > > > > The question what I would like to ask group is what you would like to > > > see us do next in the Spartan-6 arena? > > > I know you've expressed some concerns in the past over integrating FMC > > connectors on to your boards, but I'd personally put a vote in for > > this, especially on something like your Raggedstone2 and Broaddown > > boards. =A0There is a hole in the FPGA board market right now, where it > > is hard to find a reasonably priced FPGA board with a PCIe interface + > > an FMC interface that would easily fit into a PC (i.e., doesn't come > > off the top of the PCB as it does on the SP605, ML605, and most of the > > other FMC-based FPGA boards available today). > > > (warning: minor advertising ahead, but just for the purpose of > > clarifying my interests). =A0Our company, Epiq Solutions, has finally > > moved our Bitshark FMC-1RX software-defined radio FMC card into > > production, and we've had several inquiries from folks looking for a > > PCIe host board solution that will easily fit into a PC (and that > > doesn't cost an arm and a leg). So the i/o portion of the FMC board > > would be positioned where the i/o side is typically oriented on a PCIe > > board. In our case, this would provide access to the RF inputs from > > outside of the host PC when the PC case is closed up. =A0To clarify, a > > picture of our board can be found here (website is still in the > > process of being updated, but you get the idea): > > >http://www.epiq-solutions.com/product_detail.php?line=3DBitshark&produc.= .. > > > So, my vote is for including FMC, at least the low-pin count variant. > > The connectors aren't that pricey any more, and both Samtec and Molex > > (I think) have them available. > > > Regards, > > Johnwww.epiq-solutions.com > > I definitely vote for PCI-e plus ethernet. If the FPGA have > transceivers for PCI-e - its a sin not to use it! I like having many > places to connect additional wires/boards, but this is for ADC/DAC/VGA/ > etc addition - most of the basic things have to be on the board. > > Kind regards, > Tomas D.Article: 149239
> I have been using Wiznet in a number of 'in production' designs for > the last 4 years. Currently the W5300 or module with the same would be > the best choice. I evaluated the other options but required > 50Mb/s > and ability to use only UDP (harsh industial heavy welding > environments along with real time data meant TCP retries would not be > desirable to say the least). > A few registers to set up (from the client side) and thereafter it's > akin to FTDI. Thanks David, it's an industrial environment this is going into so this is useful to know. Nial.Article: 149240
On Mon, 11 Oct 2010 02:30:44 -0700 (PDT), John Adair <g1@enterpoint.co.uk> wrote: >To some extent we can already do this with our Ethernet add-on >modules. There is a plan for a Gigabit add-on module as well but no >timescale on that as yet. > >In the higher performance area our Broaddown3 and Broaddown5 that are >just going into production have Gigabit capability built in. > These don't appear to be on the website ... is there any information about them yet? - BrianArticle: 149241
> It's unbelievable and different from the asmi_parallel data sheet. > The data sheet shows that only 3 us is needed after single byte write > operation. > So, I'd like to get some advice here what makes unexpected result. > The signals I give asmi_parallel ip core, the write/wren/addr/data are > exact. I'd check the data sheet for whatever flash device you're using, that will be what determines the delay (mostly), not the core. Nial.Article: 149242
Hi Everyone, I am designing a system where I am interfacing a Motorolla processor in my system for read and write data. This processor is on the board where my fpga will interact with it. The processor is the master mode always and the salave is my interface design and the fpga. The motoroll Processor will have LBC Local bus controller signals will be comunicating to my interface inside the FPGA. The processor can run at configurable clock of 33 MHz to 133 MHz. The address bus is 24 Bits and tye data bus is 32 bits. I have to design an interface where the control signals from the processor to my interface will be 1. LALE Used for latching address and making is two distict phases as data and address phase. The LALE when HIgh is an Address phase and when Address is low it is Data phase. (From processor to Design ) 2. LWE it is a read and write signal single bit active low. (From processor to Design ) 3. LOE Output enable active low (From processor to Design ) 4. LCS is active low signal from processor to my interface. It is used for selecting the chip/slave chip select 5. LA address 24 bits ( From processor to Design ) 6. LAD data 32 bits (Bidirectional) I am thinking about runing my design at 300 Mhx 3X then the processor LBC clock . The LBC clock is not coming from the processor to my interface in fpga . So in my Interface i dont have the reference clock from the processor and all the above mentioned signals are from Processor to my design except LAD which is bidirectional . I am using 2 flop synchronisers for the control signals and MUX-Latch model for data latching and synchronization across the cock domain . My Confusion is that when we have multiple control signal passing the clock domain . Can we synchronize with 2 flops all the control signals. Shall we use some glue logic to make sure we pass and synchronise only one control signal across the domain and later use this synchronous signal value to select the mux-latch of other control signals that are input to a latch and sampled when we get the synchronized signal. In the scenario like this has anyone used multiple control signals to pass the clock domain throgh individual 2 flop synchronizers for each control lines. I am using 3X clock in the destination clock domain and has ample time to sample the signal in the interface block. Any suggestion ideas will be highly appreciated Thanks VipulArticle: 149243
Hello All, I am new in this forum. I would like to ask if there is a way to calculate the SFDR in FPGA. I have limited resources in the FPGA, so calculating the FFT is not so preferable. knowing that my bandwidth is around 1.5 GHz. my main goal is to evaluate the ADC, SFDR specifically. any idea is appreciated. Mile --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149244
Basically yes you can do this in a Spartan-6. The I/O will run this fast. You probably want to either use the DDR or serdes features at the I/O to drop the internal data rates down to 150MHz or lower but that would probably work well for what you are doing. Now the product plug. You can try this on any of our range of Spartan-6 development boards http://www.enterpoint.co.uk/boardproducts.html= . we have significant support for LVDS in all of these. John Adair Enterpoint Ltd. On 11 Oct, 08:57, Indie Tinde <indieti...@gmail.com> wrote: > I'm new in FPGA field, so i have a problem.... > I need a low cost FPGA able to drive a sensor with > > 5 LVDS DDR data sensor->FPGA > 1 LVDS Clock at 300MHz sensor->FPGA > 1 LVDS Clock at 300Mhz FPGA->sensor > SPI FPGA->sensor > > in sensor evaluation board, a Virtex5 XC5VLX50T-1FFG1136C is used. I > need a low cost fpga, so i thought about Spartan6 family (for example > XC6SLX150T-3FGG676C). What do you think? Is it possible to obtain a > 300MHz clock =A0output from a differential IO? Any suggestion? > Thanks in advanceArticle: 149245
"kadhiem_ayob" <kadhiem_ayob@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> writes:
>A 16qam signal is upsampled by 2 and shaped by root raised cosine. At the
>Rx it is matched-filtered with same rrcos filter and decimated by 2 to get
>the symbols.
>All looks ok. Symbols are recovered clean.
>However, the decimation leads to two phases i.e. depending on which samples
>you choose from the decimator output(even or odd), only one phase is the
>correct symbols. The question is: is there a way to choose even or odd
>correctly without eyeballing? or do we need some logic to work it out?
You need some additional help to find the right phase. This can be a defined
phase reference/training symbol in regular intervals and/or by looking at the BER
of an overlayed error correction. There are also some scrambling LFSRs that
produce multiple bits per input bit and are self synchronizing in the
descrambler. AFAIK the DSS WLAN (11Mbit) uses such a scrambler.
DVB-S demodulators try to find the sync byte pattern (0x47 every 204 bytes, the
8th sync byte is inverted) and the right FEC depuncturing setup simply by trying
the phases and all the FEC variants. If the BER after the Reed-Solomon decoder is
low enough and the 7*0x47+0xb8 pattern is found a few times, then a full lock is
assumed.
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 149246On Oct 11, 7:24=A0am, "Mile" <skymoon_h2s@n_o_s_p_a_m.hotmail.com> wrote: > Hello All, > > I am new in this forum. > I would like to ask if there is a way to calculate the SFDR in FPGA. > I have limited resources in the FPGA, so calculating the FFT is not so > preferable. > knowing that my bandwidth is around 1.5 GHz. > > my main goal is to evaluate the ADC, SFDR specifically. > > any idea is appreciated. > > Mile > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com First, a couple of questions: 1) What are your test conditions? 2) Do you really have a bandwidth of 1.5 GHz? If so, how will you process that much BW in an FPGA? Seems to me that you should just find a way to capture the ADC samples and post process them using a standard software tool (e.g., Matlab). Also, you should post your question to comp.dsp. Darol KlawetterArticle: 149247
>"kadhiem_ayob" <kadhiem_ayob@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> writes: >>A 16qam signal is upsampled by 2 and shaped by root raised cosine. At the >>Rx it is matched-filtered with same rrcos filter and decimated by 2 to get >>the symbols. >>All looks ok. Symbols are recovered clean. >>However, the decimation leads to two phases i.e. depending on which samples >>you choose from the decimator output(even or odd), only one phase is the >>correct symbols. The question is: is there a way to choose even or odd >>correctly without eyeballing? or do we need some logic to work it out? > >You need some additional help to find the right phase. This can be a defined >phase reference/training symbol in regular intervals and/or by looking at the BER >of an overlayed error correction. There are also some scrambling LFSRs that >produce multiple bits per input bit and are self synchronizing in the >descrambler. AFAIK the DSS WLAN (11Mbit) uses such a scrambler. > >DVB-S demodulators try to find the sync byte pattern (0x47 every 204 bytes, the >8th sync byte is inverted) and the right FEC depuncturing setup simply by trying >the phases and all the FEC variants. If the BER after the Reed-Solomon decoder is >low enough and the 7*0x47+0xb8 pattern is found a few times, then a full lock is >assumed. > >-- > Georg Acher, acher@in.tum.de > http://www.lrr.in.tum.de/~acher > "Oh no, not again !" The bowl of petunias Many thanks Georg already I have logic that searches for byte boundary and quadrant boundary. I never thought that matched filter need be included in the search but It makes sense. Kadhiem > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149248
Hi, I have a weird problem with my design. I am using xilinx 12.1 for its synthesis and implementation. The problem is that when i generate my bitstream with a chipscope core inserted in the design and program my FPGA, programming fails saying that "DONE did not go high" whereas when i take out the chipscope core or some signals from the core, programming succeeds but after that my JTAG stops working. If i try ti initialize JTAG chain in iMPACT it asks me whether i have a BSDL or BIT file for this device or if i try to run chipscope,it also gives a warning and doesn't start. I checked the JTAG voltages and they were fine. Rarely does my design work, so, i am kind of stuck here as i cannot debug my system altogether. Is there something wrong with the Bit file or my usb drivers? I tried reinstalling the drivers but didn't work. Then i reinstalled xilinx 12.1,still same problem. Does it happen because of the size of the FPGA and the complexity of the logic we are inserting in it ? I mean that if the FPGA is not big enough to hold the logic and it's a very tigh fit, can it lead to such behaviour ? Regards SalimBaba --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149249
On Oct 11, 3:16=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I have a weird problem with my design. I am using xilinx 12.1 for its > synthesis and implementation. > The problem is that when i generate my bitstream with a chipscope core > inserted in the design and program my FPGA, programming fails saying that > "DONE did not go high" whereas when i take out the chipscope core or some > signals from the core, programming succeeds but after that my JTAG stops > working. If i try ti initialize JTAG chain in iMPACT it asks me whether i > have a BSDL or BIT file for this device or if i try to run chipscope,it > also gives a warning and doesn't start. I checked the JTAG voltages and > they were fine. > > Rarely does my design work, so, i am kind of stuck here as i cannot debug > my system altogether. Is there something wrong with the Bit file or my us= b > drivers? I tried reinstalling the drivers but didn't work. Then i > reinstalled xilinx 12.1,still same problem. > > Does it happen because of the size of the FPGA and the complexity of the > logic we are inserting in it ? I mean that if the FPGA is not big enough = to > hold the logic and it's a very tigh fit, can it lead to such behaviour ? > > Regards > SalimBaba =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com One obvious thing that can happen when you put a lot of logic in an FPGA is that the core power supply might not be strong enough to source the required dynamic power. You can get an estimate of the power requirements using Xpower and make sure your power source can handle the current. You can also put an oscilloscope on the Vccint near an FPGA pin or ball, and trigger on a low-going spike. This might either show that your supply cannot handle the current (usually when the spike goes very low or stays low for a long time) or that you have insufficient bypass caps to handle the sudden load increase. Typically right after configuration there is a sudden large rise in Vccint supply current requirement. One thing you might see when the supply cannot handle the load is that the FPGA starts up, gets a glitch in internal power, and then goes back to its power-on reset state due to internal power monitoring. Then the power supply comes back up to voltage because in this state the FPGA again takes much less current. Regards, Gabor
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