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Messages from 14975

Article: 14975
Subject: Re: 4002A .bit -> .hex
From: Brian Boorman <XZY.bboorman@harris.com>
Date: Mon, 01 Mar 1999 12:13:26 -0500
Links: << >>  << T >>  << A >>
If you already have a .bit file, then using (command line) promgen
utility should convert it to .hex.
From a DOS prompt (assuming Xilinx tools are in your path) just type
promgen -h to get a list of the options.

For instance,

promgen -p mcs -o mydesign.mcs -s _prom_size_in_Kbytes -u _start_address
mydesign.bit

will convert mydesign.bit to mydesign.mcs, starting at _start_address,
going up, targeted to a prom which is of the size _prom_size_in_Kbytes.

Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>

Steve Vallerand wrote:
> 
> Hi,
> 
> 2 years ago, I have done a project using a FPGA (XC4002A). All work fine
> and I presently looking to put my .bit in a serial ROM. Presently, I
> download each time the .bit file using the serial port. But, I have to
> format the .bit to a .hex file accepted by the ROM programmer. My problem
> is that new Xilinx software don't support XC4002A and I am not able to
> transform my .bit to a .hex file. Anyone can help me???
> 
> Steve Vallerand
> svallera@gel.ulaval.ca

--
Article: 14976
Subject: graphic Lcd control core
From: "saffary" <saffary@club-internet.fr>
Date: Mon, 1 Mar 1999 19:54:24 +0100
Links: << >>  << T >>  << A >>
Does anyone have a lcd cntrol core, and ,or info about this.

Thanks


Article: 14977
Subject: Re: graphic Lcd control core
From: Ray Andraka <randraka@ids.net>
Date: Mon, 01 Mar 1999 14:04:21 -0500
Links: << >>  << T >>  << A >>
The specifics by display and by application vary enough to make it
unlikely that a specific core will meet your requirements.  Design of an
LCD controller is fortunately fairly straightforward and is usually not
to challenging timing-wise.  If the display does not have a low level
controller on it, the most important thing is to be sure there is no DC
component on the drive signals.  Most simple displays require the
controller designer to take care of this.  Many of the larger displays
have an internal low level controller that accepts an input not much
different than a CRT display.

saffary wrote:

> Does anyone have a lcd cntrol core, and ,or info about this.
>
> Thanks



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 14978
Subject: CFP: Crypto Workshop
From: Christof Paar <christof@ece.wpi.edu>
Date: Mon, 1 Mar 1999 14:16:27 -0500
Links: << >>  << T >>  << A >>
In order to receive future announcements about the CHES workshop,
subscribe to the mailing list by sending a brief mail to ches@ece.orst.edu

--------------------------------------------------------------------------
         WORKSHOP ON CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS (CHES)
                    http://ece.WPI.EDU/Research/crypt/ches

                       Worcester Polytechnic Institute
                        Worcester, Massachusetts, USA
                            August 12 & 13, 1999

                           Second Call for Papers

General Information

The focus of this workshop is on all aspects of cryptographic hardware and
embedded system design. The workshop will be a forum of new results from th=
e
research community as well as from the industry. Of special interest are
contributions that describe new methods for efficient hardware
implementations and high-speed software for embedded systems, e.g., smart
cards, microprocessors, DSPs, etc. We hope that the workshop will help to
fill the gap between the cryptography research community and the applicatio=
n
areas of cryptography. Consequently, we encourage submission from academia,
industry, and other organizations. All submitted papers will be reviewed.

The topics of interest include but are not limited to:

   * Computer architectures for public-key cryptosystems
   * Computer architectures for secret-key cryptosystems
   * Reconfigurable computing and applications in cryptography
   * Cryptographic processors and co-processors
   * Modular and Galois field arithmetic architectures
   * Tamper resistance on the chip and board level
   * Architectures for smart cards
   * Tamper resistance for smart cards
   * Efficient algorithms for embedded processors
   * Special-purpose hardware for cryptanalysis
   * Fast network encryption
   * True and pseudo random number generators

Mailing List

If you want to receive emails with subsequent Call for Papers and=20
registration information, please send a brief mail to ches@ece.orst.edu.=20

Instructions for Authors

Authors are invited to submit original papers. The preferred submission for=
m
is by electronic mail to ches@ece.orst.edu. Papers should be formatted in
12pt type and not exceed 12 pages (not including the title page and the
bibliography). The title page should contain the author's name, address
(including email address and an indication of the corresponding author), an
abstract, and a small list of key words. Please submit the paper in
Postscript or PDF. We recommend that you generate the PS or PDF file using
LaTeX, however, MS Word is also acceptable. All submissions will be
refereed.

Only original research contributions will be considered. Submissions must
not substantially duplicate work that any of the authors have published
elsewhere or have submitted in parallel to any other conferences or
workshops that have proceedings.

Workshop Proceedings

The post-proceedings will be published in Springer-Verlag's Lecture Notes=
=20
in Computer Science (LNCS) series. Notice that in order to be included
in the proceedings, the authors of an accepted paper must guarantee to
present their contribution at the workshop.=20

Important Dates

 Submission Deadline:          April 30th, 1999.
 Acceptance Notification:      June 15th, 1999.
 Final Version due:            July 15th, 1999.
 Workshop:                     August 12th & 13th, 1999.
=20
NOTES: The CHES dates August 12 & 13 are the Thursday & Friday preceding
       CRYPTO '99 which starts on August 15.

Invited Speakers

Dale Hopkins, Compaq - Atalla, USA.

Brian Snow, National Security Agency, USA.

Eberhard von Faber, Debis IT Security Services, Germany.
  "Evaluation Schemes for Financial Organizations."

Colin D. Walter, Computation Department - UMIST, U.K.
  "An Overview of Montgomery's Multiplication Technique:=20
   How to make it Smaller and Faster."

Program Chairs

All correspondence and/or questions should be directed to either of the
Program Chairs:

 Cetin Kaya Koc                       Christof Paar
 Dept. of Electrical & Computer       Dept. of Electrical & Computer
 Engineering                          Engineering
 Oregon State University              Worcester Polytechnic Institute
 Corvallis, Oregon 97331, USA         Worcester, MA 01609, USA
 Phone: +1 541 737 4853               Phone: +1 508 831 5061
 Fax: +1 541 737 1300                 Fax: +1 508 831 5491
 Email: Koc@ece.orst.edu              Email: christof@ece.wpi.edu

Program Committee

Gordon Agnew,  University of Waterloo, Canada
David Aucsmith,   Intel Corporation, USA
Ernie Brickell,  CertCo, USA
Wayne Burleson,   University of Massachusetts at Amherst, USA
Burt Kaliski,   RSA Laboratories, USA
Jean-Jacques Quisquater,   Universit=E9 Catholique de Louvain, Belgium
Christoph Ruland,   University of Siegen, Germany
Victor Shoup,   IBM Research, Switzerland
Michael Wiener,   Entrust Technologies, Canada

Location

WPI is in Worcester, the second largest city in New England. The city is 80
km (50 miles) West of Boston and 280 km (175 miles) North-East of New York
City.

Worcester is home to a wealth of cultural treasures, many of which are just
a short distance from WPI. These include the historic Higgins Armory Museum=
,
which houses one of the world's largest collections of armor; the EcoTarium
(formerly New England Science Center), one of the only museums in the
country dedicated to environmental education; and the beautifully restored
Mechanics Hall, one of America's finest concert halls. The Worcester Art
Museum, holding one of the nation's finest collections, and the
world-renowned American Antiquarian Society, with the largest collection of
items printed during the nation's colonial period, are within two blocks of
the WPI campus. Worcester is also well known for its ten colleges, which
cooperate through the Colleges of Worcester Consortium.

Recreation areas within easy driving distance include Boston and Cape Cod t=
o
the east, the White and Green mountains to the north, and the Berkshires to
the west.

August weather in New England is usually very pleasant with average
temperatures of 20 C (70 F).

Workshop Sponsors

This workshop has received generous support from Advanced Communications In=
c.,=20
Compaq - Atalla Security Products, Intel, SECUNET, and SITI. The organizers=
=20
express their sincere thanks.


Article: 14979
Subject: PC for CAD
From: "Steve" <reply.through.newsgroup@paranoid.com>
Date: Mon, 01 Mar 1999 21:21:59 GMT
Links: << >>  << T >>  << A >>
I trust this isn't too far off topic?

I am upgrading my PC.
Which would be best for Xilinx PAR, Active-VHDL sim etc.

Pentium II Xeon
Pentium III
or AMD-K3 (with 256K L2 cache!)


Thanks

Steve


Article: 14980
Subject: Re: newbie questions
From: j5rson@frontiernet.net (Jeff Iverson)
Date: 1 Mar 1999 21:39:24 GMT
Links: << >>  << T >>  << A >>
Check this book out:

VHDL for Programmable Logic
http://www.amazon.com/exec/obidos/ASIN/0201895730/iversonsoftwarecA

On Sat, 27 Feb 1999 15:45:52 -0600, francesco l spadini
<spadini@students.uiuc.edu> wrote:

>Lastly, what other good sources (urls or book titles would be
>much appreciated) would you recommend for learning more about programmable
>logic and VHDL.

Kind Regards,
Jeff Iverson
-- 
Iverson Software Co.  507-235-9209 - voice
418 N. State St. #7   507-235-8835 - fax
Fairmont MN  56001    http://www.iversonsoftware.com/

Article: 14981
Subject: Re: JTAG HANG UP......
From: bibico <pobox303@usa.net>
Date: Mon, 01 Mar 1999 23:19:04 +0100
Links: << >>  << T >>  << A >>
Hold TMS high and
even if you pick up noise on TCK in five cycles you can be sure to be in
the JTAG reset state.

Mike H. wrote:

> Jim wrote in message <36D4AA69.E95CB74@erols.com>...
> >Any folks run into any JTAG gotchas with pulling up the
> >tdi and tclk pins?
>
> The only problems I've experienced have been with the
> /TRST pin, which seems to be interpreted differently
> by different devices. Some like it pulled up when the
> JTAG port isn't being used, some like it pulled down.
> Can lead to operational inconsistencies.
>
> Mike H.



Article: 14982
Subject: WTB: MPA1036DH FPGAs
From: Michal <michal@mytekdigital.com>
Date: 1 Mar 1999 23:20:42 GMT
Links: << >>  << T >>  << A >>
We are looking to buy some of these Motorola FPGA's (160PQFP) . If you
have surplus stock please contact Michal @ 212-9625404

Article: 14983
Subject: Re: Problem with xilinx M1
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 1 Mar 1999 16:56:19 -0700
Links: << >>  << T >>  << A >>
Sergio A. Cuenca Asensi wrote in message <36DA688C.74D9818A@dtic.ua.es>...
>
>Andy Peters wrote:
>
>> Sergio A. Cuenca Asensi wrote:
>>
>> > Yes, I've synthesized all three as top-level modules.  I want three
independent
>> > modules but without starpup blocks, the problem is that I can't find
any option
>> > in FPGA express to avoid startup adding to them. Do you know where is
it?
>>
>> I'm not sure you can have a chip with more than one top-level module!
>>
>> Why would you want to do that????
>>
>> -andy
>
>I am using FPGA Express v2.0 and Xilinx Foundationv1.4. We use mixed mode
entry
>(schematic+vhdl), really I don't want three top-level modules but it is the
only way
>to synthetize an independent module in Express. The idea is create a
"library" of
>synthesized vhdl modules, then I could instantiate the macros like a
component from
>the schematic.
>But the problem is that every module synthetized include a startup, so I
only can
>instatiate a module. I have to integrate all vhdl files of the design in a
top-level
>module and sinthesize again.


Wellllllll....I see.

To be honest, I'm not sure if you can create a "library" the way you want.

Perhaps you'd be better off creating macros for each of your sources for
each design.  What happens if you synthesize for an XC4005E and you decide
to use a different family? you have to resynthesize, anyway.

The synthesis, IMHO, takes less time than the place-and-route.  So, I
wouldn't bother trying to create a pre-synthesized library.  Just reuse the
sources.

-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

Don't waste apostrophes!  The plural of the acronym for "personal computers"
is PCs, NOT PC's.



Article: 14984
Subject: Re: Problem with xilinx M1
From: Hobson Frater <hobson@xilinx.com>
Date: Mon, 01 Mar 1999 16:47:06 -0800
Links: << >>  << T >>  << A >>
Sergio,

Correct me if I'm wrong, but it seems to me that you have a top level
schematic and want to instantiate VHDL modules on that schematic.  In
the Foundation 1.4 flow, FPGA Express was a stand alone tool.  You would
therefore have to synthesize your code to an XNF file and instantiate
that XNF on the schematic.  I believe your problem lies in the fact that
you're synthesizing the code as a "top level".  This means that Express
will insert your I/O buffers and pads for you.  It also means that
Express will try to insert the STARTUP block in your design (if
appropriate).  What I believe you really want to do is synthesize your
code as a "macro" instead of a "top level."  To do that, you must check
the option that says "Do not insert I/O pads".  This will also keep
Express from inserting the STARTUP block.  This option is available when
you "implement" in Express.

After creating the XNF file in Express, go into Foundation Schematic
Capture and choose Hierarchy -> Create Macro Symbol From Netlist.  This
will create a component that can be instantiated on your schematic that
is also linked to the XNF file.  However, it will be considered a black
box so you can't descend into it.

As for the discussion about whether or not to create libraries, I'll let
you and Andy sort that one out...

Regards,
Hobson Frater
Xilinx Applications

Article: 14985
Subject: WTB: OTP 87C51
From: Michal <michal@mytekdigital.com>
Date: 2 Mar 1999 00:48:51 GMT
Links: << >>  << T >>  << A >>
We need 50-100pcs in DIP40.
If you have surplus stock please email or contact Michal @ 212-9625404
Article: 14986
Subject: ALTERA pin assignment
From: Brett George <b.george@clarityeq.com>
Date: Tue, 02 Mar 1999 10:53:06 +1000
Links: << >>  << T >>  << A >>
hi all,

I'm sure this topic has come up before, and I assure you I know about
deja-news.
I have just finished an altera design (MAX7000), and about to layout the
design in
the schematic. I am quickly learning that I cannot assign the pins
exactly where I
would like, so I am forced to ask should I be assigning pins at all?
If I desire some grouping, should I just specify the LAB I would like
some
outputs/inputs to be in?
Does such decisions radically affect the timing of operation (and make
it
less reliable), or is it simply more difficult for the compiler to route
a sol'n.
I foresee that if I do wish to have a consistent pin layout, I will have
to lock
all the pins into place, even if it is in the positions the compiler
chooses.

If some one can identify a question in this babble, or has any comments
I would
be interested to hear them.

Brett.

Article: 14987
Subject: Re: ALTERA pin assignment
From: terry.harris@iname.com (Terry Harris)
Date: Tue, 02 Mar 1999 04:18:49 GMT
Links: << >>  << T >>  << A >>
Brett George <b.george@clarityeq.com> wrote:

>would like, so I am forced to ask should I be assigning pins at all?
>If I desire some grouping, should I just specify the LAB I would like
>some outputs/inputs to be in?
>Does such decisions radically affect the timing of operation (and make
>it less reliable), or is it simply more difficult for the compiler to route
>a sol'n. I foresee that if I do wish to have a consistent pin layout, I will have
>to lock all the pins into place, even if it is in the positions the compiler
>chooses.

>If some one can identify a question in this babble, or has any comments
>I would be interested to hear them.

Good luck. You have to lock down pins or the part won't fit the PCB
next time you compile will it.

I have seen Maxplus refuse to place a 7128 with locked pins after tiny
changes internal changes. Fiddling with fitter options and internal
logic some more eventually created a fit that still matched the PCB. 

You are significantly more likely to run into problems when the part
is nearly full. 

I would let the fitter do the job first then look carefully at the
report file. Understand the fitting restrictions. A function might not
fit in a particular LAB because not enough shared pterms or expanders
are available in that lab. Functions may need to go on particular pins
because of shared pterms. A combination of functions might not go into
a particular lab because of the limit of 32 signals from the global
routing pool (think that's right, been a while since I used 7000's). 

Sometimes you can get round these problems with a soft buffers or
lcells if you can afford the space and delay. 

There is no easy answer. You have try to get what you think it a good
fit then go for it and hope any future changes will still fit the same
pins. 

Best advice is try to understand what the fitter report is telling
you. 
Cheers Terry...
Article: 14988
Subject: LCD driver
From: vitalyh@hotmail.com
Date: Tue, 02 Mar 1999 11:03:51 GMT
Links: << >>  << T >>  << A >>
Hi,

I wrote BCD-to-7Segment driver for LCD, something like 74HC/HCT4543.
When I synthesize it in Warp, everything is fine. But  Altera Max+II 9.01
gives it a hard time. There are 590(!) warning messages with Flex rules and
the device doesn't work at all. How can I change the design to satisfy
Altera?

------------------------
---- bcd to lcd --------
------------------------
library ieee ;
use ieee.std_logic_1164.all ;
entity aldera10 is
   port ( bcd           : in integer range 0 to 9     ;
          lt, rbi, pol  : in std_logic                      ;
          abcdefg       : buffer std_logic_vector (6 downto 0) ;
          rbo           : buffer std_logic                   ) ;
end aldera10 ;
architecture arc_aldera10 of aldera10 is
begin
   process(lt,rbi,pol,bcd)
   begin
     if (lt='1' and pol='1') then
        abcdefg <= "1111111" ;
        rbo <= '0' ;
     elsif (lt='1' and pol='0') then
         abcdefg <= "0000000" ;
         rbo <= '0' ;
     elsif (rbi='0' and pol='1') or (rbi='1' and bcd/=0 and pol='1') then
        if bcd = 0 then
              abcdefg <= "1111110" ;
        elsif bcd = 1 then
              abcdefg <= "0110000" ;
        elsif bcd =  2 then
              abcdefg <= "1101101" ;
        elsif bcd = 3 then
              abcdefg <= "1111001" ;
        elsif bcd = 4 then
              abcdefg <= "0110010" ;
        elsif bcd = 5 then
              abcdefg <= "1011011" ;
        elsif bcd = 6 then
              abcdefg <= "1011111" ;
        elsif bcd = 7 then
              abcdefg <= "1110000" ;
        elsif bcd = 8 then
              abcdefg <= "1111111" ;
        elsif bcd = 9 then
              abcdefg <= "1111011" ;
        else
              abcdefg <= "1011011" ;     -- for invalide values
   end if ;
   rbo <= '0' ;
     elsif (rbi='0' and pol='0') or (rbi='1' and bcd/=0 and pol='0') then
      if bcd = 0 then
           abcdefg <= "0000001" ;
     elsif bcd = 1 then
           abcdefg <= "1001111" ;
     elsif bcd =  2 then
           abcdefg <= "0010010" ;
     elsif bcd = 3 then
           abcdefg <= "0000110" ;
     elsif bcd = 4 then
           abcdefg <= "1001100" ;
     elsif bcd = 5 then
           abcdefg <= "0100100" ;
     elsif bcd = 6 then
           abcdefg <= "0100000" ;
     elsif bcd = 7 then
           abcdefg <= "0001111" ;
     elsif bcd = 8 then
           abcdefg <= "0000000" ;
     elsif bcd = 9 then
           abcdefg <= "0000100" ;
     else
           abcdefg <= "0100100" ;     --for invalide values
    end if;
    rbo <='0' ;
     elsif (rbi='1' and bcd=0 and pol='0') then
         abcdefg <= "1111111" ;
       rbo <= '1' ;
     elsif (rbi='1' and bcd=0 and pol='1') then
         abcdefg <= "0000000" ;
       rbo <= '1' ;
   end if ;
end process;
end arc_aldera10;

---------------------------- --- bcd to_lcd ( 3 in 1)----
---------------------------- library ieee ; use ieee.std_logic_1164.all ;
entity aldera100 is  port ( bcd1, bcd2, bcd3  : in integer range 0 to 9  ; 
lt, rbi, pol  : in std_logic  ;  abcdefg1, abcdefg2, abcdefg3 : buffer
std_logic_vector (6 downto 0)); end aldera100 ; architecture arc_aldera100 of
aldera100 is component aldera10  port ( bcd  : in integer range 0 to 9	; 
lt, rbi, pol  : in std_logic  ;  abcdefg  : buffer std_logic_vector (6 downto
0) ;  rbo  : buffer std_logic  ) ; end component ;

  signal  rbi2, rbi3  : std_logic ;
begin
 lcd1: aldera10 port map(bcd1,lt,rbi ,pol,abcdefg1,rbi2 ) ;
 lcd2: aldera10 port map(bcd2,lt,rbi2,pol,abcdefg2,rbi3 ) ;
 lcd3: aldera10 port map(bcd3,lt,rbi3,pol,abcdefg3,open ) ;
end arc_aldera100;
regards,
Vitaly.

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 14989
Subject: CFP: Engineering of Reconfigurable Hardware/Software Objects
From: Toomas Plaks <T.Plaks@reading.ac.uk>
Date: Tue, 02 Mar 1999 12:32:10 +0000
Links: << >>  << T >>  << A >>
EXTENDED DEADLINE:

=======================



Dear Colleague,


You are invited to submit a paper for the Technical Session:

"Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)"

of the 1999 International Conference on Parallel and Distributed
Processing Techniques and Applications (PDPTA'99), June 28 -- July 1,
1999, 
Monte Carlo Resort, Las Vegas, Nevada, USA.


Please forward this message to your department members and all
interested 
colleagues.

I apologise if you receive multiple copies.

Yours sincerely, 

   Toomas P. Plaks

Session Co-chair

========================================================================


Call for Papers: 
----------------

Technical Session:

Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)
------------------------------------------------------------------
http://www.cs.rdg.ac.uk/cs/research/pedal/events/pdpta.html


of

The 1999 International Conference on Parallel and Distributed
Processing Techniques and Applications (PDPTA'99):
http://www.cps.udayton.edu/~pan/pdpta/.

June 28 -- July 1, 1999
Monte Carlo Resort, Las Vegas, Nevada, USA



There has been a growing interest in using reconfigurable computing
platform 
(FPGAs) for the design of application-specific computer systems (e.g. 
for multimedia application) as well as particular dedicated systems
(e.g. for 
specific tasks in computer vision and signal processing).
An important issue is the development of hardware/software codesign 
methodology that provides the designer with flexible tools for mapping 
different algorithms into FPGAs. The mapping methodology must take into 
account different parameters: 
	
	* problem parameters (size of problem)
	* real-time parameters (latency, throughput rate)
	* hardware parameters (structural properties, scalability)

and provide reconfigurable and parametrizable objects. There are 
different approaches for describing and representing  algorithms 
and for mapping them onto reconfigurable hardware environment, 
for example:

	* logical specification and refinement
	* polytope model and systolic arrays
	* dataflow models

This technical session focuses on the methods to provide reconfigurable 
objects for reconfigurable computing, i.e. finding hardware parameters 
that meet the real-time and problem parameters.

We are also interested in applications and implementations, that 
demonstrate the systematic way to develop hardware/software objects 
with the emphasis on parametrizability end reconfigurability.

Possible applications of interest include, but are not limited to:

	* signal and image processing
	* multimedia
	* long arithmetic
	* image databases
	* object recognition
	* navigation of robots


Important dates:
----------------
	March 15, 1999:  Draft papers (about 4 pages)
	April 5, 1999:  Notification of acceptance
	May 1, 1999:    Camera-Ready papers
	June 28 - July 1, 1999: Conference and Technical Session

Prospective authors are invited to submit three copies of their draft
paper 
to Toomas P. Plaks by the due date. E-mail submissions in Postscript
format 
viewable and printable with ghostview are also acceptable.


Session Chairs:
---------------

Dr. Toomas P Plaks
Department of Computer Science
The University of Reading
P.O. Box 225
Reading RG6 6AY
Engalnd, UK

email: T.Plaks@reading.ac.uk

Tel.: +44 (0) 118 987 5123 ext 7633
Fax:: +44 (0) 118 975 1994



Prof. Graham. M. Megson
Department of Computer Science
The University of Reading
P.O. Box 225
Reading RG6 6AY
Engalnd, UK

email: G.M.Megson@reading.ac.uk

Tel.: +44 (0) 118 931 8600
Fax:: +44 (0) 118 975 1994
Article: 14990
Subject: Re: PC for CAD
From: walter@chasque.apc.org
Date: Tue, 02 Mar 1999 09:47:02 -0300
Links: << >>  << T >>  << A >>
Steve wrote:
> 
> I trust this isn't too far off topic?
> 
> I am upgrading my PC.
> Which would be best for Xilinx PAR, Active-VHDL sim etc.
> 
> Pentium II Xeon
> Pentium III
> or AMD-K3 (with 256K L2 cache!)
> 
> Thanks
> 
> Steve

I´m using a notebook Thinpad with a Pentium and 80 Mbytes with Fundation
Express 1.5i without problems. IMHO think about how many RAM do you
have  this is the bottle neck.

Walter.
Article: 14991
Subject: Re: LCD driver
From: "Boris Isakhanov" <boris.i@usa.net>
Date: Tue, 2 Mar 1999 14:54:08 +0200
Links: << >>  << T >>  << A >>
Hi, Vitaly
 here is the code you can use

 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lcd is
port(
   le        :in std_logic;
   bl        :in std_logic;
   ph        :in std_logic;
   Data_In      :in std_logic_vector (3 downto 0);
   Data_Out     :out std_logic_vector (6 downto 0)
  );
end lcd;

architecture x of lcd is

signal out_buf     :std_logic_vector(6 downto 0);
signal data_latch    :std_logic_vector(3 downto 0);
begin
 my_latch : process(le)
 begin
  if(le = '1') then
   data_latch <= data_in;
  end if;
 end process;
 --- decoder
 out_buf <= "1111110" when(data_latch = "0000" and bl ='0') else
       "0110000" when(data_latch = "0001" and bl ='0') else
       "1101101" when(data_latch = "0010" and bl ='0') else
       "1111001" when(data_latch = "0011" and bl ='0') else
       "0110011" when(data_latch = "0100" and bl ='0') else
       "1011011" when(data_latch = "0101" and bl ='0') else
       "1011111" when(data_latch = "0110" and bl ='0') else
       "1110000" when(data_latch = "0111" and bl ='0') else
       "1111111" when(data_latch = "1000" and bl ='0') else
       "1111011" when(data_latch = "1001" and bl ='0') else
----- add here more stages if necessary
       "0000000";

 data_out <= out_buf when(ph = '0') else
       not out_buf;
end;

Boris   <boris.i@usa.net>


vitalyh@hotmail.com wrote in message <7bggik$gc3$1@nnrp1.dejanews.com>...
>Hi,
>
>I wrote BCD-to-7Segment driver for LCD, something like 74HC/HCT4543.
>When I synthesize it in Warp, everything is fine. But  Altera Max+II 9.01
>gives it a hard time. There are 590(!) warning messages with Flex rules and
>the device doesn't work at all. How can I change the design to satisfy
>Altera?
>
>------------------------
>---- bcd to lcd --------
>------------------------
>library ieee ;
>use ieee.std_logic_1164.all ;
>entity aldera10 is
>   port ( bcd           : in integer range 0 to 9     ;
>          lt, rbi, pol  : in std_logic                      ;
>          abcdefg       : buffer std_logic_vector (6 downto 0) ;
>          rbo           : buffer std_logic                   ) ;
>end aldera10 ;
>architecture arc_aldera10 of aldera10 is
>begin
>   process(lt,rbi,pol,bcd)
>   begin
>     if (lt='1' and pol='1') then
>        abcdefg <= "1111111" ;
>        rbo <= '0' ;
>     elsif (lt='1' and pol='0') then
>         abcdefg <= "0000000" ;
>         rbo <= '0' ;
>     elsif (rbi='0' and pol='1') or (rbi='1' and bcd/=0 and pol='1') then
>        if bcd = 0 then
>              abcdefg <= "1111110" ;
>        elsif bcd = 1 then
>              abcdefg <= "0110000" ;
>        elsif bcd =  2 then
>              abcdefg <= "1101101" ;
>        elsif bcd = 3 then
>              abcdefg <= "1111001" ;
>        elsif bcd = 4 then
>              abcdefg <= "0110010" ;
>        elsif bcd = 5 then
>              abcdefg <= "1011011" ;
>        elsif bcd = 6 then
>              abcdefg <= "1011111" ;
>        elsif bcd = 7 then
>              abcdefg <= "1110000" ;
>        elsif bcd = 8 then
>              abcdefg <= "1111111" ;
>        elsif bcd = 9 then
>              abcdefg <= "1111011" ;
>        else
>              abcdefg <= "1011011" ;     -- for invalide values
>   end if ;
>   rbo <= '0' ;
>     elsif (rbi='0' and pol='0') or (rbi='1' and bcd/=0 and pol='0') then
>      if bcd = 0 then
>           abcdefg <= "0000001" ;
>     elsif bcd = 1 then
>           abcdefg <= "1001111" ;
>     elsif bcd =  2 then
>           abcdefg <= "0010010" ;
>     elsif bcd = 3 then
>           abcdefg <= "0000110" ;
>     elsif bcd = 4 then
>           abcdefg <= "1001100" ;
>     elsif bcd = 5 then
>           abcdefg <= "0100100" ;
>     elsif bcd = 6 then
>           abcdefg <= "0100000" ;
>     elsif bcd = 7 then
>           abcdefg <= "0001111" ;
>     elsif bcd = 8 then
>           abcdefg <= "0000000" ;
>     elsif bcd = 9 then
>           abcdefg <= "0000100" ;
>     else
>           abcdefg <= "0100100" ;     --for invalide values
>    end if;
>    rbo <='0' ;
>     elsif (rbi='1' and bcd=0 and pol='0') then
>         abcdefg <= "1111111" ;
>       rbo <= '1' ;
>     elsif (rbi='1' and bcd=0 and pol='1') then
>         abcdefg <= "0000000" ;
>       rbo <= '1' ;
>   end if ;
>end process;
>end arc_aldera10;
>
>---------------------------- --- bcd to_lcd ( 3 in 1)----
>---------------------------- library ieee ; use ieee.std_logic_1164.all ;
>entity aldera100 is  port ( bcd1, bcd2, bcd3  : in integer range 0 to 9  ;
>lt, rbi, pol  : in std_logic  ;  abcdefg1, abcdefg2, abcdefg3 : buffer
>std_logic_vector (6 downto 0)); end aldera100 ; architecture arc_aldera100
of
>aldera100 is component aldera10  port ( bcd  : in integer range 0 to 9 ;
>lt, rbi, pol  : in std_logic  ;  abcdefg  : buffer std_logic_vector (6
downto
>0) ;  rbo  : buffer std_logic  ) ; end component ;
>
>  signal  rbi2, rbi3  : std_logic ;
>begin
> lcd1: aldera10 port map(bcd1,lt,rbi ,pol,abcdefg1,rbi2 ) ;
> lcd2: aldera10 port map(bcd2,lt,rbi2,pol,abcdefg2,rbi3 ) ;
> lcd3: aldera10 port map(bcd3,lt,rbi3,pol,abcdefg3,open ) ;
>end arc_aldera100;
>regards,
>Vitaly.
>
>-----------== Posted via Deja News, The Discussion Network ==----------
>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own


Article: 14992
Subject: Re: LCD driver
From: mench@mench.com
Date: 2 Mar 1999 15:02:04 GMT
Links: << >>  << T >>  << A >>
vitalyh@hotmail.com wrote:
> I wrote BCD-to-7Segment driver for LCD, something like 74HC/HCT4543.
> When I synthesize it in Warp, everything is fine. But Altera Max+II
> 9.01 gives it a hard time. There are 590(!) warning messages with
> Flex rules and the device doesn't work at all. How can I change the
> design to satisfy Altera?

It might help if you were to provide a sample of the messages.

Paul

-- 
Paul Menchini          | mench@mench.com | "Non si vive se non il
OrCAD                  | www.orcad.com   |  tempo che si ama."
P.O. Box 71767         | 919-479-1670[v] |  --Claude Adrien Helvetius
Durham, NC  27722-1767 | 919-479-1671[f] |
Article: 14993
Subject: Re: LCD driver
From: Wiggo Olufsen <wiggo.olufsen@online.no>
Date: Tue, 02 Mar 1999 18:12:37 +0100
Links: << >>  << T >>  << A >>
Vitalyh,

As far as I know you don't need the priority implied by using the innermost
if-elsif construction. Try replacing it with a "case" statement, which may reduce
synthesized logic.

Wiggo.

vitalyh@hotmail.com wrote:

> Hi,
>
> I wrote BCD-to-7Segment driver for LCD, something like 74HC/HCT4543.
> When I synthesize it in Warp, everything is fine. But  Altera Max+II 9.01
> gives it a hard time. There are 590(!) warning messages with Flex rules and
> the device doesn't work at all. How can I change the design to satisfy
> Altera?
>
> ------------------------
> ---- bcd to lcd --------
> ------------------------
> library ieee ;
> use ieee.std_logic_1164.all ;
> entity aldera10 is
>    port ( bcd           : in integer range 0 to 9     ;
>           lt, rbi, pol  : in std_logic                      ;
>           abcdefg       : buffer std_logic_vector (6 downto 0) ;
>           rbo           : buffer std_logic                   ) ;
> end aldera10 ;
> architecture arc_aldera10 of aldera10 is
> begin
>    process(lt,rbi,pol,bcd)
>    begin
>      if (lt='1' and pol='1') then
>         abcdefg <= "1111111" ;
>         rbo <= '0' ;
>      elsif (lt='1' and pol='0') then
>          abcdefg <= "0000000" ;
>          rbo <= '0' ;
>      elsif (rbi='0' and pol='1') or (rbi='1' and bcd/=0 and pol='1') then
>         if bcd = 0 then
>               abcdefg <= "1111110" ;
>         elsif bcd = 1 then
>               abcdefg <= "0110000" ;
>         elsif bcd =  2 then
>               abcdefg <= "1101101" ;
>         elsif bcd = 3 then
>               abcdefg <= "1111001" ;
>         elsif bcd = 4 then
>               abcdefg <= "0110010" ;
>         elsif bcd = 5 then
>               abcdefg <= "1011011" ;
>         elsif bcd = 6 then
>               abcdefg <= "1011111" ;
>         elsif bcd = 7 then
>               abcdefg <= "1110000" ;
>         elsif bcd = 8 then
>               abcdefg <= "1111111" ;
>         elsif bcd = 9 then
>               abcdefg <= "1111011" ;
>         else
>               abcdefg <= "1011011" ;     -- for invalide values
>    end if ;
>    rbo <= '0' ;
>      elsif (rbi='0' and pol='0') or (rbi='1' and bcd/=0 and pol='0') then
>       if bcd = 0 then
>            abcdefg <= "0000001" ;
>      elsif bcd = 1 then
>            abcdefg <= "1001111" ;
>      elsif bcd =  2 then
>            abcdefg <= "0010010" ;
>      elsif bcd = 3 then
>            abcdefg <= "0000110" ;
>      elsif bcd = 4 then
>            abcdefg <= "1001100" ;
>      elsif bcd = 5 then
>            abcdefg <= "0100100" ;
>      elsif bcd = 6 then
>            abcdefg <= "0100000" ;
>      elsif bcd = 7 then
>            abcdefg <= "0001111" ;
>      elsif bcd = 8 then
>            abcdefg <= "0000000" ;
>      elsif bcd = 9 then
>            abcdefg <= "0000100" ;
>      else
>            abcdefg <= "0100100" ;     --for invalide values
>     end if;
>     rbo <='0' ;
>      elsif (rbi='1' and bcd=0 and pol='0') then
>          abcdefg <= "1111111" ;
>        rbo <= '1' ;
>      elsif (rbi='1' and bcd=0 and pol='1') then
>          abcdefg <= "0000000" ;
>        rbo <= '1' ;
>    end if ;
> end process;
> end arc_aldera10;
>
> ---------------------------- --- bcd to_lcd ( 3 in 1)----
> ---------------------------- library ieee ; use ieee.std_logic_1164.all ;
> entity aldera100 is  port ( bcd1, bcd2, bcd3  : in integer range 0 to 9  ;
> lt, rbi, pol  : in std_logic  ;  abcdefg1, abcdefg2, abcdefg3 : buffer
> std_logic_vector (6 downto 0)); end aldera100 ; architecture arc_aldera100 of
> aldera100 is component aldera10  port ( bcd  : in integer range 0 to 9  ;
> lt, rbi, pol  : in std_logic  ;  abcdefg  : buffer std_logic_vector (6 downto
> 0) ;  rbo  : buffer std_logic  ) ; end component ;
>
>   signal  rbi2, rbi3  : std_logic ;
> begin
>  lcd1: aldera10 port map(bcd1,lt,rbi ,pol,abcdefg1,rbi2 ) ;
>  lcd2: aldera10 port map(bcd2,lt,rbi2,pol,abcdefg2,rbi3 ) ;
>  lcd3: aldera10 port map(bcd3,lt,rbi3,pol,abcdefg3,open ) ;
> end arc_aldera100;
> regards,
> Vitaly.
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own



--
+---------------------------------------------------------------+
| Wiggo Olufsen                                                 |
| Cypress Software AS           Phone : +47-73-52 46 59         |
| P.O.Box 2668                  Fax   : +47-73-52 46 80         |
| N-7415 TRONDHEIM              E-mail: wiggo.olufsen@online.no |
| NORWAY                                                        |
+---------------------------------------------------------------+


Article: 14994
Subject: Re: Under-clocking SDRAM
From: Tim Hubberstey <marmot@rogers.wave.ca>
Date: Tue, 02 Mar 1999 17:37:52 +0000
Links: << >>  << T >>  << A >>
bmathew@hotmail.com wrote:
> 
> Hi,
> 
> Does anyone know if it is possible to clock SDRAM (any vendor)
> at 1 MHZ or less so as to interface it with an FPGA based
> hardware emulator ?
> 
> Thanks,
> Binu

A quick look at the data sheet for a 64Mb device suggests it should be
possible but the only way to know for sure is to check the data sheet
for the SDRAM you want to use. It will show up as either a maximum clock
high/low time specification or a maximum time spec for some other
parameter such as tRAS. 
-- 
Tim Hubberstey, P.Eng. . . . . . . . . . . . . . .  Marmot Engineering
Vancouver, BC, Canada  . . . . . Hardware/Software Consulting Engineer
Email: marmot@rogers.wave.ca . .  VHDL, ASICs, FPGAs, embedded systems
Phone: (604) 488-1048  . . . . . . . . . . . . . . Fax: (604) 488-1212

Article: 14995
Subject: Problem with Xchecker connection
From: "Laurent HAAS" <lhaas@satie.u-bourgogne.fr>
Date: Tue, 2 Mar 1999 17:38:16 -0000
Links: << >>  << T >>  << A >>
Hello,
Does somebody have ever got a problem whith the connexion of an xchecker
cable on a Xilinx board :
    Sometimes M1 software does'nt see the cable. The disconnection ant then
reconnection of the
Xchecker cable on the Xilinx board solves the problem! Why?
Thanks for an answer.


Article: 14996
Subject: Problems inferring RAM memory
From: Eduardo Augusto Bezerra <E.A.Bezerra@sussex.ac.uk>
Date: Tue, 02 Mar 1999 18:13:37 +0000
Links: << >>  << T >>  << A >>

Hello

I want to use VHDL in order to have a technology independent
implementation, but the problem is that VHDL is not synthesis
tool independent. Is it correct? Is it possible to have only
one VHDL description which can be used for several synthesis
tools to infer memory to different FPGAs?

I'm asking this because some time ago I posted a question
referent to a problem I had when I tried to fit my design in
an XC40150XL FPGA. I've received some suggestions, and from
one of them (Philip Freidin's message below) I could realize
that I had made a big mistake. I had implemented the RAM
memory, in VHDL, using a Synplify template (from Synplify
User Guide Release 5.0) and I synthesized the code using
Foundation Express F1.5i. The problem is that (as expected??)
Foundation couldn't infer memory from Synplify VHDL code
format (file ram256_mem_ea.vhd below).

Following Philip's explanation, the XC4000XL resource usage
for one 256 x 5 FIFO would be 90/100 CLBs:

Philip Freidin wrote:
> 
> (for all calcs below, note that a 4 to 1 mux requires 1 CLB, so a 16 to
> 1 mux requires 4 of these to get from 16 signals down to 4 signals, and 1
> more to get the final output. All calcs are for XC4000/E/EX/XL/XV style
> CLBs, with 2 flip flops, and 2 LUT/FMAP/Functiongenerators each. Since
> Virtex CLBs are basically like two of the XC4000 type CLBs, just halve
> the numbers to get a feel of what it would require in Virtex.)
> 
> First the FIFOs, which are 256 by 5  bits, and there are two of them.
> What is not clear is whether you are reading the FIFOs at the same time
> you are writing them, and if you are doing both, whether the read clock
> and write clock are the same.
> 
> Best case would be only read or write at any time, only 1 clock: 256 by 1
> requires 8 CLBs of single port memory (32 bits per CLB), plus an 8 to 1
> mux on the output that requires 3 CLBs, for a total of 11CLBs. for 5 bits
> wide, this 60 CLBs, times 2 FIFOs, is a total 120 CLBs. There is some
> overhead in address decode and read write logic, which is probably less
> than 50 CLBs.
> 
> So: best case, two FIFOs of 256 x 5  => 170 CLBs
> 


The tables below show the synthesis results for three different RAM
implementations, using Foundation Express F1.5:

Table 1:
--------
- FIFO (control) + RAM (256 x 5)
- RAM memory component (ram_sng.edn) was generated by CoreGen.
- CLB usage is according to the expected

Table 2:
--------
- FIFO (control) + RAM (256 x 5)
- Hand made RAM memory component (ram256_mem_ea.vhd), following
  Synplify template.
- CLB usage is beyond the expected, about 30x

Table 3:
--------
- only RAM (256 x 5)
- RAM memory component (ram_sng.edn) was generated by CoreGen.
- CLB usage is according to the expected

Table 4:
--------
- only RAM (256 x 5)
- Hand made RAM memory component (ram256_mem_ea.vhd), following
  Synplify template.
- CLB usage is beyond the expected

Table 5:
--------
- only RAM (256 x 5)
- Hand made RAM memory component (mem_ea.vhd), following Xilinx
  template.
- CLB usage is beyond the expected


+------------------------------------------------------------+
|Table 1                       |Table 2                      |
|Synthesis results:            |Synthesis results:           |
|Single port memory component  |Single port hand made memory |
|generated by CoreGen          |component                    |
|------------------------------|-----------------------------|
|sval_p.vhd                    |sval_p.vhd                   |
|ram_sng.edn (EDIF)            |ram256_mem_ea.vhd            |
|fifo_hf_ea.vhd                |fifo_hf_ea.vhd               |
|------------------------------|-----------------------------|
|Primitive reference count:    |Primitive reference count:   |
|------------------------------|-----------------------------|
|BUFG          2               |BUFG          3              |
|CY4          20               |CY4          20              |
|CY4_18       10               |CY4_18       10              |
|CY4_20        3               |CY4_20        3              |
|CY4_25        4               |CY4_25        4              |
|CY4_27        1               |CY4_27        1              |
|CY4_42        2               |CY4_42        2              |
|DFF          37               |DFF        1325              |
|FMAP        103               |FMAP       3087              |
|HMAP         15               |HMAP        361              |
|IBUF          6               |IBUF          6              |
|OBUF          8               |OBUF          8              |
+------------------------------------------------------------+


+------------------------------------------------------------+
|Table 3                       |Table 4                      |
|Synthesis results:            |Synthesis results:           |
|Single port memory component  |Single port hand made memory |
|generated by CoreGen          |component (Synplify code)    |
|------------------------------|-----------------------------|
|                              |sval_p.vhd                   |
|ram_sng.edn (EDIF)            |ram256_mem_ea.vhd            |
|------------------------------|-----------------------------|
|Primitive reference count:    |Primitive reference count:   |
|------------------------------|-----------------------------|
|AND2         16               |                             |
|BUFG          1               |BUFG          1              |
|DFF          96               |DFF        1280              |
|FMAP         20               |FMAP       2876              |
|IBUF         15               |HMAP        209              |
|NAND4        16               |                             |
|OBUF          5               |OBUF          5              |
|RAMS         80               |IBUF          6              |
|TBUF         80               |INFF          8              |
+------------------------------------------------------------+


+------------------------------+
|Table 5                       |
|Synthesis results:            |
|Single port hand made memory  |
|component (Xilinx code)       |
|------------------------------|
|mem_ea.vhd                    |
|------------------------------|
|Primitive reference count:    |
|BUFG          2               |
|DFF          40               |
|FMAP         75               |
|HMAP         20               |
|IBUF         10               |
|OUTFFT        5               |
+------------------------------+


Could anybody tell me why Foundation Express can not infer memory from
the ram256_mem_ea.vhd code below?

The VHDL source codes:

*******************************************************************
*******************************************************************
----------
sval_p.vhd
----------
*******************************************************************
*******************************************************************
library IEEE;
   use IEEE.std_logic_1164.all;
package SVAL_PKG is
   --
   -- Definitions for the memory (including FIFOs)
   --
   constant NIBBLE_C  : integer := 4;       -- 4 bits
   constant FIVE_C    : integer := 5;       -- 5 bits
   constant BYTE_C    : integer := 8;       -- 8 bits
   constant WORD_C    : integer := 16;      -- 16 bits
   constant LWORD_C   : integer := 32;      -- 32 bits
   -- Memories
   constant SIZE16_C  : integer := 16;      --  16 addresses
   constant SIZE32_C  : integer := 32;      --  32 addresses
   constant SIZE64_C  : integer := 64;      --  64 addresses
   constant SIZE68_C  : integer := 68;      --  68 addresses
   constant SIZE128_C : integer := 128;     -- 128 addresses
   constant SIZE256_C : integer := 256;     -- 256 addresses
   constant SIZE512_C : integer := 512;     -- 512 addresses
   constant SIZE1K_C  : integer := 1024;    -- 1 K addresses
   -- Memory pointers
   constant PTR16_C  : integer := 4;        --  16 addresses
   constant PTR32_C  : integer := 5;        --  32 addresses
   constant PTR64_C  : integer := 6;        --  64 addresses
   constant PTR68_C  : integer := 7;        --  68 addresses
   constant PTR128_C : integer := 7;        -- 128 addresses
   constant PTR256_C : integer := 8;        -- 256 addresses
   constant PTR512_C : integer := 9;        -- 512 addresses
   constant PTR1K_C  : integer := 10;       -- 1 K addresses

   constant FIFO_HF_SIZE_C        : integer := 255; -- 7;
   constant FIFO_HALF_FULL_HF_C   : integer := 128; -- 4;
end SVAL_PKG;

*******************************************************************
*******************************************************************
------------------------------------
-- ram256_mem_ea.vhd (Synplify model)
------------------------------------
*******************************************************************
*******************************************************************
library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_unsigned.all;
   use work.SVAL_PKG.all;

entity RAM256_MEM is
  port ( CLK_IN       : in  std_logic;
         ADDR_IN      : in  std_logic_vector(PTR256_C - 1 downto 0);
         WR_IN        : in  std_logic;
         DATA_IN      : in  std_logic_vector(FIVE_C - 1 downto 0);
         DATA_OUT     : out std_logic_vector(FIVE_C - 1 downto 0)
        );
end RAM256_MEM;

architecture RAM256_MEM_BEH of RAM256_MEM is
   type RAM_TYP is array(SIZE256_C - 1 downto 0) of
                   std_logic_vector(FIVE_C - 1 downto 0);
   signal MEM         : RAM_TYP;
   signal ADDR_IDX    : std_logic_vector(PTR256_C - 1 downto 0);

begin
   DATA_OUT <= MEM(conv_integer(ADDR_IDX));
   MEMORY_PRO: process (CLK_IN)
   begin
      if CLK_IN'event and CLK_IN = '1' then
         if (WR_IN = '1') then
            MEM(conv_integer(ADDR_IDX)) <= DATA_IN;
         end if;
         ADDR_IDX <= ADDR_IN;
      end if;
   end process MEMORY_PRO;
end RAM256_MEM_BEH;


*******************************************************************
*******************************************************************
------------------------------------
-- mem_ea.vhd (Xilinx model)
------------------------------------
*******************************************************************
*******************************************************************
library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_unsigned.all;

package my_pkg is
   type MEM_WORD is array (255 downto 0) of
                    std_logic_vector (4 downto 0);
end my_pkg;

use work.my_pkg.all;
library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_unsigned.all;

entity mem is
   port (dio           : inout  std_logic_vector (4 downto 0);
         meme, we,
         inclk, outclk : in std_logic;
         addr          : integer range 7 downto 0;
         ro            : out std_logic
        );

end mem;

architecture behav of mem is
   signal mem   : MEM_WORD;
   signal d_int : std_logic_vector (4 downto 0);
begin
   process (inclk)
   begin
      if (inclk'event and inclk = '1') then
         if (meme = '1' and we = '1') then
            mem(addr) <= dio;
         end if;
      end if;
   end process;

   process (outclk)
   begin
      if (outclk'event and outclk = '1') then
         d_int <= mem (addr);
      end if;
   end process;
   dio <= d_int when (meme = '1' and we = '0') else
          "ZZZZZ";
end behav;


*******************************************************************
*******************************************************************
-------------------------------------------------------------------
-- fifo_hf_ea.vhd (with some bugs, but suitable for RAM inferecing)
-------------------------------------------------------------------
*******************************************************************
*******************************************************************
library ieee;
   use ieee.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   use IEEE.std_logic_unsigned.all;
   use work.SVAL_PKG.all;

entity FIFO_HF is

   port ( RESET_NEG_IN   : in  std_logic;      -- '0' -> reset FIFO
          RD_NEG_IN      : in  std_logic;      -- '0' -> read FIFO
          WR_NEG_IN      : in  std_logic;      -- '0' -> write FIFO
          DATA_IN        : in  std_logic_vector(4 downto 0);
          DATA_OUT       : out std_logic_vector(4 downto 0);
          FIFO_HALF_OUT  : out std_logic;      -- '1' when FIFO is >
half full
          FIFO_EMPTY_OUT : out std_logic;      -- '1' when FIFO is empty
          FIFO_FULL_OUT  : out std_logic       -- '1' when FIFO is full
        );

end FIFO_HF;

architecture FIFO_HF_BEH of FIFO_HF is

   component RAM256_MEM is
      port ( CLK_IN       : in  std_logic;
             ADDR_IN      : in  std_logic_vector(PTR256_C - 1 downto 0);
             WR_IN        : in  std_logic;
             DATA_IN      : in  std_logic_vector(FIVE_C - 1 downto 0);
             DATA_OUT     : out std_logic_vector(FIVE_C - 1 downto 0)
            );
   end component;

   -- RAM memory generated by CoreGen
--   component ram_sng port (
--	a: IN std_logic_VECTOR(7 downto 0);    -- ADDR    *
--	d: IN std_logic_VECTOR(4 downto 0);    -- DI      *
--	we: IN std_logic;                      -- WE      *
--	c: IN std_logic;                       -- CLK     *
--	ce: IN std_logic;                      -- RD ??
--	q: OUT std_logic_VECTOR(4 downto 0));  -- DO      *
--   end component;


   -- declarations for RAM_MEM component
   signal DATAIN_MEM,
          DATAOUT_MEM           : std_logic_vector(FIVE_C - 1 downto 0);
   signal ADDR_MEM              : std_logic_vector(PTR256_C - 1 downto
0);
   signal CLK_MEM, WR_MEM       : std_logic;
--   signal RD_MEM                : std_logic;

   -- FIFO pointers
   signal COUNT, COUNT_RD,
          COUNT_WR              : std_logic_vector (8 downto 0);
   signal LAST_IDX, FIRST_IDX   : std_logic_vector (7 downto 0);
   signal FIRST_TIME            : std_logic;
   signal FLAG_FIFO_EMPTY,
          FLAG_FIFO_FULL        : std_logic;
   -- FIFO memory

begin

   RAM256_MEM1: RAM256_MEM
      port map ( CLK_IN   => CLK_MEM,
                 ADDR_IN  => ADDR_MEM,
                 WR_IN    => WR_MEM,
                 DATA_IN  => DATAIN_MEM,
                 DATA_OUT => DATAOUT_MEM
            );

--   RAM256_MEM1 : ram_sng
--      port map (
--	a => ADDR_MEM,
--	d => DATAIN_MEM,
--	we => WR_MEM,
--	c => CLK_MEM,
--	ce => RD_MEM,
--	q => DATAOUT_MEM
--	);

   FIFO_WR_PRO: process(RESET_NEG_IN, WR_NEG_IN, COUNT, LAST_IDX )
   begin
      if RESET_NEG_IN = '0' then
         FLAG_FIFO_FULL    <= '0';
         COUNT_WR          <= (others => '0');
         LAST_IDX          <= (others => '0');
      elsif WR_NEG_IN'event and WR_NEG_IN = '0' then   -- write to FIFO
         if COUNT <= FIFO_HF_SIZE_C then    -- FIFO is not full
            FLAG_FIFO_FULL <= '0';
            COUNT_WR       <= COUNT + 1;
            if LAST_IDX = FIFO_HF_SIZE_C then
               LAST_IDX    <= (others => '0');
            else
               LAST_IDX    <= LAST_IDX + 1;
            end if;
         else
            FLAG_FIFO_FULL <= '1';
            COUNT_WR       <= COUNT;
         end if;
      end if;
   end process FIFO_WR_PRO;

   FIFO_RD_PRO: process(RESET_NEG_IN, RD_NEG_IN, COUNT, FIRST_IDX )
   begin
      if RESET_NEG_IN = '0' then
         FIRST_IDX         <= (others => '0');
         COUNT_RD          <= (others => '0');
         FLAG_FIFO_EMPTY   <= '1';
         FIRST_TIME        <= '1';
      elsif RD_NEG_IN'event and RD_NEG_IN = '0' then
         if COUNT > 0 then  -- FIFO is not empty
            FIRST_TIME      <= '0';
            FLAG_FIFO_EMPTY <= '0';
            COUNT_RD        <= COUNT - 1;
            if FIRST_IDX = FIFO_HF_SIZE_C then
               FIRST_IDX <= (others => '0');
            else
               FIRST_IDX <= FIRST_IDX + 1;
            end if;
         else
            FIRST_TIME      <= '0';
            FLAG_FIFO_EMPTY <= '1';
            COUNT_RD        <= (others => '0');
         end if;
      end if;
   end process FIFO_RD_PRO;

   CLK_MEM         <= '1' when WR_NEG_IN = '0' or RD_NEG_IN = '0' else
                      '0';

   DATAIN_MEM      <= DATA_IN;

   ADDR_MEM        <= LAST_IDX  when WR_NEG_IN = '0' else
                      FIRST_IDX when RD_NEG_IN = '0' else
                      (others => '0');

   WR_MEM          <= '1' when (WR_NEG_IN = '0') and (COUNT <=
FIFO_HF_SIZE_C) else
                      '0' when RD_NEG_IN = '0' else
                      '0';

--   RD_MEM          <= '1' when RD_NEG_IN = '0' else
--                      '0';

   DATA_OUT        <= (others => '0') when RESET_NEG_IN = '0' else
                      DATAOUT_MEM;

   COUNT           <= (others => '0') when RESET_NEG_IN = '0' else
                      COUNT_WR    when ((WR_NEG_IN    = '0') or
(FIRST_TIME = '1')) else
                      COUNT_RD    when RD_NEG_IN    = '0' else
                      (others => '0');

   FIFO_HALF_OUT   <= '0' when RESET_NEG_IN = '0' else
                      '1' when COUNT >= FIFO_HALF_FULL_HF_C else
                      '0';
   FIFO_EMPTY_OUT  <= '1' when RESET_NEG_IN = '0' else
                      '0' when ((COUNT > 0) and (FIRST_TIME = '1')) else
                      FLAG_FIFO_EMPTY;
   FIFO_FULL_OUT   <= '0' when RESET_NEG_IN = '0' else
                      FLAG_FIFO_FULL;
end FIFO_HF_BEH;
Article: 14997
Subject: Re: Problem with xilinx M1
From: "Sergio A. Cuenca Asensi" <sergio@dtic.ua.es>
Date: Tue, 02 Mar 1999 20:09:50 +0100
Links: << >>  << T >>  << A >>

--This happens as a result of a bug in the version of Synopsys' FPGA
--Express that you are using.  Go to http://support.xilinx.com.

--In the text field type:

--fpga express and startup

--Xilinx Answers #3477 and #3566 will help to solve your problem.

--Regards,
--Hobson Frater
--Xilinx Applications

Thank you :)


> ===================================================================
> Sergio A. Cuenca Asensi
> Dept. Tecnologia Informatica y Computacion (TIC)
> Escuela Politecnica Superior, Campus de San Vicente
> Universidad de Alicante
> Ap. Correos 99, E-03080 ALICANTE
> ESPAŅA (SPAIN)
> email   : sergio@dtic.ua.es
> Phone : +34 96 590 39 34
> Fax     : +34 96 590 39 02
> ===================================================================

--
===================================================================
Sergio A. Cuenca Asensi
Dept. Tecnologia Informatica y Computacion (TIC)
Escuela Politecnica Superior, Campus de San Vicente
Universidad de Alicante
Ap. Correos 99, E-03080 ALICANTE
ESPAŅA (SPAIN)
email   : sergio@dtic.ua.es
Phone : +34 96 590 39 34
Fax     : +34 96 590 39 02
===================================================================


Article: 14998
Subject: Student edition!
From: Ilia Oussorov <ilia.oussorov@et.stud.tu-ilmenau.de>
Date: Tue, 02 Mar 1999 20:27:09 +0100
Links: << >>  << T >>  << A >>
Hi all!
I'm student
Where I can get Student Editon of Foundation Ser. Is it free for me?
With best regards.

Ilia Oussorov
TU Ilmenau

Pl. answer on my email!

Article: 14999
Subject: Re: LCD driver
From: Steve@s-deweynospam.demon.co.uk (Steve Dewey)
Date: Tue, 02 Mar 99 20:00:23 GMT
Links: << >>  << T >>  << A >>
In article <7bggik$gc3$1@nnrp1.dejanews.com> vitalyh@hotmail.com  writes:
> Hi,
> 
> I wrote BCD-to-7Segment driver for LCD, something like 74HC/HCT4543.
> When I synthesize it in Warp, everything is fine. But  Altera Max+II 9.01
> gives it a hard time. There are 590(!) warning messages with Flex rules and
> the device doesn't work at all. How can I change the design to satisfy
> Altera?
> 

Sorry if this is a stupid question, but why not instantiate one of the 
7446, 7447, 7448, 7449, 74246, 74247 or 74248 that Altera provide as 
macrofunctions ?

According to their help file you can instantiate them in VHDL.

-- 
Steve Dewey
Steve@s-deweynospam.demon.co.uk
Too boring to have an interesting or witty .sig file.



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