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Messages from 150125

Article: 150125
Subject: Re: ISIM simulation speed
From: Gabor <gabor@alacron.com>
Date: Wed, 15 Dec 2010 08:18:54 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 15, 9:32=A0am, rickman <gnu...@gmail.com> wrote:
> On Dec 15, 4:00=A0am, Petter Gustad <newsmailco...@gustad.com> wrote:
>
> > "HT-Lab" <han...@ht-lab.com> writes:
> > > one limitation. When the user design + testbench exceeds 50,000 lines=
 of HDL
>
> > Then something like this would get around the limitation:
>
> > find vhdl-dir -iname '*.vhd' -print0 | xargs -0 cat | sed 's/\(.*\)--.*=
/\1/' | tr -d "\n\r" > oneliner.vhd
>
> > :-) I always thought the limitation was given as a number of hdl
> > tokens/statements.
>
> It is. =A0They don't count YOUR lines, they parse the code and count
> what THEY consider to be lines.
>
> I am VERY surprised that Xilinx is crippling their own simulator!!!
> Isim is a Xilinx product no? =A0So where is the marketing advantage to
> slowing down your simulations when you are working with larger code
> and most likely larger devices???
>
> Do they really think it is a good idea to give away software that
> discourages the use of their larger part$?
>
> Rick

They must, since the Webpack does not support synthesis for the larger
parts either...

Article: 150126
Subject: Xilinx support makes me want to scream
From: ghelbig <ghelbig@lycos.com>
Date: Wed, 15 Dec 2010 08:59:41 -0800 (PST)
Links: << >>  << T >>  << A >>
Sorry, but I need to vent.

I have a design that works just fine with ISE-11.5, and fails 'PAR'
with ISE-12.3

I opened a web case about my design failing PAR.  The archive of the
project created with ISE was incomplete, so it has taken a while (six
weeks) to get all of the files transferred.

I just got an email from Xilinx Tech Support:  "Your design fails PAR
with ISE-12, can you help ..."

Sigh.  Heavy sigh.

Thanks for listening,
G.

Article: 150127
Subject: Re: spartan 3 xc3s4000 JTAG pins not pulled up
From: Gabor <gabor@alacron.com>
Date: Wed, 15 Dec 2010 10:25:24 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 15, 6:42=A0am, "Fredxx" <fre...@spam.com> wrote:
> "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote in messag=
e
>
> news:o_WdnQVMl9hIDZXQnZ2dnUVZ_uGdnZ2d@giganews.com...
>
>
>
> > hi, i am using spartan 3 xc3s4000 in my design daisy chanied to an EEPR=
OM
> > xcf16p. They are connected in this manner:
>
> > XCF16P -> spartan 3
>
> > It is a custom design and the problem is that my JTAG pins TCK and TDO =
are
> > not getting pulled up to Vccaux, rather they are showing 0 constantly a=
nd
> > TMS is pulled upto 3.3V whereas it should be 2.5v (vccaux). Correct me =
if
> > i
> > am wrong here.
>
> > I have already checked the short circuits on the board and there isn't =
any
> > apparently. My only guess now is the dry soldering of FPGA balls which =
has
> > left the connection open.
>
> > I dont want to take off the FPGA from the board before i am sure of my
> > result so i need ur help in debugging this issue. Kindly give me pointe=
rs,
> > what should i check next before arriving to my conclusion.
>
> > another thing, i took off the EEPROM from board and then checked my JTA=
G
> > pins, none was pulled upto 2.5V. I checked my connections and they were
> > fine, so does this mean my FPGA is not working or what?
>
> The Spartan 3 has internal JTAG pull-up of a modest value. =A0Yes the TMS
> ought to be pulled to 2.5V, but as long as you limit pin current and take
> steps to ensure Vccaux doesn't rise as per XAPP453 you'll be ok.
>
> I would first ensure that 2.5V Vccaux is present.
>
> Check orientation of FPGA, may sound silly but........
>
> I would then use a DVM between 2.5V and JTAG lines to see what current, a=
nd
> equivalent value of pull-down you've got.
>
> Possibly remove the XCF16P if a leaded component to remove any doubt if
> above is showing low impedance.
>
> You should also get access to many of the signals close to the FPGA pads
> through vias on the underside.
>
> How confident are you that the assembler is competent? =A0Generally BGAs =
go
> down well, so I would expect some of the connections to have been made if
> sufficient temperature has been applied. =A0Before removing the FPGA, I w=
ould
> want an inspection, either camera or x-ray. =A0Was the footprint a standa=
rd
> PCB library part.


Another simple check you can do on any signal that goes to an FPGA I/
O.
Use a DVM in the diode-check mode with the hot lead on ground and the
minus lead on the signal.  If your connection is O.K. you should see
the
clamp diode in the IOB, usually around 0.5V.  This works best on a
signal
that doesn't go anywhere else on the board or one that has had it's
other
components removed like your EEPROM.

-- Gabor

Article: 150128
Subject: Re: ISIM simulation speed
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 15 Dec 2010 18:59:00 +0000
Links: << >>  << T >>  << A >>
On Wed, 15 Dec 2010 06:32:41 -0800 (PST), rickman <gnuarm@gmail.com> wrote:

>On Dec 15, 4:00 am, Petter Gustad <newsmailco...@gustad.com> wrote:
>> "HT-Lab" <han...@ht-lab.com> writes:
>> > one limitation. When the user design + testbench exceeds 50,000 lines of HDL
>>
>> Then something like this would get around the limitation:
>>
>> find vhdl-dir -iname '*.vhd' -print0 | xargs -0 cat | sed 's/\(.*\)--.*/\1/' | tr -d "\n\r" > oneliner.vhd
>>
>> :-) I always thought the limitation was given as a number of hdl
>> tokens/statements.
>
>It is.  They don't count YOUR lines, they parse the code and count
>what THEY consider to be lines.
>
>I am VERY surprised that Xilinx is crippling their own simulator!!!
>Isim is a Xilinx product no?  So where is the marketing advantage to
>slowing down your simulations when you are working with larger code
>and most likely larger devices???

The un-crippled version only adds about $1000 to the price of the un-crippled
toolset as a whole ($2400 -> $3400 approx ) and in my opinion it's pretty good
value, as opposed to the price of a retail Modelsim seat. 

It's buggier, but it works cross-language and cross-platform. (and even if you
never touch Verilog, you still need to sim it because vendors don't supply VHDL
models of DDR2 memories...)

What doesn't help is Xilinx's insistence on supplying gate-level sim models for
key components (e.g. PCIe interface - AND its testbench!) - this means the 50k
line limit is crossed before a single line of application is written...

- Brian


Article: 150129
Subject: Re: Xilinx support makes me want to scream
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 15 Dec 2010 19:02:03 +0000
Links: << >>  << T >>  << A >>
On Wed, 15 Dec 2010 08:59:41 -0800 (PST), ghelbig <ghelbig@lycos.com> wrote:

>Sorry, but I need to vent.
>
>I have a design that works just fine with ISE-11.5, and fails 'PAR'
>with ISE-12.3
>
>I opened a web case about my design failing PAR.  The archive of the
>project created with ISE was incomplete, so it has taken a while (six
>weeks) to get all of the files transferred.
>
>I just got an email from Xilinx Tech Support:  "Your design fails PAR
>with ISE-12, can you help ..."
>
>Sigh.  Heavy sigh.

So... congratulate them on reproducing the problem, and ask when they expect to
have a solution!

- Brian

Article: 150130
Subject: Re: Xilinx support makes me want to scream
From: Chris Maryan <kmaryan@gmail.com>
Date: Wed, 15 Dec 2010 12:13:45 -0800 (PST)
Links: << >>  << T >>  << A >>
Perhaps in an effort to solve your problem faster than Xilinx support: how =
is it failing? Is it a timing failure (i.e. a normal PAR failure)?

If so, that's not unusual between tool versions, especially on designs that=
 are near the limits of the FPGA. The algorithms change between versions an=
d something that formerly passed may not pass anymore. Usually the trade-of=
f is that newer versions will be faster, more robust, and generally better =
for 90% of designs. You just happen to be in the other 10% this time.

Tweak your constraints, add area groups where necessary and do whatever you=
 would normally do to get a design to pass PAR.

The fact that you passed PAR before is only valid for a given set of constr=
aints, netlist and tool (ISE 11.5). This also underscores the importance of=
 specifying the toolchain along with any source code control tags if you ne=
ed to have (and everyone should need to have) completely repeatable bit fil=
es.

Chris

Article: 150131
Subject: Re: Xilinx support makes me want to scream
From: ghelbig <ghelbig@lycos.com>
Date: Wed, 15 Dec 2010 13:09:33 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 15, 12:13=A0pm, Chris Maryan <kmar...@gmail.com> wrote:
> Perhaps in an effort to solve your problem faster than Xilinx support: ho=
w is it failing? Is it a timing failure (i.e. a normal PAR failure)?
>
> If so, that's not unusual between tool versions, especially on designs th=
at are near the limits of the FPGA. The algorithms change between versions =
and something that formerly passed may not pass anymore. Usually the trade-=
off is that newer versions will be faster, more robust, and generally bette=
r for 90% of designs. You just happen to be in the other 10% this time.
>
> Tweak your constraints, add area groups where necessary and do whatever y=
ou would normally do to get a design to pass PAR.
>
> The fact that you passed PAR before is only valid for a given set of cons=
traints, netlist and tool (ISE 11.5). This also underscores the importance =
of specifying the toolchain along with any source code control tags if you =
need to have (and everyone should need to have) completely repeatable bit f=
iles.
>
> Chris

It looks like I wasn't communicating properly: their reply made it
seem that they wanted my help getting it to pass PAR.  Or that even
though it worked in 11.5, it was a user design error that caused MAP
to pass an invalid placement to PAR.  (AFAIK, in v12 'place' is done
by MAP, and PAR is just a router.)

It doesn't start as a timing failure.  MAP puts hard macros where they
can't go (too far away from their dedicated I/O pins), and PAR
generates an error instead of moving them.  Version 11 always puts
these blocks in the one and only place that they will fit.

When I constrain them to where they must be (and where v11 puts them
without LOC constraints) is when the timing error surfaces.  Both
versions fail timing when these blocks have LOC constraints.  Version
11 does NOT fail timing when the blocks are placed w/o LOC, even
though (w/ v11) all of these blocks are in exactly the same place with
or without LOC constraints.  Obviously I couldn't try v12 w/o the
LOCs.

G.

Article: 150132
Subject: Re: ISIM simulation speed
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Wed, 15 Dec 2010 19:41:57 -0800 (PST)
Links: << >>  << T >>  << A >>
On 14 Dez., 10:51, Przemys=B3aw Elias <pempus...@gmail.com> wrote:
> Hi,
>
> I've got some logic to simulate in ISIM. The problem is that it's
> quite complex and it takes 9 hours to simulate on my laptop. Is there
> any option that could help me gain a little speed-up?

Use std_ulogic instead of std_logic.

Kolja

Article: 150133
Subject: Re: microblaze spi core problem
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Thu, 16 Dec 2010 10:01:46 +0000
Links: << >>  << T >>  << A >>
Tobias Baumann <ttobsen@hotmail.com> writes:

> Hello
>
> I'm using Xilinx EDK 11.5 with xps_spi core version 2.01b. Core is
> correctly integrated in my SDK, I can see the signals on my
> DSO. Everything seems to be allright. But I've got a little software
> problem.
>
> In SDK I transfer my data with the function "XSpi_Transfer(&mySPI,
> outBuffer, inBuffer, 2)" (see above). It works exactly one time and I
> get XST_SCCUSS back. But if I call XSpi_Transfer again, I get
> XST_DEVICE_BUSY back.
>

Maybe it is actually busy?  There's a FIFO in the SPI controller, so
the XSpi_Transfer call can return before the hardware has finished
sending.  Try checking the status flags before calling XSpi_Transfer
again.

If that's not the case, here's some other thoughts (without looking
deeply into your code, sorry!):

Have you provided your own XAssert handler function to report when
assertions fail - the Xilinx drivers are liberally sprinkled with
them, but the default action is just to hang.  If you look at the call
stack in the debugger, you can see what's going on, but I prefer to
have it pushed out over stdout as well...

I have this in main():
    XAssertSetCallback((XAssertCallback)myassert);

and this function elsewhere.

/* override the Xilinx xassert stub to report errors */
void myassert(char * file, int line)
{
    xil_printf("XASSERT: %s: line %d\r\n", file, line);
}

This may give some clues.

Also:

Have you enabled interrupts?  If so, is the driver expecting
interrupts?  As I recall, the 2.00.a driver didn't work in
non-interrupt mode (it re-enabled the SPI interrupts at the end of a
transmit, irrespective of the interrupt status on entry :) but I think
that was fixed in 2.00.b

Have you provided a StatusHandler function for the spi driver? I seem
to recall doing this helped me debug a similar problem.

On the up side - you at least have all the source to the driver, so
you can single step everything through :)

> void pause(void)
> {
> 	for(int i=0; i<CPU_FREQ; i++);
> }

This is not the world's greatest pause function!  The compiler will
just optimise the loop away (although probably not the function call
itself).

You need a timer in your system that you can watch to see elapsed
time.

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

Article: 150134
Subject: Re: Xilinx support makes me want to scream
From: Marc Jet <jetmarc@hotmail.com>
Date: Thu, 16 Dec 2010 02:36:28 -0800 (PST)
Links: << >>  << T >>  << A >>
Looks like you were testing the limits of v11 already.

I'd try to LOC a different small component (something like a single
FF) prominently where v12 wants to place your hard macro.  That should
force v12 to choose a different placement.  Rinse & repeat until the
macro ends up where it needs to be.

Not a good solution, but maybe enough to make it work until a real fix
is found.  Good luck!

Article: 150135
Subject: Re: Lattice XO2 video
From: Antti <antti.lukats@googlemail.com>
Date: Thu, 16 Dec 2010 02:54:51 -0800 (PST)
Links: << >>  << T >>  << A >>
not sure about being sold in the online store, i think not.
but we got almost firm confirmation of our samples being allocated :)

Antti

Article: 150136
Subject: Re: Question about SOPC and SOF file
From: =?ISO-8859-1?Q?G=F3rski_Adam?= <gorskiamalpa@wpkropkapl>
Date: Thu, 16 Dec 2010 14:50:56 +0100
Links: << >>  << T >>  << A >>
W dniu 12/15/2010 14:57, fasf pisze:
> Hi,
> i'm new on FPGA programming, so i've tried to build my soft core with
> a altera sopc builder. Generate procedure works, so files are
> generated....but: i'm trying to obtain .sof file for devboard: how can
> i do?I should start a new project? Which files i should include?
> thanks

Hi,

So you did first step to use niosii. Great.

Then you have to use for example schematic and put new symbol from 
project library.

Then connect clk,reset, in, out etc.

Build project

Have fun

Adam

Article: 150137
Subject: FPGA modules/cards with peripheral functions
From: Dave <starfire151@cableone.net>
Date: Thu, 16 Dec 2010 10:22:34 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi all -

I'm new to group.  I have a project which uses a Virtex-6 part (the
XC6VLX75T flavor).  The FPGA is a component in a larger circuit which
includes several different interfaces in a standard board format.  The
board format is similar to a VME layout.

I found a company called Pico (www.picocomputing.com/m_series.html)
that makes a module called the M-501.  This module has a Virtex-6,
512MB DDR2 RAM, a JTAG port, and an x8 PCI Express host interface all
on a small board footprint.  The module is designed to be plugged into
a larger carrier card for operation.

Does anyone know of a company making modules similar to this with
generic I/O port pins instead of the PCI Express interface and maybe
some additional peripherals like an SD card, and RS232 or USB port,
etc.?

Thanks.

Article: 150138
Subject: report_timing -from -to
From: "onkars" <onkars@n_o_s_p_a_m.n_o_s_p_a_m.winlab.rutgers.edu>
Date: Thu, 16 Dec 2010 13:16:39 -0600
Links: << >>  << T >>  << A >>

In Synopsys PrimeTime we can do a report_timing -from <A> -to <B>

How can I do the same in Xilinx Timing Analyzer?
Moreover how can I load an interactive session on the Timing analyzer and
do the above?

Thank you.

Onkar	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 150139
Subject: Re: FPGA modules/cards with peripheral functions
From: backhus <goouse99@googlemail.com>
Date: Thu, 16 Dec 2010 22:52:23 -0800 (PST)
Links: << >>  << T >>  << A >>
On 16 Dez., 19:22, Dave <starfire...@cableone.net> wrote:
> Hi all -
>
> I'm new to group. =A0I have a project which uses a Virtex-6 part (the
> XC6VLX75T flavor). =A0The FPGA is a component in a larger circuit which
> includes several different interfaces in a standard board format. =A0The
> board format is similar to a VME layout.
>
> I found a company called Pico (www.picocomputing.com/m_series.html)
> that makes a module called the M-501. =A0This module has a Virtex-6,
> 512MB DDR2 RAM, a JTAG port, and an x8 PCI Express host interface all
> on a small board footprint. =A0The module is designed to be plugged into
> a larger carrier card for operation.
>
> Does anyone know of a company making modules similar to this with
> generic I/O port pins instead of the PCI Express interface and maybe
> some additional peripherals like an SD card, and RS232 or USB port,
> etc.?
>
> Thanks.

Hi,
you may take a look here:
http://enterpoint.co.uk/products/spartan-6-development-boards/

Have a nice synthesis
  Eilert

Article: 150140
Subject: Re: ISIM simulation speed
From: Andy Peters <google@latke.net>
Date: Fri, 17 Dec 2010 07:48:04 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 15, 7:32=A0am, rickman <gnu...@gmail.com> wrote:
>
> I am VERY surprised that Xilinx is crippling their own simulator!!!
> Isim is a Xilinx product no? =A0So where is the marketing advantage to
> slowing down your simulations when you are working with larger code
> and most likely larger devices???

Short (and fully correct answer): They want you to buy the full-up
software.

Their assumption has always been that if you can afford to use the
largest devices in a design, then you can afford the full-up tools
required to design them in, on the theory that these larger designs
will require more support, which is paid for by buying the full-up
software.

Of course that's absurd. What Xilinx should really do is what Apple
does for support. The tools are free. But if you want support, you
choose either the free mailing lists, or you can pay for different
levels/amounts of support. So you can pay, in advance, for three or
four support 'incidents,' and the advantage here is that you get in
touch with someone on the first level that can actually help you, as
opposed to having to deal with the first-line drones, which wastes
days until you can convince them to escalate the problem (you
generally need to get your FAE involved).

Anyways, ISIM is cheaper than Active-HDL and ModelSim, but that makes
sense, because it's not ready for prime time yet.

-a

Article: 150141
Subject: Re: spacewire project on opencores.org
From: Sebastien Bourdeauducq <sebastien.bourdeauducq@gmail.com>
Date: Fri, 17 Dec 2010 16:35:41 -0800 (PST)
Links: << >>  << T >>  << A >>
On Friday, December 10, 2010 3:57:43 PM UTC+1, Thomas Stanka wrote:
> Open cores tend to have a lack in documentation and verification,

I'd even say a lack in everything. Very often, architecture and implementation choices aren't brilliant either. GRLIB is well above most of what you can find at opencores.org, and AMBA is a lesser evil.

I would also take what it said in the Opencores.org newsletter with a grain of salt. Those people have lots of delusions.

> which is a no-go for developing space electronics.

Any serious electronics at all.
S.

Article: 150142
Subject: Re: FPGA modules/cards with peripheral functions
From: Bryan <bryan.fletcher@avnet.com>
Date: Sat, 18 Dec 2010 08:08:33 -0800 (PST)
Links: << >>  << T >>  << A >>
www.em.avnet.com/virtex6lx130t-evl
www.xilinx.com/ml605

Bryan


On Dec 16, 1:22=A0pm, Dave <starfire...@cableone.net> wrote:
> Hi all -
>
> I'm new to group. =A0I have a project which uses a Virtex-6 part (the
> XC6VLX75T flavor). =A0The FPGA is a component in a larger circuit which
> includes several different interfaces in a standard board format. =A0The
> board format is similar to a VME layout.
>
> I found a company called Pico (www.picocomputing.com/m_series.html)
> that makes a module called the M-501. =A0This module has a Virtex-6,
> 512MB DDR2 RAM, a JTAG port, and an x8 PCI Express host interface all
> on a small board footprint. =A0The module is designed to be plugged into
> a larger carrier card for operation.
>
> Does anyone know of a company making modules similar to this with
> generic I/O port pins instead of the PCI Express interface and maybe
> some additional peripherals like an SD card, and RS232 or USB port,
> etc.?
>
> Thanks.


Article: 150143
Subject: Re: FPGA modules/cards with peripheral functions
From: Dave <starfire151@cableone.net>
Date: Sat, 18 Dec 2010 12:21:48 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 18, 9:08=A0am, Bryan <bryan.fletc...@avnet.com> wrote:
> www.em.avnet.com/virtex6lx130t-evlwww.xilinx.com/ml605
>
> Bryan
>

While these are similar to what I'm talking about, I need something in
a modular format with only the FPGA, memory, storage Flash, some
optional interfaces (serial, USB, Ethernet), and a bunch of unused
FPGA I/O pins that could connect with my application.

I was looking for something similar to the boards in the link pointed
to by Eilert (thanks, by the way, for posting that) in that they are a
module to be plugged in to a carrier card of some sort.

The idea is to concentrate all the high-density, multilayer board to
only the section needed by the FPGA and memory interfaces.  This would
be in a smaller footprint.  This overall module could be plugged into
a carrier card of some format (VME, PC, CAMAC, etc.).  The carrier
card would not necessarily need to have as many layers as the module
and the design would be simpler and less expensive.

It seems most of the existing modules out there are designed for a PCI
Express interface and, so, have many pins dedicated to that interface.

If anyone else knows about such a FPGA module, I would really
appreciate hearing about it.

Thanks.

Article: 150144
Subject: Re: FPGA modules/cards with peripheral functions
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Sun, 19 Dec 2010 06:44:16 -0600
Links: << >>  << T >>  << A >>
Here are a few companies that may have what you are looking for :-

Nallatech
Alpha Data
Hunt Engineering

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 150145
Subject: Re: FPGA modules/cards with peripheral functions
From: John Adair <g1@enterpoint.co.uk>
Date: Sun, 19 Dec 2010 05:25:19 -0800 (PST)
Links: << >>  << T >>  << A >>
Dave

If you see anything from our range that catches your eye it is always
worth asking us for the price of semi custom variant of that product.
Unlike many of our compeditors we do offer semi and full custom boards
and it usually works well typically for customer volumes 10 boards+.

If it is a one off project can also off modules for adaption and tha
typically is a lower cost. Just depends what is needed.

I will also mention that our popular Drigmorn4 design
http://www.enterpoint.co.uk/drigmorn/drigmorn4.html is getting an
upgrade of features the main one being 38 extra pairs of I/O on 2 new
connectors on the rear of the board. These can be used as LVDS or
single ended 3.3V I/O. The full compliment of this new I/O will be
available on LX150 versions but less on other variants of the board.
We will be bringing a wide range of support modules for this new
header including touchscreen, battery packs, wide range input power,
FMC interface and relay modules to name a few. It will also suit a lot
of customers like you that need I/O in a compact form. The size of the
original board is unchanged with this upgrade and it remains
compatible with Drigmorn3 and Drigmorn2 mountings.

John Adair
Enterpoint Ltd.

On Dec 18, 8:21=A0pm, Dave <starfire...@cableone.net> wrote:
> On Dec 18, 9:08=A0am, Bryan <bryan.fletc...@avnet.com> wrote:
>
> >www.em.avnet.com/virtex6lx130t-evlwww.xilinx.com/ml605
>
> > Bryan
>
> While these are similar to what I'm talking about, I need something in
> a modular format with only the FPGA, memory, storage Flash, some
> optional interfaces (serial, USB, Ethernet), and a bunch of unused
> FPGA I/O pins that could connect with my application.
>
> I was looking for something similar to the boards in the link pointed
> to by Eilert (thanks, by the way, for posting that) in that they are a
> module to be plugged in to a carrier card of some sort.
>
> The idea is to concentrate all the high-density, multilayer board to
> only the section needed by the FPGA and memory interfaces. =A0This would
> be in a smaller footprint. =A0This overall module could be plugged into
> a carrier card of some format (VME, PC, CAMAC, etc.). =A0The carrier
> card would not necessarily need to have as many layers as the module
> and the design would be simpler and less expensive.
>
> It seems most of the existing modules out there are designed for a PCI
> Express interface and, so, have many pins dedicated to that interface.
>
> If anyone else knows about such a FPGA module, I would really
> appreciate hearing about it.
>
> Thanks.


Article: 150146
Subject: Re: FPGA modules/cards with peripheral functions
From: Socrates <mailsoc@gmail.com>
Date: Sun, 19 Dec 2010 17:07:33 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 19, 3:25=A0pm, John Adair <g...@enterpoint.co.uk> wrote:
> Dave
>
> If you see anything from our range that catches your eye it is always
> worth asking us for the price of semi custom variant of that product.
> Unlike many of our compeditors we do offer semi and full custom boards
> and it usually works well typically for customer volumes 10 boards+.
>
> If it is a one off project can also off modules for adaption and tha
> typically is a lower cost. Just depends what is needed.
>
> I will also mention that our popular Drigmorn4 designhttp://www.enterpoin=
t.co.uk/drigmorn/drigmorn4.htmlis getting an
> upgrade of features the main one being 38 extra pairs of I/O on 2 new
> connectors on the rear of the board. These can be used as LVDS or
> single ended 3.3V I/O. The full compliment of this new I/O will be
> available on LX150 versions but less on other variants of the board.
> We will be bringing a wide range of support modules for this new
> header including touchscreen, battery packs, wide range input power,
> FMC interface and relay modules to name a few. It will also suit a lot
> of customers like you that need I/O in a compact form. The size of the
> original board is unchanged with this upgrade and it remains
> compatible with Drigmorn3 and Drigmorn2 mountings.
>
> John Adair
> Enterpoint Ltd.

Are You planning any boards with Altera devices? A board with Cyclone
IV GX would definitely have its market, I suppose. There is a nice kit
@ Altera with that device, however it lacks free I/O pins for custom
solutions.

Article: 150147
Subject: Re: spacewire project on opencores.org
From: Alessandro Basili <alessandro.basili@cern.ch>
Date: Mon, 20 Dec 2010 17:28:12 +0100
Links: << >>  << T >>  << A >>
On 12/18/2010 1:35 AM, Sebastien Bourdeauducq wrote:
> On Friday, December 10, 2010 3:57:43 PM UTC+1, Thomas Stanka wrote:
>> Open cores tend to have a lack in documentation and verification,
>
> I'd even say a lack in everything. Very often, architecture and
> implementation choices aren't brilliant either. GRLIB is well above
> most of what you can find at opencores.org, and AMBA is a lesser
> evil.

Appreciate your feedback, even though I believe that a review to 
opencores is a bit OT. I may agree with you that it can be chosen a 
different location for the project (can you propose any valid 
alternative to opencores?), but the main idea was to sample an overall 
feeling about the project itself.

Thanks anyway!

Al

Article: 150148
Subject: Re: FPGA modules/cards with peripheral functions
From: John Adair <g1@enterpoint.co.uk>
Date: Mon, 20 Dec 2010 10:00:55 -0800 (PST)
Links: << >>  << T >>  << A >>
We have Raggedstone3 ready to launch. It is Cyclone IV GX based. It
will be launched formally in January and that point I will talk about
it a bit more.

John Adair
Enterpoint Ltd.

On Dec 20, 1:07=A0am, Socrates <mail...@gmail.com> wrote:
> On Dec 19, 3:25=A0pm, John Adair <g...@enterpoint.co.uk> wrote:
>
>
>
> > Dave
>
> > If you see anything from our range that catches your eye it is always
> > worth asking us for the price of semi custom variant of that product.
> > Unlike many of our compeditors we do offer semi and full custom boards
> > and it usually works well typically for customer volumes 10 boards+.
>
> > If it is a one off project can also off modules for adaption and tha
> > typically is a lower cost. Just depends what is needed.
>
> > I will also mention that our popular Drigmorn4 designhttp://www.enterpo=
int.co.uk/drigmorn/drigmorn4.htmlisgetting an
> > upgrade of features the main one being 38 extra pairs of I/O on 2 new
> > connectors on the rear of the board. These can be used as LVDS or
> > single ended 3.3V I/O. The full compliment of this new I/O will be
> > available on LX150 versions but less on other variants of the board.
> > We will be bringing a wide range of support modules for this new
> > header including touchscreen, battery packs, wide range input power,
> > FMC interface and relay modules to name a few. It will also suit a lot
> > of customers like you that need I/O in a compact form. The size of the
> > original board is unchanged with this upgrade and it remains
> > compatible with Drigmorn3 and Drigmorn2 mountings.
>
> > John Adair
> > Enterpoint Ltd.
>
> Are You planning any boards with Altera devices? A board with Cyclone
> IV GX would definitely have its market, I suppose. There is a nice kit
> @ Altera with that device, however it lacks free I/O pins for custom
> solutions.


Article: 150149
Subject: Help! Question about Debug!
From: "zhanglixing7890" <magicxdms@n_o_s_p_a_m.gmail.com>
Date: Mon, 20 Dec 2010 14:16:28 -0600
Links: << >>  << T >>  << A >>
After I clicked the debug button, several minutes later, an error is
displaying in the console window, which said view console [nios2-gdb-server
out put],and "target is not responding(time out)" writen bellow that
sentence. I can not debug, but I can run it. Why? How to solve this
problem.

	   
					
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