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On Mar 14, 1:03=A0pm, NeedCleverHandle <d_s_kl...@yahoo.com> wrote: > On Mar 14, 7:52=A0am, "Nial Stewart" > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > > If you think that you will get farther in your goal by using FPGAs > > > from Altera, Lattice, Microsemi (aka Actel), or QuickLogic then you > > > should absolutely switch over. > > > Ed, I read this as "Please use someone else's devices so I can stop > > answering these ****ing stupid questions". > > > :-) > > > Nial. > > My experience with the brand-X sales force leads me to believe that > they have significant training in politeness and political > correctness. =A0Many times I have watched in amazement as impossible > demands were deflected without insult. > > I ain't made of that stuff. If that is your impression of the X-team then you haven't been posting here but for a short time. There used to be some very interesting "conversations" here which were not very "polite" or PC. But someone at X high up the food chain put an end to that by decree. RickArticle: 151226
On Mar 15, 6:27=A0am, Thomas Womack <twom...@chiark.greenend.org.uk> wrote: > In article <ilnebt$tm...@news.eternal-september.org>, > glen herrmannsfeldt =A0<g...@ugcs.caltech.edu> wrote: > > > > >whygee <y...@yg.yg> wrote: > > >(after I wrote) > >>> Not so long ago, I was considering a project for genomics that > >>> needs about 1e18 six bit add/subtract operations per day. =A0 > >>> I figured out that it could be done with about 2000 S3E devices, > >>> though so far no interest in building one. > > >> at this level, maybe a finely tuned and optimised MMX/SSE/SSE2/whateve= r > >> code would do the trick, using 8-bit chunks in 64, 128 or 256-bits > >> wide words... and it would be future-proof, as the x86 (or whatever > >> arch of the day is) could be upgraded to faster/lower power/more core > >> hardware. > > >At (about) 1e5 seconds/day, I need 1e13/second. =A0At 1GHz, > >that is 1e4 per clock cycle. =A0No, there are no 80000 bit > >registers in MMX or SSE. > > No, but getting hold of a hundred PCs (which will do four SSE > operations per clock cycle, so about sixty six-bit add/subtracts, and > run at 2.5GHz with four cores) is not a difficult task. =A0If you can > partition the job over 2000 FPGAs, you can probably partition it over > 100 PCs. > > Tom I don't follow. Why would it take 2000 FPGAs to do what you can do with 100 PCs? I would think the ratio would be far in the other direction. The PC may have a 10x performance advantage in terms of clock speed (or less), but the FPGA has the advantage of 100x to 1000x hardware resources! We are only talking about 6 bit adders, right? No mention of memory or other resources required. But the add/sub units are trivial. RickArticle: 151227
Ed McGettigan <ed.mcgettigan@xilinx.com> writes: > On Mar 15, 10:26 am, "sebas" > <tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: >> Hi, >> >> A newbie's question, in the following code: <snip> >> why is the writing done sequentially and the reading purely combinational? >> That is writing inside an always activated on the front edge of clk and >> reading in a continuous assignment. >> >> Thanks >> > > Because the designer wanted the read to be asynchronous? > ...so that the synthesizer would infer CLB RAM? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 151228
In article <0a389d39-3e86-46a1-8f20-b291384bac49@34g2000pru.googlegroups.com>, rickman <gnuarm@gmail.com> wrote: >On Mar 15, 6:27=A0am, Thomas Womack <twom...@chiark.greenend.org.uk> >wrote: >> In article <ilnebt$tm...@news.eternal-september.org>, >> glen herrmannsfeldt =A0<g...@ugcs.caltech.edu> wrote: >> >> >> >> >whygee <y...@yg.yg> wrote: >> >> >(after I wrote) >> >>> Not so long ago, I was considering a project for genomics that >> >>> needs about 1e18 six bit add/subtract operations per day. =A0 >> >>> I figured out that it could be done with about 2000 S3E devices, >> >>> though so far no interest in building one. >> >> >> at this level, maybe a finely tuned and optimised MMX/SSE/SSE2/whateve= >r >> >> code would do the trick, using 8-bit chunks in 64, 128 or 256-bits >> >> wide words... and it would be future-proof, as the x86 (or whatever >> >> arch of the day is) could be upgraded to faster/lower power/more core >> >> hardware. >> >> >At (about) 1e5 seconds/day, I need 1e13/second. =A0At 1GHz, >> >that is 1e4 per clock cycle. =A0No, there are no 80000 bit >> >registers in MMX or SSE. >> >> No, but getting hold of a hundred PCs (which will do four SSE >> operations per clock cycle, so about sixty six-bit add/subtracts, and >> run at 2.5GHz with four cores) is not a difficult task. =A0If you can >> partition the job over 2000 FPGAs, you can probably partition it over >> 100 PCs. >> >> Tom > >I don't follow. Why would it take 2000 FPGAs to do what you can do >with 100 PCs? 10^18 per day = 10^13 per second = 10^9.7 per FPGA-second, according to the figures he's using. Which might be a 100MHz FPGA clock and 80 units on the FPGA, or 25MHz and 300 units. The PCs are 2.5GHz quad-cores, so there's the factor 100; SSE gets you sixteen units rather than eighty, but the much faster clocks make up for it. (this is the problem I run into whenever considering how to do number-theory really fast on FPGAs: a Spartan 3 has a hundred 17x17 multipliers running at 200MHz, a cheap AMD CPU has four 64x64 multipliers running at 2500MHz and an expensive one has twelve) TomArticle: 151229
On Mar 16, 8:49=A0am, rickman <gnu...@gmail.com> wrote: > On Mar 14, 1:03=A0pm, NeedCleverHandle <d_s_kl...@yahoo.com> wrote: > > > > > On Mar 14, 7:52=A0am, "Nial Stewart" > > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > > > If you think that you will get farther in your goal by using FPGAs > > > > from Altera, Lattice, Microsemi (aka Actel), or QuickLogic then you > > > > should absolutely switch over. > > > > Ed, I read this as "Please use someone else's devices so I can stop > > > answering these ****ing stupid questions". > > > > :-) > > > > Nial. > > > My experience with the brand-X sales force leads me to believe that > > they have significant training in politeness and political > > correctness. =A0Many times I have watched in amazement as impossible > > demands were deflected without insult. > > > I ain't made of that stuff. > > If that is your impression of the X-team then you haven't been posting > here but for a short time. =A0There used to be some very interesting > "conversations" here which were not very "polite" or PC. =A0But someone > at X high up the food chain put an end to that by decree. > > Rick I was posting when it was called usenix. The experiences I was talking about were in the Real World, not The Internet. Cheers, RKArticle: 151230
On Mar 16, 8:49=A0am, rickman <gnu...@gmail.com> wrote: > On Mar 14, 1:03=A0pm, NeedCleverHandle <d_s_kl...@yahoo.com> wrote: > > > > > > > On Mar 14, 7:52=A0am, "Nial Stewart" > > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > > > If you think that you will get farther in your goal by using FPGAs > > > > from Altera, Lattice, Microsemi (aka Actel), or QuickLogic then you > > > > should absolutely switch over. > > > > Ed, I read this as "Please use someone else's devices so I can stop > > > answering these ****ing stupid questions". > > > > :-) > > > > Nial. > > > My experience with the brand-X sales force leads me to believe that > > they have significant training in politeness and political > > correctness. =A0Many times I have watched in amazement as impossible > > demands were deflected without insult. > > > I ain't made of that stuff. > > If that is your impression of the X-team then you haven't been posting > here but for a short time. =A0There used to be some very interesting > "conversations" here which were not very "polite" or PC. =A0But someone > at X high up the food chain put an end to that by decree. > > Rick- Hide quoted text - > > - Show quoted text - Rick, I'm not sure where you got that idea. There have been a number of influences that have affected the Xilinx participation here, but there has never been a decree. Over the last 15 or so years there's only been a handful of Xilinx people posting to comp.arch.fpga that would include myself, Peter Alfke and Austin Lesea as the most proliferate posters. There were a number of others that posted occasionally, but when AT&T dropped all USENET groups a few years ago the internal comp.arch.fpga newsgroup feed was no longer available and the casual Xilinx poster became a rarity. The recent rise in SPAM postings that are not filter out from Google Groups almost made me retreat completely to the Xilinx Forums, but I'm still here for now. Ed McGettigan -- Xilinx Inc.Article: 151231
rickman <gnuarm@gmail.com> wrote: (snip) > I was going to use this once, a long time ago, with the Spartan > family. But I don't think this ever materialized for the Spartans. > But you can do this with the Virtex parts. The partial bitstreams are > stored in a file or ROM and a controlling CPU sends them to the FPGA. > I think you can even build the CPU into the static part of the FPGA > design and it can reload the partial bitstreams itself! Yes. I heard a talk some years ago from someone who had Linux running on the PPC in the FPGA, then using that to control the reconfiguration. -- glenArticle: 151232
rickman <gnuarm@gmail.com> wrote: (snip) > I don't follow. Why would it take 2000 FPGAs to do what you can do > with 100 PCs? I would think the ratio would be far in the other > direction. The PC may have a 10x performance advantage in terms of > clock speed (or less), but the FPGA has the advantage of 100x to 1000x > hardware resources! > We are only talking about 6 bit adders, right? No mention of memory > or other resources required. But the add/sub units are trivial. The memory requirements are very small. Maybe 300 16x2 ROMs (or, as previously suggested, SRL16s). Maybe also some buffering of results on the way out, probably using the BRAMs. So, for 1e18 add/sub per day, 86400 seconds per day, say 3GHz and, with SSEn, 32 add/sub per cycle. (There is probably some overhead in there.) Then 120 would do it. I am pretty sure it doesn't work such that every cycle uses the appropriate SSEn registers, so it is likely somewhat worse. Even so, the choice is between a box full of FPGAs connected to one computer (which might fit in a small room), and, say 300 PCs, appropriate power and network wiring. I suppose they could net boot such that you didn't need to install OS, but write custom software for them. They take up a lot of space, use a lot of power, and otherwise aren't that much more useful. Data is coming in at the appropriate rate to keep the system busy for years. -- glenArticle: 151233
Thomas Womack <twomack@chiark.greenend.org.uk> wrote: (snip, someone wrote) >>I don't follow. Why would it take 2000 FPGAs to do what you can do >>with 100 PCs? > 10^18 per day = 10^13 per second = 10^9.7 per FPGA-second, according > to the figures he's using. Which might be a 100MHz FPGA clock and 80 > units on the FPGA, or 25MHz and 300 units. > The PCs are 2.5GHz quad-cores, so there's the factor 100; SSE gets you > sixteen units rather than eighty, but the much faster clocks make up > for it. It has been done on SSE, Google for 699 Rognes Seeberg and it comes up at the top of the list. > (this is the problem I run into whenever considering how to do > number-theory really fast on FPGAs: a Spartan 3 has a hundred 17x17 > multipliers running at 200MHz, a cheap AMD CPU has four 64x64 > multipliers running at 2500MHz and an expensive one has twelve) Conveniently my problem has no multiplies in it. -- glenArticle: 151234
On Tuesday, March 15, 2011 7:03:37 PM UTC-4, Ed McGettigan wrote: > On Mar 15, 3:05=A0pm, "andreiseb" > <andrei...@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > > >On Mar 15, 10:26=3DA0am, "sebas" > > ><tanarne...@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: > > >> Hi, > > > > >> A newbie's question, in the following code: > > > > >> module reg_file > > >> ( > > >> input wire clk, > > >> input wire wr_en, > > >> input wire [1:0] w_addr, r_addr, > > >> input wire [7:O] w_data, > > >> output wire [7:Ol r_data > > >> ) > > > > >> reg [7:Ol array_reg [2**1:0] ; > > >> always @(posedge clk) > > >> =3DA0 =3DA0 =3DA0 =3DA0 if (wr_en) > > >> =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 array_reg [w_addrl <= =3D3D w_data; > > >> assign r_data =3D3D array_reg [r_addr]; > > > > >> why is the writing done sequentially and the reading purely > > combinational=3D > > >? > > >> That is writing inside an always activated on the front edge of clk = and > > >> reading in a continuous assignment. > > > > >> Thanks =3DA0 =3DA0 > > > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > > >> Posted throughhttp://www.FPGARelated.com > > > > >Because the designer wanted the read to be asynchronous? > > > > >Ed McGettigan > > >-- > > >Xilinx Inc. > > > > Lol, good answer. Let me rephrase that, then: is this a usual practice:= the > > writing to be synchronous and the reading to be asynchronous? Can they = both > > be =A0asynchronous? =A0 =A0 =A0 =A0 =A0 > > > > --------------------------------------- =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com- Hide quoted text - > > > > - Show quoted text - >=20 > A register file is basically an array of registers (aka flip/flops) > with a defined width and depth. As an example you could take 128 > registers and define them as 8 bits wide and 16 deep. This can define > in Verilog like this: >=20 > reg [7:0] my_reg_file [3:0] >=20 I think you meant to write: reg [7:0] my_reg_file [0:15]; if you really wanted 16 8-bit registers=20 rather than 4 8-bit registers. > The write to the register file must be synchronous, after all they are > registers and they have to save state. In theory it would be possible > to create an asynchronous write, but this is comp.arch.fpga and any > attempt to do so in an FPGA would be a big mistake. >=20 > The "read' isn't really a read, but a multiplexer selection of a > single register within the array. In the case of the above example > this would be a eight 16-to-1 mux with 4 select lines. The address to > data would be combinatorial (aka asynchronous), but it would also > include a synchronous path for the clock-to-out from the registers in > the array. >=20 > Complicating the asynchronous vs synchronous description of the access > is that the read address would have been generated by something > synchronous and the data out will likely be stored in something > synchronous. So the label is really in the eye of the beholder. >=20 > Ed McGettigan > -- > Xilinx Inc.Article: 151235
On Mar 16, 2:35=A0pm, Gabor <ga...@alacron.com> wrote: > On Tuesday, March 15, 2011 7:03:37 PM UTC-4, Ed McGettigan wrote: > > On Mar 15, 3:05=A0pm, "andreiseb" > > <andrei...@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > > > >On Mar 15, 10:26=3DA0am, "sebas" > > > ><tanarne...@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: > > > >> Hi, > > > > >> A newbie's question, in the following code: > > > > >> module reg_file > > > >> ( > > > >> input wire clk, > > > >> input wire wr_en, > > > >> input wire [1:0] w_addr, r_addr, > > > >> input wire [7:O] w_data, > > > >> output wire [7:Ol r_data > > > >> ) > > > > >> reg [7:Ol array_reg [2**1:0] ; > > > >> always @(posedge clk) > > > >> =3DA0 =3DA0 =3DA0 =3DA0 if (wr_en) > > > >> =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 array_reg [w_addrl= <=3D3D w_data; > > > >> assign r_data =3D3D array_reg [r_addr]; > > > > >> why is the writing done sequentially and the reading purely > > > combinational=3D > > > >? > > > >> That is writing inside an always activated on the front edge of cl= k and > > > >> reading in a continuous assignment. > > > > >> Thanks =3DA0 =3DA0 > > > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > > > >> Posted throughhttp://www.FPGARelated.com > > > > >Because the designer wanted the read to be asynchronous? > > > > >Ed McGettigan > > > >-- > > > >Xilinx Inc. > > > > Lol, good answer. Let me rephrase that, then: is this a usual practic= e: the > > > writing to be synchronous and the reading to be asynchronous? Can the= y both > > > be =A0asynchronous? =A0 =A0 =A0 =A0 =A0 > > > > --------------------------------------- =A0 =A0 =A0 =A0 > > > Posted throughhttp://www.FPGARelated.com-Hide quoted text - > > > > - Show quoted text - > > > A register file is basically an array of registers (aka flip/flops) > > with a defined width and depth. =A0As an example you could take 128 > > registers and define them as 8 bits wide and 16 deep. =A0This can defin= e > > in Verilog like this: > > > reg [7:0] my_reg_file [3:0] > > I think you meant to write: > > reg [7:0] my_reg_file [0:15]; > > if you really wanted 16 8-bit registers > rather than 4 8-bit registers. > > > > > The write to the register file must be synchronous, after all they are > > registers and they have to save state. =A0In theory it would be possibl= e > > to create an asynchronous write, but this is comp.arch.fpga and any > > attempt to do so in an FPGA would be a big mistake. > > > The "read' isn't really a read, but a multiplexer selection of a > > single register within the array. =A0In the case of the above example > > this would be a eight 16-to-1 mux with 4 select lines. =A0The address t= o > > data would be combinatorial (aka asynchronous), but it would also > > include a synchronous path for the clock-to-out from the registers in > > the array. > > > Complicating the asynchronous vs synchronous description of the access > > is that the read address would have been generated by something > > synchronous and the data out will likely be stored in something > > synchronous. =A0So the label is really in the eye of the beholder. > > > Ed McGettigan > > -- > > Xilinx Inc.- Hide quoted text - > > - Show quoted text -- Hide quoted text - > > - Show quoted text - A quick google search for Verliog example code shows that Gabor is 100% correct. I've probably only used arrays a handful of times and didn't realize that right hand vector was an integer range (which I find a bit odd, but there must be some underlying elegance to be described this way). Ed McGettigan -- Xilinx Inc.Article: 151236
On Tue, 15 Mar 2011 08:17:21 -0500 "sdaau" <sd@n_o_s_p_a_m.n_o_s_p_a_m.imi.aau.dk> wrote: > By the way, I experimented a bit with querying process IDs in Linux, > and could capture most of the command lines issued by ISE when running > particular commands. So, given that the reference point is after > "Cleanup Project Files": If you want something more reliable, try "strace -e trace=process -o somefile -ff mycommand", it will run "mycommand" and dump into "somefile.<pid>" all the forks, execs, and exits done by the command and all its children (there will be a separate file for the syscalls done by each process). You now guarantee to capture every command line. ChrisArticle: 151237
> The recent rise in SPAM postings that are not filter out from Google > Groups almost made me retreat completely to the Xilinx Forums, but I'm > still here for now. Ed, Please stick about. I'm predominently an Altera user but your input here is important for the 'community' such as it is. And I know you'll be here for project or two I do with Xilinx devices :-) Do you have to use Google groups? I pay for news.individual.net access (10 Euros/year) which has really good spam filters but I think there are a few free usenet servers with good filtering. Please keep it up. Nial.Article: 151238
"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> writes: > I pay for news.individual.net access (10 Euros/year) which has really good > spam filters but I think there are a few free usenet servers with good > filtering. I'm using news.eternal-september.org, which is free, but you have to register. I almost never see any spam. See http://eternal-september.org/ //Petter -- .sig removed by request.Article: 151239
hi all rick : > > i wanted to use chunks of bit-stream assembled in my model conformance > > to process in place of the cpu > > Uhhh... you can do that. =A0It's called partial reconfiguration. =A0 i knew partial reconfiguration it's ok for some "work" ;) some elses need a complete one so it's not the full joy > > I was going to use this once, a long time ago, with the Spartan > family. =A0But I don't think this ever materialized for the Spartans. > But you can do this with the Virtex parts. The partial bitstreams are > stored in a file or ROM and a controlling CPU sends them to the FPGA. > I think you can even build the CPU into the static part of the FPGA > design and it can reload the partial bitstreams itself! i saw some boards sellers stating there spartan 3E boards do it so i bought spartan 3E ;) thanks Rick & allArticle: 151240
Hi !
geobsd wrote:
> hi all
> rick :
>>> i wanted to use chunks of bit-stream assembled in my model conformance
>>> to process in place of the cpu
>> Uhhh... you can do that. It's called partial reconfiguration.
> i knew partial reconfiguration
> it's ok for some "work" ;)
please take the following aspects into account :
- what rick described is a system where the configuration chunks
are precomputed. your own system is meant to recompute configurations on the fly,
which is another, different story : rick meant "static" reconfiguration
(the circuit has predefined functions, they are just swapped during use),
you want to have "dynamic" reconfiguration where you don't know
in advance what the circuits will do.
- there is a difference between "i've seen it done once" and "i do it usually",
between "it's possible" and "it's common practice". Xilinx does allow partial
reconfiguration on the more expensive parts because the cheap parts go to
standard applications where reconfiguration is not considered, practical,
too much of a problem for little gain, etc.
- so in practice, it seems to me that dynamic partial reconfiguration is a
nice, but unused and marginally useful feature, and only one of the many
benefits of FPGA. I can do without, and many others do. Sure, we are engineers
and solve real-life, industrial problems, we are not AI researchers :-)
OTOH several FPGA families have "full" dynamic reconfiguration,
I seem to remember that S3 can select one out of several bitstreams
from its local Flash storage, depending on some external pin configurations.
it's less sexy than partial reconfiguration but useful in more places :-)
hope this helps,
yg
--
http://ygdes.com / http://yasep.org
Article: 151241On Wednesday, March 16, 2011 8:33:45 PM UTC-4, Ed McGettigan wrote: > On Mar 16, 2:35=A0pm, Gabor <ga...@alacron.com> wrote: [snip] > > > A register file is basically an array of registers (aka flip/flops) > > > with a defined width and depth. =A0As an example you could take 128 > > > registers and define them as 8 bits wide and 16 deep. =A0This can def= ine > > > in Verilog like this: > > > > > reg [7:0] my_reg_file [3:0] > > > > I think you meant to write: > > > > reg [7:0] my_reg_file [0:15]; > > > > if you really wanted 16 8-bit registers > > rather than 4 8-bit registers. [snip] >=20 > A quick google search for Verliog example code shows that Gabor is > 100% correct. I've probably only used arrays a handful of times and > didn't realize that right hand vector was an integer range (which I > find a bit odd, but there must be some underlying elegance to be > described this way). >=20 > Ed McGettigan > -- > Xilinx Inc. I'm not sure why you find it odd. The range of a bit vector is an "integer range". If you want 16 bits you write reg [15:0] foo; So if you want 16 registers why would you think you would write something other than reg [15:0] foo [0:15]; or (less common) reg [15:0] foo [15:0]; I'm not sure why the range is usually ascending on the right side. Since you can't access a sub-range of vectors, it really doesn't affect the resulting hardware regardless of its direction. However the fact that the range defines 16 items rather than the range of the required address (Log2(16)) seems normal to me. -- GaborArticle: 151242
On 16 Mrz., 16:34, rickman <gnu...@gmail.com> wrote: > On Mar 14, 8:46=A0pm, Kolja Sulimma <ksuli...@googlemail.com> wrote: > > > On 13 Mrz., 01:46, rickman <gnu...@gmail.com> wrote: > > > > since a bad bitstream has potential of frying an FPGA. > > > This argument is invalid. > > > You can fry an FPGA with VDHL and vendor synthesis software. > > This has been demonstrated at the FPL conference a decade ago. > > =A0It doesn't matter if there are other ways > to fry a part. =A0The point is that the vendors exert control over the > design software so that they have control over this sort of problem. > It doesn't matter if they prevent you 100% from doing damage to the > chips. =A0They take responsibility if you are using their tools. But how would documenting the bitstream format make this issue worse? I could still expect the vendor tools to be correct, don't I? KoljaArticle: 151243
On Mar 17, 6:21=A0am, Gabor <ga...@alacron.com> wrote: > On Wednesday, March 16, 2011 8:33:45 PM UTC-4, Ed McGettigan wrote: > > On Mar 16, 2:35=A0pm, Gabor <ga...@alacron.com> wrote: > [snip] > > > > A register file is basically an array of registers (aka flip/flops) > > > > with a defined width and depth. =A0As an example you could take 128 > > > > registers and define them as 8 bits wide and 16 deep. =A0This can d= efine > > > > in Verilog like this: > > > > > reg [7:0] my_reg_file [3:0] > > > > I think you meant to write: > > > > reg [7:0] my_reg_file [0:15]; > > > > if you really wanted 16 8-bit registers > > > rather than 4 8-bit registers. > [snip] > > > A quick google search for Verliog example code shows that Gabor is > > 100% correct. =A0I've probably only used arrays a handful of times and > > didn't realize that right hand vector was an integer range (which I > > find a bit odd, but there must be some underlying elegance to be > > described this way). > > > Ed McGettigan > > -- > > Xilinx Inc. > > I'm not sure why you find it odd. =A0The range of > a bit vector is an "integer range". =A0If you > want 16 bits you write > > =A0reg [15:0] foo; > > So if you want 16 registers why would you > think you would write something other than > > =A0reg [15:0] foo [0:15]; > or (less common) > =A0reg [15:0] foo [15:0]; > > I'm not sure why the range is usually ascending > on the right side. =A0Since you can't access > a sub-range of vectors, it really doesn't affect > the resulting hardware regardless of its direction. > However the fact that the range defines 16 items > rather than the range of the required address > (Log2(16)) seems normal to me. > > -- Gabor- Hide quoted text - > > - Show quoted text - The reason why I found it odd that the same text seemed to create two different ranges depending on the usage. [15:0] =3D 16 bits =3D Range of 65535 to 0 (if on the left) [15:0] =3D 16 elements =3D Range of 15 to 0 (if on the right) As I typed the above I saw why it is the way that it is, but my mind keeps trying to go back to the binary to (unsigned) integer conversion for the range.... Ed McGettigan -- Xilinx Inc.Article: 151244
We have some plans in this area but I can't give a timeline at the moment. John Adair Enterpoint Ltd. On Mar 13, 6:32=A0pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote: > I'm looking for cards for a couple of different applications, dual 10G > Ehternet (requires dual SFP+) connectors and QDR InfiniBand (dual QSFP+). > Both applications require 10G SerDes which means either a Stratix4GT or a > Virtex6HXT, either is acceptable. > > Hitechglobal has some interesting cards that meet these requirements, wha= t > other vendors should I explore?Article: 151245
don't take the fly whygee > > please take the following aspects into account : > > =A0 - what rick described is a system where the configuration chunks > =A0 =A0 are precomputed. your own system is meant to recompute configurat= ions on the fly, > =A0 =A0 which is another, different story : rick meant "static" reconfigu= ration > =A0 =A0 (the circuit has predefined functions, they are just swapped duri= ng use), > =A0 =A0 you want to have "dynamic" reconfiguration where you don't know > =A0 =A0 in advance what the circuits will do. i know what is called partial reconfiguration it is documented no complain about it from me > > =A0 - there is a difference between "i've seen it done once" and "i do it= usually", > =A0 =A0 between "it's possible" and "it's common practice". google give many peoples telling it don't work properly > =A0 - so in practice, it seems to me that dynamic partial reconfiguration= is a > =A0 =A0 nice, but unused and marginally useful feature, and only one of t= he many > =A0 =A0 benefits of FPGA. I can do without, and many others do. Sure, we = are engineers > =A0 =A0 and solve real-life, industrial problems, we are not AI researche= rs :-) ok, you are driving the fly, i wrote to you that i also wanted study a new kind of AI (for free) the most need for real dynamic bit-stream is for this it's not cause i'm not a "pro" electronician nor searcher that you can decide fpgas are not for me > > OTOH several FPGA families have "full" dynamic reconfiguration, > I seem to remember that S3 can select one out of several bitstreams > from its local Flash storage, depending on some external pin configuratio= ns. > it's less sexy than partial reconfiguration but useful in more places :-) i know about it too more places for your job > > hope this helps, i hope flys will not eat youArticle: 151246
On Mar 17, 2:30=A0pm, Kolja Sulimma <ksuli...@googlemail.com> wrote: > But how would documenting the bitstream format make this issue worse? > I could still expect the vendor tools to be correct, don't I? Kolja it seem honesty is the problem, not only from buyers but also from makers that can sell non-conform products without the fear of an external certification tool !Article: 151247
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: (snip on register file in verilog) > The reason why I found it odd that the same text seemed to create two > different ranges depending on the usage. > [15:0] = 16 bits = Range of 65535 to 0 (if on the left) > [15:0] = 16 elements = Range of 15 to 0 (if on the right) > As I typed the above I saw why it is the way that it is, but my mind > keeps trying to go back to the binary to (unsigned) integer conversion > for the range.... I wonder if you are a Pascal programmer. Pascal has a subrange type where you specify the range of values that you would like it to have. PL/I allows one to specify the number of bits (for BINARY types), or decimal digits (for DECIMAL types). (and note that the underlying representation doesn't have to agree.) Fortran has SELECTED_INT_KIND() and SELECTED_REAL_KIND that allow one to specify in decimal digits (even though it is usually implemented in binary) the range one needs. But if you think of them as bit patterns, instead of numerical values, then it is more obvious to count bits. -- glenArticle: 151248
Hello, I am having a problem using DMA. When I run my code in Altera DE2
Board, the program stucks at "while (!txrx_done)". It seems like it has
infinite loop. I dont know what happen. Please assist. Thank you in
advance!
my code:
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
#include <string.h>
#include <system.h>
#include <io.h>
#include <alt_types.h>
#include "sys/alt_dma.h"
#include "sys/alt_cache.h"
#include "sys/alt_alarm.h"
#include "alt_types.h"
static volatile int txrx_done = 0;
//callback function when DMA transfer done
static void txrxDone(void * handle, void * data)
{
txrx_done = 1;
}
void initMEM(int base_addr,int len)
{
for (int i=0;i<len;i++)
{
IOWR_8DIRECT(base_addr,i,i);
}
}
int main()
{
printf("testing ssram & sdram : dma operation\n");
alt_16 buffer[10];
//memset((void *)SSRAM_0_BASE,0x7a,0x10);//this write base on byte
initMEM(SDRAM_1_BASE,0x10);
memset((void *)(SDRAM_1_BASE+0x10),0x33,0x10);
printf("content of sdram_1:before DMA operation\n");
for (int i=0;i<0x10;i++)
{
printf("%d: %x\n",i,IORD_8DIRECT(SDRAM_1_BASE,i));
}
printf("content of sdram_1(offset 0x10):before DMA operation\n");
for (int i=0;i<0x10;i++)
{
printf("%d: %x\n",i,IORD_8DIRECT(SDRAM_1_BASE+0x10,i));
}
int rc; //request
alt_dma_txchan txchan;
alt_dma_rxchan rxchan;
void* tx_data = (void*)SDRAM_1_BASE; /* pointer to data to send */
void* rx_buffer = (void*)(SDRAM_1_BASE+0x10); /* pointer to rx buffer */
/* Create the transmit channel */
if ((txchan = alt_dma_txchan_open("/dev/dma_0")) == NULL)
{
printf ("Failed to open transmit channel\n");
exit (1);
}
/* Create the receive channel */
if ((rxchan = alt_dma_rxchan_open("/dev/dma_0")) == NULL)
{
printf ("Failed to open receive channel\n");
exit (1);
}
/* Post the transmit request */
if ((rc = alt_dma_txchan_send (txchan,
tx_data,
0x10,
NULL,
NULL)) < 0)
{
printf ("Failed to post transmit request, reason = %i\n", rc);
//exit (1);
}
/* Post the receive request */
if ((rc = alt_dma_rxchan_prepare (rxchan,
rx_buffer,
0x10,
txrxDone,
NULL)) < 0)
{
printf ("Failed to post read request, reason = %i\n", rc);
//exit (1);
}
/* wait for transfer to complete */
while (!txrx_done);
printf ("Transfer successful!\n");
printf("content of sdram_1:after DMA operation\n");
for (int i=0;i<0x10;i++)
{
printf("%d: %x\n",i,IORD_8DIRECT(SDRAM_1_BASE,i));
}
printf("content of sdram_1(offset 0x10):after DMA operation\n");
for (int i=0;i<0x10;i++)
{
printf("%d: %x\n",i,IORD_8DIRECT(SDRAM_1_BASE+0x10,i));
}
return 0;
}
---------------------------------------
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Article: 151249Hi all, I am working on a Spartan-6 FPGA. I am using a DCM (DCM_CLKGEN Primitive) to generate some clock rates that I want to. Here is how I declare the DCM DCM_CLKGEN g723clk_dcm ( .CLKIN ( fpgaclk ), .RST ( dcm_rst_g723 ), .LOCKED (lock_val_g723), .CLKFX ( codec_286m_dcm ), .CLKFX180 ( codec_286m_180p) ); defparam g723clk_dcm.CLKIN_PERIOD = 50; defparam g723clk_dcm.CLKFX_MULTIPLY = 143; defparam g723clk_dcm.CLKFX_DIVIDE = 10; // synthesis attribute CLKIN_PERIOD of g723clk_dcm is 50; // synthesis attribute CLKFX_MULTIPLY of g723clk_dcm is 143; // synthesis attribute CLKFX_DIVIDE of g723clk_dcm is 10; I am getting a warning like this "The DCM, g723clk_dcm, has the attribute DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK. No phase relationship exists between the input clock and CLKFX or CLKFX180 outputs of this DCM. Data paths between these clock domains must be constrained using FROM/TO constraints." Can somebody let me know what could be the reason for this warning? Am I doing any wrong in declaring the DCM? Thanks, Regards, Aditi.
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