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Thanks for the explanation Jonathan. The one thing I still don't understand is what you would do if you want to change the bit width of the vectors. In my Verilog mux I can just instantiate it and override the parameters to create a different mux. If I want 5 mux in my design, all with different sizes then thats not a problem. I dont quite see how you would do that in VHDL using the constant in the package. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152426
On Sun, 21 Aug 2011 13:09:15 -0500, "maxascent" wrote:
>Thanks for the explanation Jonathan. The one thing I still don't understand
>is what you would do if you want to change the bit width of the vectors. In
>my Verilog mux I can just instantiate it and override the parameters to
>create a different mux. If I want 5 mux in my design, all with different
>sizes then thats not a problem. I dont quite see how you would do that in
>VHDL using the constant in the package.
Well, you're right that this is a slightly awkward feature of
design parameterization in VHDL. You can deal with it in various
ways. VHDL-2008 package generics (not very widely supported yet)
handle it nicely. The more portable, but slightly more wordy way
is to use true 2-dimensional arrays; these let you do the
parameterization with complete generality, but force you into
writing conversion functions or blocks to shuttle between "array of
std_logic_vector" and "2-d array of std_logic". It's not really
difficult, and it doesn't cost you any extra logic, but it looks
a bit convoluted. The type declaration would be
type multi_SLV is array(
natural range <>, -- choose a word
natural range <>) -- choose a bit in a word
of std_logic;
and you can put one of those on an unconstrained port, or use
generics to constrain its dimensions. But you can't directly
slice it to give you a std_logic_vector. Instead you need a
selector function, which of course you squirrel away in the same
package that defines the array:
-- Get one SLV slice out of the 2-d array
function get_vector(the_array: in multi_SLV; slice: in natural)
return std_logic_vector is
-- Make a variable that matches one row of the array
variable v: std_logic_vector(the_array'range(2));
begin
for bit_num in v'range loop
v(bit_num) := the_array(slice, bit_num);
end loop;
return v;
end;
And probably an updater function too:
-- Update one SLV slice in a 2-D array, returning the
-- updated array as a whole
function set_vector(the_array: in multi_SLV; slice: in natural;
new_slice_contents: in std_logic_vector)
return multi_SLV is
variable a: multi_SLV(the_array'range(1), the_array'range(2));
variable v: std_logic_vector(the_array'range(2);
begin
v := new_slice_contents; -- normalizes the vector range
a := the_array;
for bit_num in v'range loop
a(slice, bit_num) := v(bit_num);
end loop;
return a;
end;
Looks clunky, but once you've written the package it's all
quite neat and tidy - and it's only bit-twiddling so there's
no additional logic overhead.
--
Jonathan Bromley
Article: 152427On Aug 19, 11:25=A0pm, Steve <theec...@gmail.com> wrote: > >> The 4K7 pullups for PROGRAM_B and INIT_B plus the 330 ohm pullup on Do= ne > > > Is it okay to use the internal pullups for those (by typing HSWAPEN to > > GND)? > > I strongly advise against it. =A0Resistors cost about one tenth of a cent= , > I can't think of a reason to leave them out. Well, board space is a reason -- I'm awful at soldering SMT components, and a through-hole resistor is a big chunk of real estate. But it isn't a good reason. I'll put in the discrete pull-ups. > http://www.xilinx.com/support/answers/35002.htm Wow, thanks for that link, that explains a lot. They ought to mention the internal-resistor-is-only-for-slow-CCLKs rationale in the configuration guide.Article: 152428
> This is known as a fractional divider, and there are many ways of
> designing these.
>
> For simulation purposes I use a module that takes a real parameter to
> specify the desired frequency in Hz. It works for frequencies up to half
> of the reciprocal of the timing resolution of the simulator.
>
> Regards,
> Allan
Allan, many thanks for your answer. I still used the ps resolution and
came up with a:
//Clock generation
always
begin
#41666 fx2_clk = !fx2_clk;
#41667 fx2_clk = !fx2_clk;
#41667 fx2_clk = !fx2_clk;
end
That would lower the jitter even more.
It works perfectly and now I have very good and round timings in my
simulator.
Could you tell me more about the module you mentioned?
Thanks in advance.
Giuseppe Marullo
Article: 152429On 17 ao=FBt, 21:18, "Phil Emmup" <ph...@hotnots.rot> wrote: > "Nicolas Matringe" <nicolas.matri...@fre.fre> wrote in message > > news:4e4c1188$0$7330$426a74cc@news.free.fr... > > > Hi > > I have found old parts lying around in the lab and I could put them to > > good use. Alas, they are not supported by Quartus any more. Do you know > > which version of the tool I should get (and where I could get it, if > > Altera doesn't provide it) ? > > > Thanks > > Nicolas > > Quartus V9.1 sp2 =A0(the last sensible version before the excellent inter= nal > simulator was dropped) supports Flex10k. > > Should still be available on Altera website. Hi It was actually V9.0, as stated in this 9.1 note http://www.altera.com/literature/rn/rn_qts_91sp2_dev_support.pdf NicolasArticle: 152430
On 18 ao=FBt, 16:14, radarman <jsham...@gmail.com> wrote: > On Aug 17, 2:27=A0pm, Nicolas Matringe <nicolas.matri...@fre.fre> wrote: [...] > Note, Altera often supports parts long after they stop showing up in > the device selection panel. I have a board with somewhat rare > Flex10K100 on it (specifically, a 10K100GC503-3), that quit showing up > in the drop downs a very long time ago. The original design was done > in MaxPlusII! > I have to manually edit the QSF with the specific part number to get > it to work. However, if you get the part number exactly right, Quartus > will set everything else up for you. Even the pin mapper works > correctly. The thing is that since I'll be working on a new design (and I haven't used these parts for years, and I changed company since) I don't have any QSF example. I'll work with Quartus v9.0 at first and see if I can migrate the design to a more recent version. > It's as if Altera doesn't want to advertise support for these older > parts, but keeps it anyway. This may not apply to the Flex10K for > current versions, but as a general rule, Altera (and Xilinx) often > support obsolete parts this way. Maybe they don't want too much advertising to avoid getting requests for the parts they don't supply anymore. Thanks for the tip NicolasArticle: 152431
On Mon, 22 Aug 2011 00:58:17 +0200, Giuseppe Marullo wrote:
>> This is known as a fractional divider, and there are many ways of
>> designing these.
>>
>> For simulation purposes I use a module that takes a real parameter to
>> specify the desired frequency in Hz. It works for frequencies up to
>> half of the reciprocal of the timing resolution of the simulator.
>>
>> Regards,
>> Allan
>
> Allan, many thanks for your answer. I still used the ps resolution and
> came up with a:
>
> //Clock generation
> always
> begin
> #41666 fx2_clk = !fx2_clk;
> #41667 fx2_clk = !fx2_clk;
> #41667 fx2_clk = !fx2_clk;
> end
>
> That would lower the jitter even more.
>
> It works perfectly and now I have very good and round timings in my
> simulator.
It seems like you have the hang of things.
> Could you tell me more about the module you mentioned?
I have both Verilog and VHDL "precision_clock_generator" modules that
I've been using for about a decade now.
I also have a "precision_vcxo" (VHDL only, 'cause Verilog is too stupid
to allow ports of type real for the control voltage) that's handy for
simulating certain types of PLLs.
I may eventually get around to cleaning them up for publication, probably
on opencores.
The interface looks roughly like this:
module precision_clock_generator
#(
parameter FREQUENCY // frequency in Hz, (real)
)
(
input enable, // runs when this input is high or open
output clk_p, // main clock output
output clk_n, // inverse of clk_p
);
Basically it just models one of those 4 or 6 pin crystal oscillators and
uses various techniques to ensure that it produces the exact frequency
requested, with the minimum possible amount of jitter.
For most testbenches, the simple and obvious way of generating clocks in
either HDL works fine, but there are times when you really need the right
frequency and these modules help with that.
Regards,
Allan
Article: 152432I have a 200 MHz clock gated by a BUFGMUX. I added some unrelated logic and the routing of the gate control signal got longer and broke the FPGA. The routing delay in earlier versions was ~ 1.8ns compared to ~ 2.5ns in the broken version. So I added a MAXDELAY = 1.2ns constraint. The constraint was not met; PAR only managed 1.748ns; but the FPGA worked. So I changed the constraint to 1.8ns and re-ran PAR. It failed to meet the constraint, this time reporting an actual net delay of 2.4ns and the FPGA did not work. So I know the tools can manage 1.8ns; but I don't know how to make them! Any suggestions? TIAArticle: 152433
Andrew Holme <ah@nospam.com> wrote: > I have a 200 MHz clock gated by a BUFGMUX. I added some unrelated logic and > the routing of the gate control signal got longer and broke the FPGA. The > routing delay in earlier versions was ~ 1.8ns compared to ~ 2.5ns in the > broken version. So I added a MAXDELAY = 1.2ns constraint. The constraint > was not met; PAR only managed 1.748ns; but the FPGA worked. So I changed > the constraint to 1.8ns and re-ran PAR. It failed to meet the constraint, > this time reporting an actual net delay of 2.4ns and the FPGA did not work. > So I know the tools can manage 1.8ns; but I don't know how to make them! Well, it seems that if you ask for 1.2ns it works. The tools have to balance the constraints on all nets, including ones that you specify indirectly. Reducing that one presumably makes something else slower, but it seems not something that you care (or know) about. We like all or nothing (less than, or not less than, 1.9ns), but minimization algorithms don't work that way. Can you reduce the constraints on other nets? -- glenArticle: 152434
On 08/23/2011 06:26 AM, Andrew Holme wrote: > I have a 200 MHz clock gated by a BUFGMUX. I added some unrelated logic and > the routing of the gate control signal got longer and broke the FPGA. The > routing delay in earlier versions was ~ 1.8ns compared to ~ 2.5ns in the > broken version. So I added a MAXDELAY = 1.2ns constraint. The constraint > was not met; PAR only managed 1.748ns; but the FPGA worked. So I changed > the constraint to 1.8ns and re-ran PAR. It failed to meet the constraint, > this time reporting an actual net delay of 2.4ns and the FPGA did not work. > So I know the tools can manage 1.8ns; but I don't know how to make them! > > Any suggestions? > > TIA With ISE you're working with a chaotic system. Small changes in the input can lead to widely varying outputs. If asking for 1.2ns yielded 1.748ns and asking for 1.8ns yielded 2.4ns, then try a binary search between 1.2ns and 1.8ns on your constraint. Hopefully something in that range will work! Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.auArticle: 152435
In article <j2umiv$eff$1@speranza.aioe.org>, Steve <theecobs@gmail.com> wrote: >On 08/23/2011 06:26 AM, Andrew Holme wrote: >> I have a 200 MHz clock gated by a BUFGMUX. I added some unrelated logic and >> the routing of the gate control signal got longer and broke the FPGA. The >> routing delay in earlier versions was ~ 1.8ns compared to ~ 2.5ns in the >> broken version. So I added a MAXDELAY = 1.2ns constraint. The constraint >> was not met; PAR only managed 1.748ns; but the FPGA worked. So I changed >> the constraint to 1.8ns and re-ran PAR. It failed to meet the constraint, >> this time reporting an actual net delay of 2.4ns and the FPGA did not work. >> So I know the tools can manage 1.8ns; but I don't know how to make them! >> >> Any suggestions? >> >> TIA > >With ISE you're working with a chaotic system. Small changes in the >input can lead to widely varying outputs. > >If asking for 1.2ns yielded 1.748ns and asking for 1.8ns yielded 2.4ns, >then try a binary search between 1.2ns and 1.8ns on your constraint. >Hopefully something in that range will work! Another option that we use - take that 1.748ns result, and grab the placements from that PAR of the relevant logic (i.e. the BUFGMUX, perhaps the fanin logic of the gate control). LOC down just those blocks in your UCF, and still use the "realistic" 1.8ns constraint. This has worked for us in the past. YMMV... --MarkArticle: 152436
Hi, I don't have good experience with MAXDELAY constraint in my Virtex-5 and Virtex-6 designs and ISE 12.x and 13.x tools. Using LOC and AREA_GROUP constraints produces much better results (timing closure and build consistency). Thanks, Evgeni http://outputlogic.comArticle: 152437
On 08/16/2011 09:20 AM, majsta wrote: > Yes in my first design i used quickswich devices but then i decide to go to > the newer devices like txs0108e. This is octal bi-directional bus with > voltage level translation. And now i dont know is this design ok becuse > like you write in previus post best metod is to use quickswich. What do you > think about txs0108e in this design. Also i would not use cyclone just for > memory, i want to use mc68000 core with sdram controler to replace mc68000 > on the board. Make sure when you use a converter like that that Vih on the 5V side is low enough for TTL. From the looks of it, that is *not* true for TXS0108E when Vccb = 5V. The reason quickswitches work for 5 V TTL <-> 3.3 V CMOS is because 3.3 V leverages the assymetry in 5 V TTL voltages; active buffers are usually better for CMOS-to-CMOS conversion... -hpaArticle: 152438
I would suggest putting the critical elements of this part of design into a seperate level of hierarchy either as instantiated elements or HDL coding. If you turn hierarchy preservation on in synthesis this will then make floorplanning, and LOCing, of the critical elements much easier. It will also tend to give less variation in the synthesis results as well. You can also do this as a back end edit using FPGA Editor to achieve extreme end results but this really should be a last resort as it is very time consuming and has to done every time you rebuild unless you can create a macro to automate it. John Adair Enterpoint Ltd. - Home of Raggedstone2. The Spartan-6 PCIe Development Board. On Aug 22, 9:26=A0pm, "Andrew Holme" <a...@nospam.com> wrote: > I have a 200 MHz clock gated by a BUFGMUX. =A0I added some unrelated logi= c and > the routing of the gate control signal got longer and broke the FPGA. =A0= The > routing delay in earlier versions was ~ 1.8ns compared to ~ 2.5ns in the > broken version. =A0So I added a MAXDELAY =3D 1.2ns constraint. =A0The con= straint > was not met; PAR only managed 1.748ns; but the FPGA worked. =A0So I chang= ed > the constraint to 1.8ns and re-ran PAR. =A0It failed to meet the constrai= nt, > this time reporting an actual net delay of 2.4ns and the FPGA did not wor= k. > So I know the tools can manage 1.8ns; but I don't know how to make them! > > Any suggestions? > > TIAArticle: 152439
Hi , I am currently designing a FPGA Actel Proasci3 and I would like to know the ressource usage (ram/flipflop...) for each of module of the project , in Altera and Xilinx they report this information easily but I don't find it in Actel Designer (we also use synplify for synthesis so it shall be fine to use synplify reporting too) Thank you for your tips! AlexisArticle: 152440
On Aug 23, 12:12=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > I would suggest putting the critical elements of this part of design > into a seperate level of hierarchy either as instantiated elements or > HDL coding. If you turn hierarchy preservation on in synthesis this > will then make floorplanning, and LOCing, of the critical elements > much easier. It will also tend to give less variation in the synthesis > results as well. > > You can also do this as a back end edit using FPGA Editor to achieve > extreme end results but this really should be a last resort as it is > very time consuming and has to done every time you rebuild unless you > can create a macro to automate it. > > John Adair > Enterpoint Ltd. - Home of Raggedstone2. The Spartan-6 PCIe Development > Board. > > On Aug 22, 9:26=A0pm, "Andrew Holme" <a...@nospam.com> wrote: > > > > > > > > > I have a 200 MHz clock gated by a BUFGMUX. =A0I added some unrelated lo= gic and > > the routing of the gate control signal got longer and broke the FPGA. = =A0The > > routing delay in earlier versions was ~ 1.8ns compared to ~ 2.5ns in th= e > > broken version. =A0So I added a MAXDELAY =3D 1.2ns constraint. =A0The c= onstraint > > was not met; PAR only managed 1.748ns; but the FPGA worked. =A0So I cha= nged > > the constraint to 1.8ns and re-ran PAR. =A0It failed to meet the constr= aint, > > this time reporting an actual net delay of 2.4ns and the FPGA did not w= ork. > > So I know the tools can manage 1.8ns; but I don't know how to make them= ! > > > Any suggestions? > > > TIA Additonally I think you can form an edif netlist of some route the design meet the timing on it and use the routed netlist as the input to make an incremental compilation. This way you preserve the routing for the clock tree and place all the other modules rather independently as compared to the critical section. I have not worked with any designs in this manner, however I think this is quite possible.Article: 152441
I was looking into exactly this today for something. By default, it seems to display the slowest few nets for each clock domain, and you can set somewhere how many to show. When I tried the GUI today I got a list of about 100. You can right click somewhere and make a user defined "set" and go through and select a list of nets that you want to have in that set.. and it allows you to filter the search to find nets corresponding to a particular module.. you can filter it like *mymodule* to exclude everything else. When I did this it showed the delay information, but not everything else, I'm still trying to figure out how to get the rest (what I really want to know for the moment is minimum clock period). If/when I figure out the rest, I'll report back. Or maybe somebody else already knows this. Steve On 08/23/2011 04:18 PM, kclo4 wrote: > Hi , > > I am currently designing a FPGA Actel Proasci3 and I would like to > know the ressource usage (ram/flipflop...) for each of module of the > project , in Altera and Xilinx they report this information easily but > I don't find it in Actel Designer (we also use synplify for synthesis > so it shall be fine to use synplify reporting too) > > Thank you for your tips! > > AlexisArticle: 152442
Ahh my bad. Right after I hit "send" I realized you are looking for resource usage, not timing information. Well, synplify creates a file called your-design.srr, have you had a look at this file? It can end up being quite large, but maybe the info is there. On 08/23/2011 09:07 PM, Steve B wrote: > I was looking into exactly this today for something. > By default, it seems to display the slowest few nets for each clock > domain, and you can set somewhere how many to show. When I tried the GUI > today I got a list of about 100. > > You can right click somewhere and make a user defined "set" and go > through and select a list of nets that you want to have in that set.. > and it allows you to filter the search to find nets corresponding to a > particular module.. you can filter it like *mymodule* to exclude > everything else. When I did this it showed the delay information, but > not everything else, I'm still trying to figure out how to get the rest > (what I really want to know for the moment is minimum clock period). > If/when I figure out the rest, I'll report back. Or maybe somebody else > already knows this. > > Steve > > > > On 08/23/2011 04:18 PM, kclo4 wrote: >> Hi , >> >> I am currently designing a FPGA Actel Proasci3 and I would like to >> know the ressource usage (ram/flipflop...) for each of module of the >> project , in Altera and Xilinx they report this information easily but >> I don't find it in Actel Designer (we also use synplify for synthesis >> so it shall be fine to use synplify reporting too) >> >> Thank you for your tips! >> >> Alexis >Article: 152443
Im have different sizes of std_logic_vector arrays and want to run functions on different array types where vector sizes are different (array height is unconstrained). Ive looked at subtypes, but cant find a solution. I think it stops because an array doesnt seem to be able to be a subtype of a generic sized array. Does anyone know how to do that?Article: 152444
On Aug 23, 8:45=A0am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
> Im have different sizes of std_logic_vector arrays and =A0want to run
> functions on different array types where vector sizes are different (arra=
y
> height is unconstrained).
> Ive looked at subtypes, but cant find a solution. I think it stops becaus=
e
> an array doesnt seem to be able to be a subtype of a generic sized array.
> Does anyone know how to do that?
I'm not quite sure if I understand what you're asking for, but
functions can work with unconstrained arrays. Inside the function,
one can then determine the bounds of the array with the usual array
attributes (i.e. 'low, 'high, 'range, etc.)
Example:
function foo(my_slv: std_logic_vector) return std_logic is
begin
for i in my_slv'range loop
...
end loop;
...
Does that help?
Kevin Jennings
Article: 152445"KJ" <kkjennings@sbcglobal.net> wrote in message news:436c6b67-aeff-4121-a56a-f9a30f0b8669@a31g2000vbt.googlegroups.com... >On Aug 23, 8:45 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: >> Im have different sizes of std_logic_vector arrays and want to run >> functions on different array types where vector sizes are different >> (array >> height is unconstrained). >> Ive looked at subtypes, but cant find a solution. I think it stops >> because >> an array doesnt seem to be able to be a subtype of a generic sized array. >> Does anyone know how to do that? >I'm not quite sure if I understand what you're asking for, but >functions can work with unconstrained arrays. Inside the function, >one can then determine the bounds of the array with the usual array >attributes (i.e. 'low, 'high, 'range, etc.) >Example: >function foo(my_slv: std_logic_vector) return std_logic is >begin > for i in my_slv'range loop > ... > end loop; >... > >Does that help? Not really but thanks for trying..Your function doesnt work with an array. Ill try to explain better.. I have two array types: type SLVAR1 is array(natural range <>) of std_logic_vector(10 downto 0); type SLVAR2 is array(natural range <>) of std_logic_vector(5 downto 0); I want to pass them both to the same function as generic array size, but since they have different typenames, that is not possible. Is there a way to define those arrays differently so that they can be passed to a common function?Article: 152446
On Tue, 23 Aug 2011 14:45:18 +0200, "Morten Leikvoll" <mleikvol@yahoo.nospam> wrote: >Im have different sizes of std_logic_vector arrays and want to run >functions on different array types where vector sizes are different (array >height is unconstrained). >Ive looked at subtypes, but cant find a solution. I think it stops because >an array doesnt seem to be able to be a subtype of a generic sized array. >Does anyone know how to do that? > That's a nice little resonance. "maxascent" was bothered by exactly this in the recent thread "VHDL Basic Question". True 2-dimensional arrays provide one possible way out, although they will cost you some added trouble. See my latest response in that thread for some sketch ideas. If this is purely testbench code then there are things you can do with access types to give the flexibility you need (and, probably, more than you need). For RTL synthesis... does anyone know the current level of tool support for unconstrained element types in aggregates? Generics on packages? -- Jonathan BromleyArticle: 152447
On Aug 23, 9:05=A0am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > "KJ" <kkjenni...@sbcglobal.net> wrote in message > > news:436c6b67-aeff-4121-a56a-f9a30f0b8669@a31g2000vbt.googlegroups.com... > > > > > > >On Aug 23, 8:45 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > >> Im have different sizes of std_logic_vector arrays and want to run > >> functions on different array types where vector sizes are different > >> (array > >> height is unconstrained). > >> Ive looked at subtypes, but cant find a solution. I think it stops > >> because > >> an array doesnt seem to be able to be a subtype of a generic sized arr= ay. > >> Does anyone know how to do that? > >I'm not quite sure if I understand what you're asking for, but > >functions can work with unconstrained arrays. =A0Inside the function, > >one can then determine the bounds of the array with the usual array > >attributes (i.e. 'low, 'high, 'range, etc.) > >Example: > >function foo(my_slv: =A0std_logic_vector) return std_logic is > >begin > > =A0 for i in my_slv'range loop > > =A0 =A0 =A0... > > =A0 end loop; > >... > > >Does that help? > > Not really but thanks for trying..Your function doesnt work with an array= . > Ill try to explain better.. I have two array types: > type SLVAR1 is array(natural range <>) of std_logic_vector(10 downto 0); > type SLVAR2 is array(natural range <>) of std_logic_vector(5 downto 0); > > I want to pass them both to the same function as generic array size, but > since they have different typenames, that is not possible. > Is there a way to define those arrays differently so that they can be pas= sed > to a common function?- Hide quoted text - > No, but there are a few ways around... 1. VHDL does allow function names to be overloaded so you can define two functions with the same name, one that expects type SLVAR1, the other that expects type SLVAR2. 2. Instead of using arrays of vectors, use a 2 dimensional array. Doing this will likely mean that you need to create additional functions to convert vectors into the appropriate row/column of the 2d array. Kevin JenningsArticle: 152448
"Jonathan Bromley" <spam@oxfordbromley.plus.com> wrote in message news:009757t25iqpq8vag34a0nrd7ibvv91nnr@4ax.com... > On Tue, 23 Aug 2011 14:45:18 +0200, "Morten Leikvoll" > <mleikvol@yahoo.nospam> wrote: > >>Im have different sizes of std_logic_vector arrays and want to run >>functions on different array types where vector sizes are different (array >>height is unconstrained). >>Ive looked at subtypes, but cant find a solution. I think it stops because >>an array doesnt seem to be able to be a subtype of a generic sized array. >>Does anyone know how to do that? >> > That's a nice little resonance. "maxascent" was bothered > by exactly this in the recent thread "VHDL Basic Question". I read that thread but it appeared to be a different Q. It doesnt look like the problem used different sized arrays and my first pri here is to make this clean code. My only option now is to generate one function for each size, wich is a bit awkward. For each size I could convert types and call a more generic function, but I'd like to know if there is an even more clean way to do it. If arrays could be a subtype of another [unconstrained] array, I think it would solve my problem, but I dont think it can?Article: 152449
karl schrunk wrote: > On Aug 19, 11:25 pm, Steve <theec...@gmail.com> wrote: >>>> The 4K7 pullups for PROGRAM_B and INIT_B plus the 330 ohm pullup on Done >>> Is it okay to use the internal pullups for those (by typing HSWAPEN to >>> GND)? >> I strongly advise against it. Resistors cost about one tenth of a cent, >> I can't think of a reason to leave them out. > > Well, board space is a reason -- I'm awful at soldering SMT > components, and a through-hole resistor is a big chunk of real estate. > > But it isn't a good reason. I'll put in the discrete pull-ups. > > >> http://www.xilinx.com/support/answers/35002.htm > > Wow, thanks for that link, that explains a lot. They ought to mention > the internal-resistor-is-only-for-slow-CCLKs rationale in the > configuration guide. You may also want to read through the config guide again. HSWAPEN does not affect all pins. Some dedicated pins are always pulled up, some others are always tristated. DONE is probably the only pin you an get away without pulling up, but only if you set the bitgen configuration to "drive DONE high". -- Gabor
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