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Messages from 15250

Article: 15250
Subject: Re: Inferring IO's
From: Jo Depreitere <jdp_nospam@elis.rug.ac.be>
Date: Tue, 16 Mar 1999 14:58:31 +0100
Links: << >>  << T >>  << A >>
Le mer Michel wrote:
> 
> Jo Depreitere wrote:
> 
> > How does a synthesiser decide what is the top-level entity? Should
> > the inputs and outputs in the port-part of the entity have special
> > attributes? I just have a top-level entity with input and output
> > signals declared in the port section; what more should you do?
> >
> 
> The top level entity is the file wich containts the other files.  And these
> files can contains files too. You can have multi level. The top level
> instantiates the level -1 components. The level -1 instantiates the level -2
> components... and so on.

I know that ;^)

 
> > It was a one-entity architecture (but with more than a single gate).
> > Well, I'll try the one gate approach and see what happens.
> >
> 
> If all you have only one file, this file is your top level. You can instantiate
> components or/and write logic equations inside.

Yup, been there, done that,...



> Do you use vhdl or schematic entry?

VHDL. I'll try to describe the problem: I have a top-level VHDL file that contains
one entity (the top-level of the design) and its architecture. I then synthesise
this file with Foundation Express (Create Implementation) to a Spartan XS05. I do 
*not* check the box to disable the I/O pad insertion and apparently all goes well. 
After this first stage I optimize the chip, and I get no errors. When I subsequently 
export this implementation to an XNF netlist, I get an empty XNF file (containing
only a header and an EOF). Apparently, Express failed to insert I/O pads for the
signals of my entity and therefore has trimmed all logic.

 
> What is your error message exactly?

I got no error messages, but I'm not sure about what the messages and
warnings were (I tried so many different things that I forgot). I'll
try it again this evening and write them down. I'll let you know
tomorrow.


Thanks,

-- 
name   : Jo Depreitere       | University of Ghent
e-mail : jdp@elis.rug.ac.be  | Electronics and Information Systems Dept.
Phone  : ++32+9/264 34 09    | Sint-Pietersnieuwstraat 41, B-9000 Ghent
Fax    : ++32+9/264 35 94    | http://www.elis.rug.ac.be/~jdp
Article: 15251
Subject: Constraints! Constraints and more constraints!
From: "David Murray" <dmurray@iol.ie>
Date: Tue, 16 Mar 1999 15:26:00 -0000
Links: << >>  << T >>  << A >>
Hi there,
    Here's a handy solution for editing constraints files.  The Prism Editor
is designed to handle all kinds of files from Synthesis scripts to
constraints files to report files so no matter what type of files (HDL files
included) you edit,  you get them in color, you get extra functionality
based on these types of files (macros) , and you get lists of commonly used
words (wordlists).
If you are interested then the URL is

 http://www.iol.ie/~dmurray/Prism/Prism_Editor.html

                Regards
                          David Murray


Article: 15252
Subject: Re: Power Estimiation
From: Andres David Garcia Garcia <garcia@elec.enst.fr>
Date: Tue, 16 Mar 1999 16:28:28 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------A2C75AEC01B056F2EA2D486C
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi,

The problem is that vendors are not really interested on power
consumption,
and the equations proposed by them (spec. Altera) contains some factors
that
are not easy to precise, like tog rate, and a K factor that anybody knows
where
it comes. It means that this kind of methods don't works, I compared
measured
VS estimation using vendor's equation and the difference is really big.

I don't know a software that allows to estimate power, all vendors have
create
a excel file to estimate (Altera, Xilinx, Atmel, Actel, Cypress, etc etc
etc),
but if you don't be able to precise the activity rate of each node, you
can not
estimate power. So if you see a tool to estimate power, wathc out!

There are some systems that allows to measure the thermal activity of
circuits,
there are tools to estimate power in Asics, maybe this tools work well.

Andres


Richard Guerin wrote:

> Can anyone suggest a good post-route power estimation method/tool for
> FPGA's ? (realize that this is highly dependent on frequency and
> probability of switching events .... Pav=CL*VDD^2*f)

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--------------A2C75AEC01B056F2EA2D486C--

Article: 15253
Subject: Problems with foundation
From: Andres David Garcia Garcia <garcia@elec.enst.fr>
Date: Tue, 16 Mar 1999 16:31:53 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------0A54AB7D04A097655B5412D6
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I'm trying to install Foundation 1.5i in my computer, and I have
the following error :

pcm : automation caused an exception, exit code 80080005

I'm using windows NT and a license for a IP addresse.

Did anybody see this error message in Foundation 1.5i version?

thank you.

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n:Garcia Garcia;Andres David
tel;pager:http://www-elec.enst.fr/~garcia/index.html
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adr;quoted-printable:;;46, rue Barrault=0D=0A;Paris;;75634;France
fn:PhD Student
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--------------0A54AB7D04A097655B5412D6--

Article: 15254
Subject: Re: How can I improve an adder?
From: brian@shapes.demon.co.uk (Brian Drummond)
Date: Tue, 16 Mar 1999 15:50:04 GMT
Links: << >>  << T >>  << A >>
On Tue, 16 Mar 1999 01:08:18 GMT, tcoonan@mindspring.com (Thomas A.
Coonan) wrote:

>Sounds like a school problem to me!
>Go look for carry-lookahead adders in XILINX app notes on their WWW.
>>I am currently trying to figure out how to improve an adder.  An n-bit
>>adder can be constructed by cascading n full adders in series, with the
>>carry into stage i, Ci, coming from the output of stage i-1. 

Yup, looks like homework.

But here's a goldmine.

http://www.iis.ee.ethz.ch/~zimmi/comp_arith_notes.ps.gz

- Brian

Article: 15255
Subject: Re: How can I improve an adder?
From: mushh@jps.net (David Decker)
Date: Tue, 16 Mar 1999 16:23:09 GMT
Links: << >>  << T >>  << A >>
It's unclear whether you're using the Xilinx built in fast ripple
carry chains. If you're interested in fast adders, you're probably
using some 4000 series family with built in fast ripple carry logic.
Xilinx claims that the built in carry chains are faster than carry
look ahead logic for 16 bit adders and just about as fast as carry
look ahead logic for 32 bit adders. 

As an example, a 32 bit ripple carry adder in the 4000XL family -8
speed grade could run with a clock period of 10.74ns. That clock being
used to register the data entering the adder, and also to register the
output. A 16 bit adder could run with an 8.03ns clock.

How fast do you need your adder? It only takes a second to check
speeds like this with Fliptronics' FlibTime tool, so if you post which
family and which speed grade, and what size adder you're using, I'll
be happy to tell you what speed your system clock could be, using
built in ripple carry logic.

Dave

Lisa Nangel <ln085137@sju.edu> wrote:

>I am currently trying to figure out how to improve an adder.  An n-bit
>adder can be constructed by cascading n full adders in series, with the
>carry into stage i, Ci, coming from the output of stage i-1.  The carry
>into stage 0, C0, is 0.  If each stage takes T nsec to produce its sum
>and carry, the carry into stage i will not be valid until iT nsec after
>the start of the addition.  For large n the time required for the carry
>to ripple through to the high-order stage may be unacceotably long.  I
>want to design an adder that works faster.  I believe that it has
>something to do with Ci being able to be expressed in terms of the
>operand bits Ai-1 and Bi-1 as wekk as the carry Ci-1.  Using this
>relationship it is possible to express Ci as a function of the inputs to
>stages 0 to i-1, so all the carries can be generated simultaneously. 
>Can anyone help to improve the adder?

Dave Decker
Diablo Research Co. LLC

Please use only one 'h' in mush. I'm trying to reduce the spam.



"Animals .  .  . are not brethren they are not 
underlings;  they are other nations, 
caught with ourselves in the net of life and time, 
fellow prisoners of the splendor and travail of 
the earth."
Henry Beston -  The Outermost House
Article: 15256
Subject: Re: Problems with foundation
From: Hobson Frater <hobson@xilinx.com>
Date: Tue, 16 Mar 1999 09:54:54 -0800
Links: << >>  << T >>  << A >>
Andres,

The answer to this as well as many other such questions can be found on
our support website at http://support.xilinx.com.  In this case, type
'80080005' into the text field and hit "Search".  If the answers that
are returned do not solve your problem, you may contact Xilinx Tech.
Support directly by emailing hotline@xilinx.com.

Regards,
Hobson Frater
Xilinx Applications

Article: 15257
Subject: Re: Power Estimiation
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 16 Mar 1999 10:16:16 -0800
Links: << >>  << T >>  << A >>
Thanks, Andres. You hit the nail right on the head.

The existing power consumption estimators are just
bookkeeping spreadsheets that add up all the power
ingredients. The manufacturers obviously know all the
capacitances and the internal voltage swings on each node.
Missing is just one "tiny" ingredient: the toggle rate of
each node.
Finding that toggle rate is left as an "exercise for the
student". Altera's silly invention of a k-factor just tries
to make you believe that everything behaves like a 16-bit
counter. No such luck!

To estimate dynamic power, you need a complete understanding
of all fast-moving nets in the design, which therefore means
you need information about the statistical behavior of all
chip inputs  plus of course the easy part, the internal chip
design.
And you need accuracy. Plus-minus 30% would give you a
two-to-one power uncertainty, which is really worthless when
you are concerned about thermal issues. ( Perhaps acceptable
when you are only concerned about battery life ).

FPGAs have a big advantage over ASICs:
You can try them out without spending a fortune and waiting
for months.
Sounds corny, but it's still the best advice..
I'll be the first to sing the praise of a real power
estimator.
I'm taking singing lessons...

Peter Alfke, not trying to start a flame war.
=====================================

Andres David Garcia Garcia wrote:

> Hi,
>
> The problem is that vendors are not really interested on
> power
> consumption,
> and the equations proposed by them (spec. Altera) contains
> some factors
> that
> are not easy to precise, like tog rate, and a K factor
> that anybody knows
> where
> it comes. It means that this kind of methods don't works,
> I compared
> measured
> VS estimation using vendor's equation and the difference
> is really big.
>
> I don't know a software that allows to estimate power, all
> vendors have
> create
> a excel file to estimate (Altera, Xilinx, Atmel, Actel,
> Cypress, etc etc
> etc),
> but if you don't be able to precise the activity rate of
> each node, you
> can not
> estimate power. So if you see a tool to estimate power,
> wathc out!
>
> There are some systems that allows to measure the thermal
> activity of
> circuits,
> there are tools to estimate power in Asics, maybe this
> tools work well.
>
> Andres
>
> Richard Guerin wrote:
>
> > Can anyone suggest a good post-route power estimation
> method/tool for
> > FPGA's ? (realize that this is highly dependent on
> frequency and
> > probability of switching events .... Pav=CL*VDD^2*f)
>
>                                                  
> -------------------------------------------------------------------------------------------------------------
>
>   PhD Student <garcia@elec.enst.fr>
>   PhD Student on Electronics and Communications
>   Ecole Nationale Superieure des Telecommunications
>   Communications et Electronique
>
>   PhD Student
>   PhD Student on Electronics and Communications     
> <garcia@elec.enst.fr>
>   Ecole Nationale Superieure des Telecommunications  HTML
> Mail
>   Communications et Electronique
>   46, rue Barrault ;Paris;;75634;France             
> Pager: http://www-elec.enst.fr/~garcia/index.html
>                                                      Fax:
> (33-1)45-80-40-36
>                                                      Home:
> (33-1)-44-16-18-90
>                                                      Work:
> (33-1)-45-81-78-03
>   Additional Information:
>   Last Name Garcia Garcia
>   First NameAndres David
>   Version   2.1

  

Article: 15258
Subject: Re: Xilinx routing issue
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Tue, 16 Mar 1999 10:36:03 -0800
Links: << >>  << T >>  << A >>
The "solution" requires one to globally disable a useful optimization.
How about creating a single flop RPM (containing a single FF with
RLOC=R0C0)
and using this for synchronization. Last time I checked, the tools would
not
swipe unused resources from RPMs (even if you wanted them to). Maybe
worth a try?

David Gesswein wrote:
> 
> I just lost several days tracking down a Xilinx problem and thought I would
> pass it on so others don't have the same problem.
> 
> We were having problems with an output being intermittent and finally found
> using epic that the router had created two copies of a flip flop used to
> sync an async input so we had the "same" signal both active and inactive
> depending on which flip flop the logic was connected to.  The GUI button to
> prevent replicating logic doesn't prevent replicating flip flops in the
> same CLB.  They have an solution record
> http://www.xilinx.com/techdocs/3813.htm that you set a special environment
> variable and it won't do this. set CM_EXCLUDE_XQYQ=TRUE

-- 
Tom Burgess
Article: 15259
Subject: Re: Pin constraints of Xilinx - BIG WEAKNESS
From: katem <kate.meilicke@xilinx.com>
Date: Tue, 16 Mar 1999 14:19:00 -0500
Links: << >>  << T >>  << A >>
Bruce,

You should be able to create a constraint from the clock pad to all
ffs.  This will give you the max delay of the clock to all flops;

TIMESPEC clk_to_ff = from pads(clock) to ffs 5;

Then constrant from the pads you are interested in to the ff.

TIMESPEC pad_to_ff = from pads(your_pad) to ffs 10;

This will give you the delay from the pads to the ffs.  You might need
to create timegroups that contain your pads and ffs.

You are correct that hold times are tough.  The problem is when the
clock delay is longer than the data delay.  If you have this condition
there will be a hold time issue.  A rough guess is hold time will be the
clock delay - 70% of the data delay.

Hope this answers your questions,
Kate
Xilinx FAE

Article: 15260
Subject: Re: Xilinx routing issue
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Tue, 16 Mar 1999 12:12:28 -0800
Links: << >>  << T >>  << A >>
Well I checked again, and my proposed fix won't work, even with 2 FF's,
one unused, each explicitly constrained as FFX, FFY. The tools are not
so easily tricked into doing what is wanted.

Tom Burgess wrote:
> 
> The "solution" requires one to globally disable a useful optimization.
> How about creating a single flop RPM (containing a single FF with
> RLOC=R0C0)
> and using this for synchronization. Last time I checked, the tools would
> not
> swipe unused resources from RPMs (even if you wanted them to). Maybe
> worth a try?
> 
> --

> Tom Burgess
Article: 15261
Subject: Re: Power Estimiation
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Tue, 16 Mar 1999 12:40:23 -0800
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
<snipped>
> 
> To estimate dynamic power, you need a complete understanding
> of all fast-moving nets in the design, which therefore means
> you need information about the statistical behavior of all
> chip inputs  plus of course the easy part, the internal chip
> design.

This is what a simulator is for. I am unable to fathom why
simulation software vendors (except at the ultra high-end) have
not provided this feature, though to be fair, I have never tried
to obtain detailed capacitance and node voltage swing data from
an FPGA manufacturer. This SHOULD be available in the sim netlist as
an option, but I don't know of anyone offering it. Still, whatever
the cause, it's a pretty sad state of affairs, technically simple
to fix and vital to many designers, but just not happening right now.
Perhaps if Xilinx (for example) took the initiative here and just
provided the netlist data (and maybe some hints to Aldec)
something might happen.

 (My 2 cents)
 
Tom Burgess
Article: 15262
Subject: Re: Power Estimiation
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 16 Mar 1999 13:33:26 -0800
Links: << >>  << T >>  << A >>
Tom Burgess wrote:

> Peter Alfke wrote:
> >
> <snipped>
> >
> > To estimate dynamic power, you need a complete
> understanding
> > of all fast-moving nets in the design, which therefore
> means
> > you need information about the statistical behavior of
> all
> > chip inputs  plus of course the easy part, the internal
> chip
> > design.
>
> This is what a simulator is for.

Tom, you misunderstood what I wrote.The chip simulator has
all the information about chip performance, but it has no
clue about the statistically averaged board activity.
That's why Xilinx, Altera, et al. cannot solve the problem.
Only your complete system knows how often that interrupt
line, on average, gets activated. The 20 ns response time,
which is of interest to the timing analyzer, says nothing
about the frequency.

Believe me, if it were easy ( or even tough, but possible)
we would have done it ! We recognize the need, but it
involves activities outside the chip.
There are learned papers debating this issue, and as far as
I know, there is no "easy" solution.
But I am still taking singing lessons...

Peter Alfke
  

Article: 15263
Subject: Re: Power Estimiation
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Tue, 16 Mar 1999 14:27:43 -0800
Links: << >>  << T >>  << A >>
I guess I should have expanded on what I would consider a useful
power estimate. I would be happy if I could exercise a single
FPGA simulation with a set of user-constructed stimulus vectors
representative of normal operation (say running a few hundred
random values through a signal processing pipeline),
have the simulator collect the internal node switching statistics,
then apply switching cost factors and do the sums to get power
statistics - valid for that test pattern.

Seems not too much to ask, and not too far from what
I do to functionally verify a design anyway. Board-level simulation
and automatic test pattern generation would be nice, but are not
really required (even if they were affordable).
 
Could it be that most FPGA designers will not have the patience to
construct power test vectors (or any test vectors at all),
expect the software to do everything on a pushbutton basis, and
will complain if results are inaccurate due to lack of any useful
activity data? If this is the case then I'm afraid it's hopeless indeed.

Peter Alfke wrote:
> 
> Tom, you misunderstood what I wrote.The chip simulator has
> all the information about chip performance, but it has no
> clue about the statistically averaged board activity.
> That's why Xilinx, Altera, et al. cannot solve the problem.
> Only your complete system knows how often that interrupt
> line, on average, gets activated. The 20 ns response time,
> which is of interest to the timing analyzer, says nothing
> about the frequency.
> 
> Believe me, if it were easy ( or even tough, but possible)
> we would have done it ! We recognize the need, but it
> involves activities outside the chip.
> There are learned papers debating this issue, and as far as
> I know, there is no "easy" solution.
> But I am still taking singing lessons...
> 
> Peter Alfke
> 

-- 
Tom Burgess
Article: 15264
Subject: Re: Problems with foundation
From: Gerhard Hoffmann <ghf@berlin.snafu.de>
Date: Wed, 17 Mar 1999 00:01:34 +0100
Links: << >>  << T >>  << A >>
Andres David Garcia Garcia wrote:
> 
> I'm trying to install Foundation 1.5i in my computer, and I have
> the following error :
> 
> pcm : automation caused an exception, exit code 80080005 
> Did anybody see this error message in Foundation 1.5i version?

I think I had this problem when installing 1.5 / Win95 ( but I'm
not absolutely sure about the exit code). 
The reason was that there was not enough environment space left.

The FAE told me that it was _my_ responsibilty to have enough
environment space, but how can I know it if the installation
program does not complain ("environment full" like "disk full")
and the installed program says only "exit code xyzzy" instead
of ("cannot find path to my executables");

I had some other installation problems ( installing xc4000xl only
does not work, installing all default families does, trouble
with online manuals), so the 1.5i update is unopened on the shelf
until I either need it badly for some reason or have some spare time.


Gerhard

-- 
on the air:    DK4XP
in the air:    D-8551
Article: 15265
Subject: Re: Inferring IO's
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Tue, 16 Mar 1999 16:39:25 -0700
Links: << >>  << T >>  << A >>
Jo Depreitere wrote in message <36EE42D4.7C651403@elis.rug.ac.be>...

>How does a synthesiser decide what is the top-level entity? Should
>the inputs and outputs in the port-part of the entity have special
>attributes? I just have a top-level entity with input and output
>signals declared in the port section; what more should you do?


When using FPGA Express, you tell it which file contains your top-level
entity. Let's use the FPGA Express GUI 'cause it's simple to start from
there. First, add all of your sources.  They should automatically analyze
when you add them, and you can always force them to be analyzed. In the GUI,
there's a list-box that contains all of your entities.  Click that list box
and select the name of the top-level entity.  That's all there is to it.


Jonathan:
>> My own preference has always been to keep the VHDL/Verilog technology-
>> independent, build a schematic symbol to represent the top-level entity,
>> then drop that down in a top-level schematic which has I/O pads and
>> buffers as well.
>
>Yes, that's what I've done first; and this works well. I just wanted
>to try all different aspects (full-VHDL, mixed VHDL/schematics,
XNF-netlists
>instantiated in VHDL, and so on).


My designs are all-VHDL and I haven't had a problem getting I/O pads to
automatically instantiate.  (I did have a problem with IOFFs, but that was
"user error.")


-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

Don't waste apostrophes!  The plural of the acronym for "personal computers"
is PCs, NOT PC's.



Article: 15266
Subject: Re: Power Estimiation
From: Richard Guerin <guerin2@home.com>
Date: Wed, 17 Mar 1999 01:41:22 GMT
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------DB281E93BF5C3148FE68530E
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Tom makes some excellent and sensible points. Keeping track of switching
activity is exactly what a simulator does and any good FPGA designer
would undoubtedly perform a post-route simulation as part of the normal
verification process ... hopefully using a set of meaningful test
vectors.  

In a standard cell process, a chip designer(s) could extract a post
layout transistor level SPICE netlist, add some user defined stimulus
and a power measuring circuit (i.e. something as simple as a
current-controlled voltage source and an RC network), run a transient
analysis over some given period, and then view some fairly accurate
results (after a couple of days ;-)

This is a little more pain than I would personally want to endure for
FPGA based designs, but I agree with Tom ... a 1st order estimation of
power consumption seems like it should be fairly straight forward and
integral to a simulator environment ... the basic technique for
extracting node/gate parasitics needed for power simulation seems like
it should be similar to those already employed by place & route tools 
for extracting a timing model (i.e. netlist & SDF file).

Guess the good news is that there is hope on the foreseeable horizon ...
Keep checking the IEEE P1481 Delay & Power Calculation Working Group 
site http://www.eda.org/dpc/ 

BTW ... Does this mean that VITAL will become obsolete ?



Tom Burgess wrote:
> 
> I guess I should have expanded on what I would consider a useful
> power estimate. I would be happy if I could exercise a single
> FPGA simulation with a set of user-constructed stimulus vectors
> representative of normal operation (say running a few hundred
> random values through a signal processing pipeline),
> have the simulator collect the internal node switching statistics,
> then apply switching cost factors and do the sums to get power
> statistics - valid for that test pattern.
> 
> Seems not too much to ask, and not too far from what
> I do to functionally verify a design anyway. Board-level simulation
> and automatic test pattern generation would be nice, but are not
> really required (even if they were affordable).
> 
> Could it be that most FPGA designers will not have the patience to
> construct power test vectors (or any test vectors at all),
> expect the software to do everything on a pushbutton basis, and
> will complain if results are inaccurate due to lack of any useful
> activity data? If this is the case then I'm afraid it's hopeless indeed.
> 
> Peter Alfke wrote:
> >
> > Tom, you misunderstood what I wrote.The chip simulator has
> > all the information about chip performance, but it has no
> > clue about the statistically averaged board activity.
> > That's why Xilinx, Altera, et al. cannot solve the problem.
> > Only your complete system knows how often that interrupt
> > line, on average, gets activated. The 20 ns response time,
> > which is of interest to the timing analyzer, says nothing
> > about the frequency.
> >
> > Believe me, if it were easy ( or even tough, but possible)
> > we would have done it ! We recognize the need, but it
> > involves activities outside the chip.
> > There are learned papers debating this issue, and as far as
> > I know, there is no "easy" solution.
> > But I am still taking singing lessons...
> >
> > Peter Alfke
> >
> 
> --
> Tom Burgess
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Article: 15267
Subject: Re: How can I improve an adder?
From: Richard Guerin <guerin2@home.com>
Date: Wed, 17 Mar 1999 02:44:32 GMT
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Some academic information regarding digital arithmetic ...

http://infopad.EECS.Berkeley.EDU/~icdesign/ee141_f98/Notes/lecture16_17.pdf

Lisa Nangel wrote:
> 
> I am currently trying to figure out how to improve an adder.  An n-bit
> adder can be constructed by cascading n full adders in series, with the
> carry into stage i, Ci, coming from the output of stage i-1.  The carry
> into stage 0, C0, is 0.  If each stage takes T nsec to produce its sum
> and carry, the carry into stage i will not be valid until iT nsec after
> the start of the addition.  For large n the time required for the carry
> to ripple through to the high-order stage may be unacceotably long.  I
> want to design an adder that works faster.  I believe that it has
> something to do with Ci being able to be expressed in terms of the
> operand bits Ai-1 and Bi-1 as wekk as the carry Ci-1.  Using this
> relationship it is possible to express Ci as a function of the inputs to
> stages 0 to i-1, so all the carries can be generated simultaneously.
> Can anyone help to improve the adder?
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Article: 15268
Subject: Job Openings -- Tampa Bay Area
From: brogle@worldnet.att.net (Richard Brogle)
Date: 17 Mar 1999 04:21:11 GMT
Links: << >>  << T >>  << A >>


Constellation Technology  currently has 3 job openings for embedded
systems designers.  This is both hardware and firmware/software
develoment.  One is for entry level, and the other two are for the
more experienced.  Some of the skills we are looking for:


Two positions relating to:


Firmware:

Strong 'C' background with embedded systems
Assembly, especially 80C51XA, PIC 16x, Atmel AVR, and TI 320C30/31.
Experience with RTOSs is a plus.

Hardware:

Experience with 80C51XA (16 bit), PICs, AVRs, and TI DSPs
FPGA design, particularly Altera 6K, 8K, and 10K series using MAXplus2

VHDL experience a plus.

....................................................................................

One opening (this could be contract, short term consulting, or
permanent):

Strong 'C' and assembly background, especailly for TI DSPs 320C31
DSP algorithm develpoment experience.
Use of Matlab for algorithm development.
Experience with DSP based motor control a plus,  
DSP base vibration cancellation a huge plus.


We are a small hi-tech company in the Tampa Bay area.  These positions
will require a DOD security clearance.

For more details on the company and positions, please see our website:
www.contech.com.  All of these jobs may not yet be posted on our site.
Please reply anyway to  brogleATcontechDOTcom.


Rick Brogle





Article: 15269
Subject: help!
From: label <label@bsing.ing.unibs.it>
Date: Wed, 17 Mar 1999 08:12:25 +0100
Links: << >>  << T >>  << A >>
hello!
i'm looking for a design of a multiplier (16 bit) and a adder (19bit)
using FPGA xc4005.
I want to design a FFT module on FPGA
Thanks.
Article: 15270
Subject: Re: Inferring IO's
From: Le mer Michel <michel.lemer@ago.fr>
Date: Wed, 17 Mar 1999 09:45:03 +0100
Links: << >>  << T >>  << A >>
Jo Depreitere wrote:

> Le mer Michel wrote:
> >
> > Jo Depreitere wrote:
> >
> > > How does a synthesiser decide what is the top-level entity? Should
> > > the inputs and outputs in the port-part of the entity have special
> > > attributes? I just have a top-level entity with input and output
> > > signals declared in the port section; what more should you do?
> > >
> >
> > The top level entity is the file wich containts the other files.  And these
> > files can contains files too. You can have multi level. The top level
> > instantiates the level -1 components. The level -1 instantiates the level -2
> > components... and so on.
>
> I know that ;^)
>
>
> > > It was a one-entity architecture (but with more than a single gate).
> > > Well, I'll try the one gate approach and see what happens.
> > >
> >
> > If all you have only one file, this file is your top level. You can instantiate
> > components or/and write logic equations inside.
>
> Yup, been there, done that,...
>
> > Do you use vhdl or schematic entry?
>
> VHDL. I'll try to describe the problem: I have a top-level VHDL file that contains
> one entity (the top-level of the design) and its architecture. I then synthesise
> this file with Foundation Express (Create Implementation) to a Spartan XS05. I do
> *not* check the box to disable the I/O pad insertion and apparently all goes well.
> After this first stage I optimize the chip, and I get no errors.

Here, you should have a netlist file. file.edf or file.xnf. This netlist is used by the
PAR tool. (place and route).


> When I subsequently
> export this implementation to an XNF netlist, I get an empty XNF file (containing
> only a header and an EOF). Apparently, Express failed to insert I/O pads for the
> signals of my entity and therefore has trimmed all logic.
>
>

Export an netlist is for a simulation (with a third party tool) goal. This is a
different netlist.

>
> > What is your error message exactly?
>
> I got no error messages, but I'm not sure about what the messages and
> warnings were (I tried so many different things that I forgot). I'll
> try it again this evening and write them down. I'll let you know
> tomorrow.
>
> Thanks,
>
> --
> name   : Jo Depreitere       | University of Ghent
> e-mail : jdp@elis.rug.ac.be  | Electronics and Information Systems Dept.
> Phone  : ++32+9/264 34 09    | Sint-Pietersnieuwstraat 41, B-9000 Ghent
> Fax    : ++32+9/264 35 94    | http://www.elis.rug.ac.be/~jdp

I have not the same tool review. I work with Foundation M1.5i.
Why do you open the FPGA express tool? Can you open Foundation and synthesise from this
tool?

Michel Le Mer
Gerpi sa (Xilinx Xpert)
3, rue du Bosphore
Alma city
35000 Rennes
France
(02 99 51 17 18)
http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm

Article: 15271
Subject: Re: Problems with foundation
From: Le mer Michel <michel.lemer@ago.fr>
Date: Wed, 17 Mar 1999 09:49:45 +0100
Links: << >>  << T >>  << A >>
Hobson Frater wrote:

> Andres,
>
> The answer to this as well as many other such questions can be found on
> our support website at http://support.xilinx.com.  In this case, type
> '80080005' into the text field and hit "Search".  If the answers that
> are returned do not solve your problem, you may contact Xilinx Tech.
> Support directly by emailing hotline@xilinx.com.
>
> Regards,
> Hobson Frater
> Xilinx Applications

Or frhelp@xilinx.com for the French hotline. Anyway, because you have a
french address, the hotline will send you message to the french one.

Do not forget to install the patches.


Michel Le Mer
Gerpi sa (Xilinx Xpert)
3, rue du Bosphore
Alma city
35000 Rennes
France
(02 99 51 17 18)
http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm

Article: 15272
Subject: Re: help!
From: Le mer Michel <michel.lemer@ago.fr>
Date: Wed, 17 Mar 1999 09:54:20 +0100
Links: << >>  << T >>  << A >>
label wrote:

> hello!
> i'm looking for a design of a multiplier (16 bit) and a adder (19bit)
> using FPGA xc4005.
> I want to design a FFT module on FPGA
> Thanks.

You can try Coregen. It is a Xilinx tool to generate hard macro.

Bye.

Michel Le Mer
Gerpi sa (Xilinx Xpert)
3, rue du Bosphore
Alma city
35000 Rennes
France
(02 99 51 17 18)
http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm

Article: 15273
Subject: PGCK and SGCK
From: Davide Falchieri <davide.falchieri@bo.infn.it>
Date: Wed, 17 Mar 1999 10:04:26 +0100
Links: << >>  << T >>  << A >>
Hi all,
  I am working with Xilinx FPGA XC4025E using Synopsys as front end tool
and Alliance 1.5 as back end one. I wanted to ask you what is the
difference between primary global clock input (PGCK) and secondary ones
(SGCK). In fact I am trying to force my clock input on a PGCK pad and I
have an error from M1, whereas if I put it on a SGCK all works properly.
Any help will be greatly appreciated.

Thank you.

Sincerely,
      Davide  

_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
                                                      
                      Davide Falchieri                
                                                       
              VLSI & Fuzzy Logic Research Group       
                                                      
           Physics Department, Bologna University     
                                                      
        40127,Viale Berti Pichat 6/2, Bologna(ITALY)      
                                                      
           TEL:+39-51-6305077, FAX:+39-51-6305297          
                                                      
           URL:http://sunvlsi4.bo.infn.it/~davide     
                                                      
            e-mail : davide.falchieri@bo.infn.it     
                                                      
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Article: 15274
Subject: Re: Inferring IO's
From: Jo Depreitere <jdp_nospam@elis.rug.ac.be>
Date: Wed, 17 Mar 1999 10:08:16 +0100
Links: << >>  << T >>  << A >>
Le mer Michel wrote:
> 
> I have not the same tool review. I work with Foundation M1.5i.
> Why do you open the FPGA express tool? Can you open Foundation and synthesise from this
> tool?

In the Xilinx Foundation Series v1.4, Foundation Express is still a stand-alone
tool. And the export netlist feature of v1.4 creates the xnf-file. So, I followed
the right design flow. 

But ..., yesterday I re-converted my design containing the instantiated I/O bufs 
to a design without the instantiations and all seemed to work fine. Foundation
Express *did* insert I/O bufs and pads at the top-level entity. I do not know
what caused my original problems (my guess is that I accidently left the outputs
commented out in the VHDL code), but they seem solved now.


Sorry to have troubled you with a non-problem.

Thanks for your reactions anyway,

-- 
name   : Jo Depreitere       | University of Ghent
e-mail : jdp@elis.rug.ac.be  | Electronics and Information Systems Dept.
Phone  : ++32+9/264 34 09    | Sint-Pietersnieuwstraat 41, B-9000 Ghent
Fax    : ++32+9/264 35 94    | http://www.elis.rug.ac.be/~jdp


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