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On Aug 29, 8:42=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > i wanted to know whether there exists any software that can be used to kn= ow > whether all the balls of my bga grid are properly fixed in place or not. > Actually i am using spartan 3 xc3s4000 and maxim 28544 in my design and i > cannot program the maxim through FPGA. When same code is used on another > design, maxim gets programmed. So it made me think to look for some kind = of > software that can tell me if there's exists a connection between my FPGA > and maxim.Or in other words it can verify if my FPGA stuffing is right or > not. > > Regards > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I can't find any Maxim 28544 (nor MAX28544) part, but if this part does not have a JTAG interface then any board level testing will be incomplete. You should be able to test if there is a short, but you won't be able to test if the FPGA is connected to the Maxim part. There are mutiple vendors that provide JTAG PCB software solutions as a quick Google search will show: http://www.lmgtfy.com/?q=3DJTAG+boundary+scan+testing Ed McGettigan -- Xilinx Inc.Article: 152501
The Python community is about to offer us a free lunch.
A new compliant interpreter, pypy, is already 4.3x faster
than cPython, and getting faster everyday. It shows
that there is not conceptual reason why high-level
dynamic languages should be slow.
For MyHDL, an HDL implemented as a Python library, the
results are even more spectacular: my benchmarks run
8-20x faster on pypy. In a single strike, this makes
MyHDL simulation performance competitive with Verilog/VHDL.
http://myhdl.org/doku.php/performance
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
World-class digital design: http://www.easics.com
Article: 152502Hi All, I remember a while ago I read an article on Xilinx website regarding low power modes of DSP blocks and Block RAMs on newer virtex devices (V6 and V7 I guess). I know of suspend mode in Spartan devices to reduce leakage which I think is for all FPGA fabric including BRAMs and DSPs. However I'm pretty sure that there were similar features (for example to turn off unused DSP blocks) for newer virtex devices. I digged all the recent white papers about power consumption and yet I can't find a single document implying such features. Can you please help find this document or let me know if I'm wrong? Thanks a lot for your help. AmirArticle: 152503
Ed McGettigan wrote: > On Aug 29, 8:42 am, "salimbaba" > <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >> Hi, >> i wanted to know whether there exists any software that can be used to know >> whether all the balls of my bga grid are properly fixed in place or not. >> Actually i am using spartan 3 xc3s4000 and maxim 28544 in my design and i >> cannot program the maxim through FPGA. When same code is used on another >> design, maxim gets programmed. So it made me think to look for some kind of >> software that can tell me if there's exists a connection between my FPGA >> and maxim.Or in other words it can verify if my FPGA stuffing is right or >> not. >> >> Regards >> >> --------------------------------------- >> Posted throughhttp://www.FPGARelated.com > > I can't find any Maxim 28544 (nor MAX28544) part, but if this part > does not have a JTAG interface then any board level testing will be > incomplete. You should be able to test if there is a short, but you > won't be able to test if the FPGA is connected to the Maxim part. > > There are mutiple vendors that provide JTAG PCB software solutions as > a quick Google search will show: > http://www.lmgtfy.com/?q=JTAG+boundary+scan+testing > Ed McGettigan > -- > Xilinx Inc. There's a simple method to check for open circuits on FPGA IO pins. If you can get to the net on the board surface somewhere (at the Maxim part?) you can use a multimeter in diode-check mode. Connect the positive multimeter lead to ground and the negative lead to the net under test. You should be able to read the forward drop of the ground clamp diode in the FPGA this way. Normally you would need to disconnect other loads from the net, but if the ground clamps on the Maxim part have a higher Vf, then you should be able to tell if some FPGA pins are not connected even without removing the other part. I've found that the Vf of the clamps of any given part are quite consistent, so even 100 mV above the other readings is enough to tell you that a pin is disconnected. -- GaborArticle: 152504
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: (snip) > I can't find any Maxim 28544 (nor MAX28544) part, but if this part > does not have a JTAG interface then any board level testing will be > incomplete. You should be able to test if there is a short, but you > won't be able to test if the FPGA is connected to the Maxim part. The usual way to test I/O devices like serial ports is to put a loop-back plug into the connector, send a signal out, and see if the right signal comes back. That requries a little outside help, but also tests more parts. -- glenArticle: 152505
Have a look at our Polmaddie3 http://www.enterpoint.co.uk/polmaddie/polmadd= ie3.html. If you really want to cut costs this board has an option to drive the JTAG chain as a bit bash from the on-board FT232 chip that also forms a serial port connection. As yet we don't have formal support for this feature but we do of a customer that has used it successfully in another of products with the same feature. This cheap JTAG connection will need the fit of resistor array, or solder bridges, and the work of getting the bit bash to work. Otherwise we do have our own ISE compatible USB programming cable. Price for this board with parallel port cable GBP =A340 / USD $68 + VAT (if applys) or with USB programming cable option GBP =A390 / USD $153. We also have a another not widely known product Prog4 that has a FT245 front end but can not support the bit-bash JTAG at a similar price point. It's main use is as a programming cable for our Altera based products but we also sell it as a development board. It has slightly less I/O but is physically smaller. Like the Polmaddie3 it has a XC3S50AN FPGA. Details of Prog4 http://www.enterpoint.co.uk/programming_sol= utions/prog4.html. John Adair Enterpoint Ltd. On Aug 28, 3:23=A0pm, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > Hi, > I would like to know which is the smallest (read cheapest) board with a > Spartan3 that can be programmed directly by a usb cable. > > I just need a couple to test a design that must be operated remotely and > in the need of a change in the fpga I would not bother the other party > with much software/hardware issues. > > Budget is very tight, there are no many requirements for the board > itself, a bunch of I/O (less than 20) and I would need to add a serial > LCD, a couple of quad encoders and some buttons. > > Serial port and/or USB data exchange at plus. > > Ideally, I use a Xylo-LM that has a very easy programming method, sadly > way overbudget. > > TIA. > > Giuseppe MarulloArticle: 152506
Hi, maybe you'll find something here: http://www.trenz-electronic.de markus Am 28.08.2011 16:23, schrieb Giuseppe Marullo: > Hi, > I would like to know which is the smallest (read cheapest) board with a > Spartan3 that can be programmed directly by a usb cable. > > I just need a couple to test a design that must be operated remotely and > in the need of a change in the fpga I would not bother the other party > with much software/hardware issues. > > Budget is very tight, there are no many requirements for the board > itself, a bunch of I/O (less than 20) and I would need to add a serial > LCD, a couple of quad encoders and some buttons. > > Serial port and/or USB data exchange at plus. > > Ideally, I use a Xylo-LM that has a very easy programming method, sadly > way overbudget. > > TIA. > > Giuseppe MarulloArticle: 152507
Hi, maybe you'll find something here: http://www.trenz-electronic.de The Industrial Micromodules made by Trenz are programmable via USB and kinda cheap. markus Am 28.08.2011 16:23, schrieb Giuseppe Marullo: > Hi, > I would like to know which is the smallest (read cheapest) board with a > Spartan3 that can be programmed directly by a usb cable. > > I just need a couple to test a design that must be operated remotely and > in the need of a change in the fpga I would not bother the other party > with much software/hardware issues. > > Budget is very tight, there are no many requirements for the board > itself, a bunch of I/O (less than 20) and I would need to add a serial > LCD, a couple of quad encoders and some buttons. > > Serial port and/or USB data exchange at plus. > > Ideally, I use a Xylo-LM that has a very easy programming method, sadly > way overbudget. > > TIA. > > Giuseppe MarulloArticle: 152508
On Aug 29, 1:47=A0pm, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > Thanks to all for your answers, really good advices. > I need to build a "high speed" HST IAMBIC keyer. If you want USB and cheap, then the Lattice offerings are hard to go past. They have 2 candidates: $30- called 'Breakout', but includes a FT2232H for ISP. http://www.latticesemi.com/products/developmenthardware/breakoutboardevalki= ts.cfm?source=3Dtopnav and also $29, with a small LCD, and FT2232H connected for UART on the second channel (JTAG Pgm on the other) http://www.latticesemi.com/products/developmenthardware/developmentkits/mac= hxo2picokit.cfm?source=3Dbanner or, there are Micro boards, this one even has a small speaker. http://www.atmel.com/dyn/resources/prod_images/XMEGA_A1_xplained_th.jpgArticle: 152509
On Aug 30, 5:27=A0am, Jan Decaluwe <j...@jandecaluwe.com> wrote: > For MyHDL, an HDL implemented as a Python library, the > results are even more spectacular: my benchmarks run > 8-20x faster on pypy. In a single strike, this makes > MyHDL simulation performance competitive with Verilog/VHDL. > > =A0 =A0 =A0http://myhdl.org/doku.php/performance Impressive. Do the pypy team have your code to use as a Version Test ?Article: 152510
Jan Decaluwe <jan@jandecaluwe.com> wrote: >The Python community is about to offer us a free lunch. >A new compliant interpreter, pypy, is already 4.3x faster >than cPython, and getting faster everyday. It shows >that there is not conceptual reason why high-level >dynamic languages should be slow. Did you even try this with your program? http://psyco.sourceforge.net/ Sounds more than one group is speeding up Python. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 152511
>> Not Spartan 3 but Spartan 6: >> >> http://www.sioi.com.au/shop/product_info.php/products_id/47 >> >> 28.13 euros for a Spartan 6, 4Mb Flash, 32MB DDR SDRAM, 38 IO >> expansion plus separate 6 IO expansion >> >> You can program it with a JTAG cable that has the Xilinx 14 pin JTAG >> connector. >> >> Stephen Stephen, very aggressive price but I don't want the other ham to play with parallel cables. I don't even own a USB programmer cable myself. My Xylo-LM can be programmed by the FX2 USB chip, I did purchase the el-cheapo parallel cable (I have a old digilent board with Sump LA analyzer on it) and another Xilinx/Altera compatible one from KNJN but it is a PITA on today's computers, parallel port is simply dead. I have somewhat high end laptop (x7200) and there is no pcmcia or parallel port. Antoher (usual) problem is the esoteric I/O connector, otherwise it could be a good fit. >If you want USB and cheap, then the Lattice offerings are hard to go >past. Jim, I have so much to learn with Xilinx I can't afford to switch vendor...at least I know how to create a bitfile and do a very basic simulation with WebISE. >Have a look at our Polmaddie3 http://www.enterpoint.co.uk/polmaddie>>>/polmaddie3.html. John, this one does not have programming capabilities from USB, which I would like. The Prog4 could work but I need a ready to run board, I would like something working without much fiddling/thinkering, not only for me but specially for my friend. He is a fine brass pounder with his Vibroplex but I am pretty sure not much tolerant with the quirks of bitfile programming webise/impact and cables. I fear that at the first problem he would ship the board back to me, so it is really hit/miss situation. >> > > Another spartan 6 possibility with the USB built-in: > > http://www.em.avnet.com/ctf_shared/evk/df2df2usa/xlx-s6-lx9-microboard-pb040811.pdf > > > $89.00 US at Avnet. > > I'm not sure if the 2 PMOD connectors have enough I/O for you, though. > > -- Gabor Gabor, they should suffice: 2 input for the paddles 3 x 2 input for 3 quad encoders (maximum) 2 x CW output (one is the Keyout for the radio and the other is the Tone) 1 x Serial LCD output This board is 89EUR from Trenz (that has a lot of interesting stuff, sadly not cheap for my needs (micromodules) or lacks USB programming (OHO Elektronik), and there is a discount if purchased during AVNet presentation seminars. Yes, I have enrolled in one (end of November in Milan). Maybe I could buy two at discounted rate and my problems will be solved while I progress in the development. It has a device-locked SDK license and ChipScope (much more that I could expect). The only thing I need to understand is if I could use it to try also the Microblaze (NOT FOR THIS PROJECT!). Giuseppe MarulloArticle: 152512
On Aug 30, 12:26=A0pm, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > =A0>If you want USB and cheap, then the Lattice offerings are hard to go > =A0>past. > > Jim, I have so much to learn with Xilinx I can't afford to switch > vendor...at least I know how to create a bitfile and do a very basic > simulation with WebISE. It is not that hard to flip across vendor's tools ? The two Lattice choices I gave have different tool flows, and I'd suggest the Breakout 4256ZE : less overall logic, but the IspLEVER tools give better reports, and run faster from my brief tests. IspLever is a little more cumbersome on the install. -jgArticle: 152513
On 30/08/2011 01:45, Nico Coesel wrote: > Jan Decaluwe<jan@jandecaluwe.com> wrote: > >> The Python community is about to offer us a free lunch. >> A new compliant interpreter, pypy, is already 4.3x faster >> than cPython, and getting faster everyday. It shows >> that there is not conceptual reason why high-level >> dynamic languages should be slow. > > Did you even try this with your program? > http://psyco.sourceforge.net/ > > Sounds more than one group is speeding up Python. > pscyo is an interesting project, and I've used it to speed up Python code. However, the project has been basically dead for 5 years (other than some updated builds for newer python releases on non-Linux platforms), since the guy behind it moved his effort over to the more flexible and future-oriented pypy project. In particular, pscyo is limited to 32-bit x86 cpus, while pypy is aimed at a range of targets - including 64-bit amd64.Article: 152514
On 08/30/2011 09:19 AM, David Brown wrote:
> On 30/08/2011 01:45, Nico Coesel wrote:
>> Jan Decaluwe<jan@jandecaluwe.com> wrote:
>>
>>> The Python community is about to offer us a free lunch. A new
>>> compliant interpreter, pypy, is already 4.3x faster than cPython,
>>> and getting faster everyday. It shows that there is not
>>> conceptual reason why high-level dynamic languages should be
>>> slow.
>>
>> Did you even try this with your program?
>> http://psyco.sourceforge.net/
>>
>> Sounds more than one group is speeding up Python.
>>
>
> pscyo is an interesting project, and I've used it to speed up Python
> code. However, the project has been basically dead for 5 years (other
> than some updated builds for newer python releases on non-Linux
> platforms), since the guy behind it moved his effort over to the more
> flexible and future-oriented pypy project. In particular, pscyo is
> limited to 32-bit x86 cpus, while pypy is aimed at a range of targets
> - including 64-bit amd64.
In addition, psycho doesn't accelerate generators, which are
the name of the game in MyHDL. However, through psycho I got to
track Armin Rigo as someone who can do miracles :-)
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
World-class digital design: http://www.easics.com
Article: 152515
On 08/30/2011 12:12 AM, Jim Granville wrote:
> On Aug 30, 5:27 am, Jan Decaluwe<j...@jandecaluwe.com> wrote:
>> For MyHDL, an HDL implemented as a Python library, the
>> results are even more spectacular: my benchmarks run
>> 8-20x faster on pypy. In a single strike, this makes
>> MyHDL simulation performance competitive with Verilog/VHDL.
>>
>> http://myhdl.org/doku.php/performance
>
> Impressive.
> Do the pypy team have your code to use as a Version Test ?
I don't think they use it now, but they are very aware of the
project, and it's all open source, so I'll leave that to their
good judgement.
With MyHDL, I found one bug in PyPy 1.5 which has been fixed
and added to the PyPy regression test suite, which must be
very broad by now.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
World-class digital design: http://www.easics.com
Article: 152516> yup, so the SDRAM will appear as an on chip block.... even though it > locates few inches away... Nope. On chip, you know when data arrives with respect to clock.Article: 152517
Hi, I am using Virtex II Pro (XC2VP30, package ff896) board to read 8 bit parallel data from FPGA. The output from the chip is of level 1.2V and hence I am using SSTL2_II IO standard for the inputs from the chip to the FPGA. I had designed my board to use the Pins A20 to A27 of the High speed IO bank J37 for reading the inputs from the chip. I have shared the ucf files for the not working and working case in the links below. not working ucf: https://docs.google.com/leaf?id=0B68lizyh4WNKMGFiYmI4OWQtNTQ3Ny00YzUwLThmNmEtODAzM2NhNThiY2Vl&hl=en_US working ucf: https://docs.google.com/leaf?id=0B68lizyh4WNKYTA0YzFkYzctNGY3Yi00MDFjLThmNGYtYmU0M2Y1MDZjNzBl&hl=en_US In the working ucf file, the only change I have done is, I have not used A23 and instead A31 pin of J37(L8 pin of FPGA). I checked with the Virtex II Pro data sheet and don't see any problem using A23 pin of J37. In fact, even if I remove all other constraints and just use the A23 pin also, I get the same error: Below is the link to the .par file for this failed trial. https://docs.google.com/leaf?id=0B68lizyh4WNKMzViNDhkOWQtYTE5OS00NGQ2LTkzMWYtY2VjNDUzMTA4NmI4&hl=en_US ERROR:Place:897 - The following IOBs have been locked (LOC constraint) to the I/O bank 3. They require a voltage reference supply from the VREF pin(s) within the same I/O bank to be available. The following VREF pins are currently locked and can't be used to supply the necessary reference IO Standard: Name = SSTL2_II, VREF = 1.25, VCCO = NR, TERM = NONE List of locked IOB's: DATA_OUT<3> List of occupied VREF Sites: VREF site PAD289 is occupied by comp DATA_OUT<3> Is there something fishy about this A23 pin of J37 bank of the board? If I use LVTTL IO standard, it works fine, but I can't read 1.2 volts in that standard. Why is the behavior of this particular pin dirrefent from all it's adjacent pins? Is there any other IO standard which can help reading 1.2 Volt as logic high? I have confirmed that it doesn't work for IO standard= SSTL2_I too. If there is any document to explain this strange behavior, please point me to that. Waiting for some helpful answers. Thanks and regards, PratapArticle: 152518
On Aug 30, 5:38=A0am, Pratap <pratap.i...@gmail.com> wrote: > Hi, > I am using Virtex II Pro (XC2VP30, package ff896) board to read 8 bit > parallel data from FPGA. The output from the chip is of level 1.2V and > hence I am using SSTL2_II IO standard for the inputs from the chip to > the FPGA. I had designed my board to use the Pins A20 to A27 of the > High speed IO bank J37 for reading the inputs from the chip. > I have shared the ucf files for the not working and working case in > the links below. > > not working ucf:https://docs.google.com/leaf?id=3D0B68lizyh4WNKMGFiYmI4OW= QtNTQ3Ny00YzUw... > > working ucf:https://docs.google.com/leaf?id=3D0B68lizyh4WNKYTA0YzFkYzctNG= Y3Yi00MDFj... > > In the working ucf file, the only change I have done is, I have not > used A23 and instead A31 pin of J37(L8 pin of FPGA). I checked with > the Virtex II Pro data sheet and don't see any problem using A23 pin > of J37. In fact, even if I remove all other constraints and just use > the A23 pin also, I get the same error: Below is the link to the .par > file for this failed trial. > > https://docs.google.com/leaf?id=3D0B68lizyh4WNKMzViNDhkOWQtYTE5OS00NGQ2..= . > > ERROR:Place:897 - The following IOBs have been locked (LOC constraint) > to the I/O bank 3. > =A0 =A0They require a voltage reference supply from the VREF pin(s) withi= n > the same I/O bank to be available. > =A0 =A0The following VREF pins are currently locked and can't be used to > supply the necessary reference > =A0 =A0IO Standard: Name =3D SSTL2_II, VREF =3D 1.25, VCCO =3D NR, TERM = =3D NONE > =A0 =A0List of locked IOB's: > =A0 =A0 =A0 =A0 DATA_OUT<3> > =A0 =A0List of occupied VREF Sites: > =A0 =A0VREF site PAD289 is occupied by comp DATA_OUT<3> > > Is there something fishy about this A23 pin of J37 bank of the board? > If I use LVTTL IO standard, it works fine, but I can't read 1.2 volts > in that standard. Why is the behavior of this particular pin > dirrefent from all it's adjacent pins? Is there any other IO standard > which can help reading 1.2 Volt as logic high? I have confirmed that > it doesn't work for IO standard=3D SSTL2_I too. > If there is any document to explain this strange behavior, please > point me to that. > > Waiting for some helpful answers. > Thanks and regards, > Pratap > I am using Virtex II Pro (XC2VP30, package ff896) board You need to explicitly state which board that you are using as there are many boards, from many vendors. When you reference pins of a connector (A20 to A27 of J37) there is no context to allow the reader to understand how this relates to the device. > used A23 and instead A31 pin of J37(L8 pin of FPGA). If only you had said what J37.A23 was connected to on the FPGA as well as the working J37.A31 pin... The L8 pin is in PAD183 (IO_L41N_2) in Bank 2. > List of occupied VREF Sites: > VREF site PAD289 is occupied by comp DATA_OUT<3> PAD289 in a XC2VP30-FF896 is pin AE1 (IO_L39N_3/VREF_3) in Bank 3. The pin that you have assigned that connected J37.A23 to the FPGA must be in Bank 3 and this is in conflict with the IOSTANDARD banking rules. SSTL (all flavors) is a single-ended referenced IO standard and it requires an external reference voltage of 1.25V to work. In the XC2VP30-FF896 Bank 3 these pins are U2, W1, AA1, AB2, AE1, AE3 and AH1 and the 1.25V reference voltage must be applied to all of these pins and they cannot be used for any other purpose. Your design is attempting to use one of these pins as an I/O and this is not allowed. You cannot fix this problem by reassigning the DATA_OUT<3> to another location without also modifying your board to provide the required 1.25V to the 7 VREF pins in Bank 3. Ed McGettigan -- Xilinx Inc.Article: 152519
On Aug 30, 5:34=A0am, valtih1978 <d...@not.email.me> wrote: > > yup, so the SDRAM will appear as an on chip block.... even though it > > locates few inches away... > > Nope. On chip, you know when data arrives with respect to clock. In theory you are able to know everything even before you can touch the hardware...Article: 152520
On Aug 30, 8:34=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Aug 30, 5:38=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > > > > > > > Hi, > > I am using Virtex II Pro (XC2VP30, package ff896) board to read 8 bit > > parallel data from FPGA. The output from the chip is of level 1.2V and > > hence I am using SSTL2_II IO standard for the inputs from the chip to > > the FPGA. I had designed my board to use the Pins A20 to A27 of the > > High speed IO bank J37 for reading the inputs from the chip. > > I have shared the ucf files for the not working and working case in > > the links below. > > > not working ucf:https://docs.google.com/leaf?id=3D0B68lizyh4WNKMGFiYmI4= OWQtNTQ3Ny00YzUw... > > > working ucf:https://docs.google.com/leaf?id=3D0B68lizyh4WNKYTA0YzFkYzct= NGY3Yi00MDFj... > > > In the working ucf file, the only change I have done is, I have not > > used A23 and instead A31 pin of J37(L8 pin of FPGA). I checked with > > the Virtex II Pro data sheet and don't see any problem using A23 pin > > of J37. In fact, even if I remove all other constraints and just use > > the A23 pin also, I get the same error: Below is the link to the .par > > file for this failed trial. > > >https://docs.google.com/leaf?id=3D0B68lizyh4WNKMzViNDhkOWQtYTE5OS00NGQ2.= .. > > > ERROR:Place:897 - The following IOBs have been locked (LOC constraint) > > to the I/O bank 3. > > =A0 =A0They require a voltage reference supply from the VREF pin(s) wit= hin > > the same I/O bank to be available. > > =A0 =A0The following VREF pins are currently locked and can't be used t= o > > supply the necessary reference > > =A0 =A0IO Standard: Name =3D SSTL2_II, VREF =3D 1.25, VCCO =3D NR, TERM= =3D NONE > > =A0 =A0List of locked IOB's: > > =A0 =A0 =A0 =A0 DATA_OUT<3> > > =A0 =A0List of occupied VREF Sites: > > =A0 =A0VREF site PAD289 is occupied by comp DATA_OUT<3> > > > Is there something fishy about this A23 pin of J37 bank of the board? > > If I use LVTTL IO standard, it works fine, but I can't read 1.2 volts > > in that standard. Why is the behavior of this particular pin > > dirrefent from all it's adjacent pins? Is there any other IO standard > > which can help reading 1.2 Volt as logic high? I have confirmed that > > it doesn't work for IO standard=3D SSTL2_I too. > > If there is any document to explain this strange behavior, please > > point me to that. > > > Waiting for some helpful answers. > > Thanks and regards, > > Pratap > > =A0I am using Virtex II Pro (XC2VP30, package ff896) board > > You need to explicitly state which board that you are using as there > are many boards, from many vendors. =A0When you reference pins of a > connector (A20 to A27 of J37) there is no context to allow the reader > to understand how this relates to the device. > > > used A23 and instead A31 pin of J37(L8 pin of FPGA). > > If only you had said what J37.A23 was connected to on the FPGA as well > as the working J37.A31 pin... > The L8 pin is in PAD183 (IO_L41N_2) in Bank 2. > > > =A0 =A0List of occupied VREF Sites: > > =A0 =A0VREF site PAD289 is occupied by comp DATA_OUT<3> > > PAD289 in a XC2VP30-FF896 is pin AE1 (IO_L39N_3/VREF_3) =A0in Bank 3. > The pin that you have assigned that connected J37.A23 to the FPGA must > be in Bank 3 and this is in conflict with the IOSTANDARD banking > rules. > > SSTL (all flavors) is a single-ended referenced IO standard and it > requires an external reference voltage of 1.25V to work. =A0In the > XC2VP30-FF896 Bank 3 these pins are U2, W1, AA1, AB2, AE1, AE3 and AH1 > and the 1.25V reference voltage must be applied to all of these pins > and they cannot be used for any other purpose. =A0Your design is > attempting to use one of these pins as an I/O and this is not allowed. > > You cannot fix this problem by reassigning the DATA_OUT<3> to another > location without also modifying your board to provide the required > 1.25V to the 7 VREF pins in Bank 3. > > Ed McGettigan > -- > Xilinx Inc. Hello McGettigan. Thanks for the response. To be specific, I am using the Xirtex II Pro board available from Digikey. Here is the snapshot. http://www.digilentinc.com/Data/Products/XUPV2P/XUPV2P-top.jpg I now understand the reason why assigning SSTL to J37.A23( AE1) flags error. But my doubt is, why if I use LVTTL for pin AE1 how does it work then? I would request for another clarification. If I properly understand the fix suggested, I need now to connect the pins below to an external 1.25V. But how to do this. Should this be done in UCF file or through a physical wire connected to the 1.25V supply on the FPGA board or an external DC supply? If it has to be done through an external wire, how can I connect a physical wire to the push button switch at AH1? Here is the mapping I found for the pin names corresponding to my board. U2: J5-38, W1: J6-12, AA1: J6-24, AB2: J4-47, AE1: J37-A23, AE3 : J37-A11, AH1: PB_LEFT The question may seem to be novice. But I seriously am not able to get the clue about these. Can you please suggest any document which I can follow for getting a real understanding about the IO standard and the Pin constraints? Waiting for some more valuable information as always, Thanks, PratapArticle: 152521
There is something wrong with quickswich devices. As I know MC68000 cant support 3.3V (some versions can but mine just cant). When i use quickswich any type i only get 5V to 3.3V translation and no vice versa. I need to use dual voltage level translator with auto sensing. Only parts that I can found with this is sn74lvc8t245 and new one like I write before txs0108e. For last two days I m reading about Pericom articles and those articles are just like IDT have for quickswich part. Devices are working from higher to lower and I m thinking that I just cant use those devices. For some devices who work with 5V can drive lower voltage levels that is ok but on my situation is not. For example PI5CX and PI3CX series are only related to 5V to 3.3V translation no bidirectional and then i need to use bus enable input like on most devices. From A to B bus or from B to A bus, that is not practical. Also some Pericom devices PI74LVC4245 who have two voltage on each bus side but no auto sensing again I need to set direction sides. I just dont know, as much i m reading only thing is txs0108e that I m using on design right now. Also using Pericom or IDT devices we can use pull up resistor connected to higher power source. I just dont know.... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152522
On Aug 30, 1:00=A0pm, Pratap <pratap.i...@gmail.com> wrote: > On Aug 30, 8:34=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Aug 30, 5:38=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > Hi, > > > I am using Virtex II Pro (XC2VP30, package ff896) board to read 8 bit > > > parallel data from FPGA. The output from the chip is of level 1.2V an= d > > > hence I am using SSTL2_II IO standard for the inputs from the chip to > > > the FPGA. I had designed my board to use the Pins A20 to A27 of the > > > High speed IO bank J37 for reading the inputs from the chip. > > > I have shared the ucf files for the not working and working case in > > > the links below. > > > > not working ucf:https://docs.google.com/leaf?id=3D0B68lizyh4WNKMGFiYm= I4OWQtNTQ3Ny00YzUw... > > > > working ucf:https://docs.google.com/leaf?id=3D0B68lizyh4WNKYTA0YzFkYz= ctNGY3Yi00MDFj... > > > > In the working ucf file, the only change I have done is, I have not > > > used A23 and instead A31 pin of J37(L8 pin of FPGA). I checked with > > > the Virtex II Pro data sheet and don't see any problem using A23 pin > > > of J37. In fact, even if I remove all other constraints and just use > > > the A23 pin also, I get the same error: Below is the link to the .par > > > file for this failed trial. > > > >https://docs.google.com/leaf?id=3D0B68lizyh4WNKMzViNDhkOWQtYTE5OS00NGQ= 2... > > > > ERROR:Place:897 - The following IOBs have been locked (LOC constraint= ) > > > to the I/O bank 3. > > > =A0 =A0They require a voltage reference supply from the VREF pin(s) w= ithin > > > the same I/O bank to be available. > > > =A0 =A0The following VREF pins are currently locked and can't be used= to > > > supply the necessary reference > > > =A0 =A0IO Standard: Name =3D SSTL2_II, VREF =3D 1.25, VCCO =3D NR, TE= RM =3D NONE > > > =A0 =A0List of locked IOB's: > > > =A0 =A0 =A0 =A0 DATA_OUT<3> > > > =A0 =A0List of occupied VREF Sites: > > > =A0 =A0VREF site PAD289 is occupied by comp DATA_OUT<3> > > > > Is there something fishy about this A23 pin of J37 bank of the board? > > > If I use LVTTL IO standard, it works fine, but I can't read 1.2 volts > > > in that standard. Why is the behavior of this particular pin > > > dirrefent from all it's adjacent pins? Is there any other IO standard > > > which can help reading 1.2 Volt as logic high? I have confirmed that > > > it doesn't work for IO standard=3D SSTL2_I too. > > > If there is any document to explain this strange behavior, please > > > point me to that. > > > > Waiting for some helpful answers. > > > Thanks and regards, > > > Pratap > > > =A0I am using Virtex II Pro (XC2VP30, package ff896) board > > > You need to explicitly state which board that you are using as there > > are many boards, from many vendors. =A0When you reference pins of a > > connector (A20 to A27 of J37) there is no context to allow the reader > > to understand how this relates to the device. > > > > used A23 and instead A31 pin of J37(L8 pin of FPGA). > > > If only you had said what J37.A23 was connected to on the FPGA as well > > as the working J37.A31 pin... > > The L8 pin is in PAD183 (IO_L41N_2) in Bank 2. > > > > =A0 =A0List of occupied VREF Sites: > > > =A0 =A0VREF site PAD289 is occupied by comp DATA_OUT<3> > > > PAD289 in a XC2VP30-FF896 is pin AE1 (IO_L39N_3/VREF_3) =A0in Bank 3. > > The pin that you have assigned that connected J37.A23 to the FPGA must > > be in Bank 3 and this is in conflict with the IOSTANDARD banking > > rules. > > > SSTL (all flavors) is a single-ended referenced IO standard and it > > requires an external reference voltage of 1.25V to work. =A0In the > > XC2VP30-FF896 Bank 3 these pins are U2, W1, AA1, AB2, AE1, AE3 and AH1 > > and the 1.25V reference voltage must be applied to all of these pins > > and they cannot be used for any other purpose. =A0Your design is > > attempting to use one of these pins as an I/O and this is not allowed. > > > You cannot fix this problem by reassigning the DATA_OUT<3> to another > > location without also modifying your board to provide the required > > 1.25V to the 7 VREF pins in Bank 3. > > > Ed McGettigan > > -- > > Xilinx Inc. > > Hello McGettigan. > Thanks for the response. > To be specific, I am using the Xirtex II Pro board available from > Digikey. > Here is the snapshot. > > http://www.digilentinc.com/Data/Products/XUPV2P/XUPV2P-top.jpg > > I now understand the reason why assigning SSTL to J37.A23( AE1) flags > error. But my doubt is, why if I use LVTTL for pin AE1 how does it > work then? I would request for another clarification. If I properly > understand the fix suggested, I need now to connect the pins below to > an external 1.25V. But how to do this. Should this be done in UCF file > or through a physical wire connected to the 1.25V supply on the FPGA > board or an external DC supply? If it has to be done through an > external wire, how can I connect a physical wire to the push button > switch at AH1? > Here is the mapping I found for the pin names corresponding to my > board. > U2: J5-38, > W1: J6-12, > AA1: J6-24, > AB2: J4-47, > AE1: J37-A23, > AE3 : J37-A11, > AH1: PB_LEFT > > The question may seem to be novice. But I seriously am not able to get > the clue about these. Can you please suggest any document which I can > follow for getting a real understanding about the IO standard and the > Pin constraints? > > Waiting for some more valuable information as always, > Thanks, > Pratap- Hide quoted text - > > - Show quoted text - > But my doubt is This is off topic, but I've never understood why so many non-native english writers use the word "doubt" when the correct word is "question". Did this originate from a single original [language]-to- English translation dictionary and then was propogate to every other [language]-to-English translation dictionary? >why if I use LVTTL for pin AE1 how does it work then? LVTTL is not a single-ended voltage reference IO standard and does not require an external VREF. The LVTTL standard relies on the switching levels of the transistors that make up the input buffer. This circuit has a much wider range for detecting a valid logic low (0.8V) or valid logic high (2.0V) and thus does not offer the same level of precision and speed that is possible with the other type (VREF +/- 0.15V). > I need now to connect the pins below to an external > 1.25V. But how to do this? This must be done physically on the board with a soldering iron, wires, voltage source, and capacitors for noise decoupling. If this board was intended to support these types of IO standards then it would have been designed this way. Since the board was not designed this way any use of this IO standard will not be very reliable even with the rework to the board. The IO standard will likely required external termination resistors to a VTT supply that will also need to be added further complicating the rework needed (this may have been added to the module that was designed). >Can you please suggest any document which I can > follow for getting a real understanding about the IO > standard and the Pin constraints? Every FPGA family includes documentation on the supported IO standards for that family. For the Virtex-II Pro device that you are using this information is included in the Virtex-II Pro data sheet DS083 in the Input/Output Block section. The current generation of FPGA families has this information in a separate user guide, for instance Virtex-6 SelectIO User Guide, UG361. Ed McGettigan -- Xilinx Inc.Article: 152523
Your theory proves everything true. It is known as 'determinism'. In reality, FPGA tools ensure the data not too late. Because they know the length of both clock and data. You tell the length of board clock trace to SDRAM by the feedback. But, there is no information about DQ/addr delays. Therefore, the on-chip-like timing analysis is impossible. The external clock feedback makes no sense at all.Article: 152524
I know that secondary DCM must be used to get the 90 deg time shift. You specify the clock routing very clearly. But, I do not see any info about _data line_ delays. Saying about clock makes no sense if you data line has indefinite length. Must they exactly match with clock or calibration is desired anyway and the only advantage of external FB is voltage-temperature compensation?
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