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Messages from 15450

Article: 15450
Subject: Re: big/little endian mishap
From: jmorken <foster@uvic.ca>
Date: Wed, 24 Mar 1999 09:31:17 -0800
Links: << >>  << T >>  << A >>
Here is the code that is acting up.  In the simulator when I try to
assign "reg_x <= in_port"  (x = a,b,c, or d) the value on the inport is
inverted.  Thanks for your time.

Jamie Morken

-- Register File Module

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu_pkg.ALL;

ENTITY reg_file IS
 PORT (
  reset_in   : IN std_logic;
  oe      : IN std_logic_vector(1 DOWNTO 0);
  read_write  : IN  std_logic;
  clear_reg   : IN  std_logic;
  sel_a_reg   : IN std_logic_vector(reg_ctl_width DOWNTO 0);
  sel_b_reg   : IN std_logic_vector(reg_ctl_width DOWNTO 0);
  write_sel_reg : IN std_logic_vector(reg_ctl_width DOWNTO 0);
  c_bus_in   : IN std_logic_vector(bus_width DOWNTO 0);

  a_bus_out   : OUT std_logic_vector(bus_width DOWNTO 0);
  b_bus_out   : OUT std_logic_vector(bus_width DOWNTO 0);

  -- Input and Output Port Signals
  in_port      : IN   std_logic_vector(bus_width DOWNTO 0);
  out_port      : OUT   std_logic_vector(bus_width DOWNTO 0);
  io_rw     : IN  std_logic

      );
 END;

ARCHITECTURE rtl OF reg_file IS

SIGNAL reg_a    : std_logic_vector(bus_width DOWNTO 0);
SIGNAL reg_b    : std_logic_vector(bus_width DOWNTO 0);
SIGNAL reg_c    : std_logic_vector(bus_width DOWNTO 0);
SIGNAL reg_d    : std_logic_vector(bus_width DOWNTO 0);

BEGIN

 -- Read from register and write value onto out_port when enabled ie)
io_rw = '1'
 out_port <=   reg_a WHEN  (sel_a_reg = "00")
   ELSE reg_b WHEN  (sel_a_reg = "01")
   ELSE reg_c WHEN  (sel_a_reg = "10")
   ELSE reg_d WHEN  (sel_a_reg = "11")
   ELSE (OTHERS => 'Z');

 -- Assign output to a_bus_out
 a_bus_out <= (OTHERS => 'Z') WHEN (oe(0) = '1')
   ELSE reg_a WHEN  (oe(0)='0') AND (read_write = '1') AND (sel_a_reg =
"00")
   ELSE reg_b WHEN  (oe(0)='0') AND (read_write = '1') AND (sel_a_reg =
"01")
   ELSE reg_c WHEN  (oe(0)='0') AND (read_write = '1') AND (sel_a_reg =
"10")
   ELSE reg_d WHEN  (oe(0)='0') AND (read_write = '1') AND (sel_a_reg =
"11")
   ELSE (OTHERS => 'Z');

 -- Assign output to b_bus_out
 b_bus_out <= (OTHERS => 'Z') WHEN (oe(1) = '1')
   ELSE reg_a WHEN  (oe(1)='0') AND (read_write = '1') AND  (sel_b_reg =
"00")
   ELSE reg_b WHEN  (oe(1)='0') AND (read_write = '1') AND  (sel_b_reg =
"01")
   ELSE reg_c WHEN  (oe(1)='0') AND (read_write = '1') AND  (sel_b_reg =
"10")
   ELSE reg_d WHEN  (oe(1)='0') AND (read_write = '1') AND  (sel_b_reg =
"11")
   ELSE (OTHERS => 'Z');

 -- Assign reg_a
 reg_a <= (OTHERS => '0') WHEN (reset_in = '0')
     ELSE (OTHERS => '0') WHEN (write_sel_reg="00" AND clear_reg='0')
     ELSE in_port     WHEN (write_sel_reg="00" AND io_rw = '0' AND
read_write ='1')
     ELSE c_bus_in     WHEN (write_sel_reg="00" AND io_rw = '1' AND
read_write ='0')
     ELSE reg_a;

 -- Assign reg_b
 reg_b <= (OTHERS => '0') WHEN (reset_in = '0')
     ELSE (OTHERS => '0') WHEN (write_sel_reg="01" AND clear_reg='0')
     ELSE in_port     WHEN (write_sel_reg="01" AND io_rw = '0' AND
read_write /='0')
     ELSE c_bus_in     WHEN (write_sel_reg="01" AND io_rw /= '0' AND
read_write ='0')
     ELSE reg_b;

 -- Assign reg_c
 reg_c <= (OTHERS => '0') WHEN (reset_in = '0')
     ELSE (OTHERS => '0') WHEN (write_sel_reg="10" AND clear_reg='0')
     ELSE in_port     WHEN (write_sel_reg="10" AND io_rw = '0' AND
read_write /='0')
     ELSE c_bus_in     WHEN (write_sel_reg="10" AND io_rw /= '0' AND
read_write ='0')
     ELSE reg_c;

 -- Assign reg_d
 reg_d <= (OTHERS => '0') WHEN (reset_in = '0')
     ELSE (OTHERS => '0') WHEN (write_sel_reg="11" AND clear_reg='0')
     ELSE in_port     WHEN (write_sel_reg="11" AND io_rw = '0' AND
read_write /='0')
     ELSE c_bus_in     WHEN (write_sel_reg="11" AND io_rw /= '0' AND
read_write ='0')
     ELSE reg_d;

END rtl;



Article: 15451
Subject: Re: DIY Xilinx Download Cable
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Wed, 24 Mar 1999 17:34:55 +0000
Links: << >>  << T >>  << A >>
Leon Heller wrote:
> 
> Having just attended a Xilinx symposium, and now being
> the proud owner of the Software Sampler CD-ROM, which
> includes development tools for some of the Spartan range,
> I need a download cable. On the Xilinx web site I found a
> schematic of what appears to be a suitable cable:
> 
>     www.xilinx.com/support/programr/jtag_cable.pdf
> 
> Can anyone confirm that this is the correct cable for these
> devices?

That circuit diagram is of the "pod" of the Xilinx DLC5 parallel port
download cable.  You can clone it and it will work.  But in many
situations you can get away with a *MUCH* simpler download interface: 
XESS Corp <http://www.xess.com/FPGA/ho02000.html> simply connects TDI
(DIN) and TMS (/PROG) direct to the parallel port pins, with TCK (CCLK)
driven via an LS14 Schmitt and TDO (D/P) driving via another LS14
Schmitt.  Downloading is then using XESS s/w "xsload" rather than Xilinx
s/w.

For a recent design using XC9572 CPLDs I cloned the Xilinx DLC5 but used
a single HCT367 rather than two HC125s.  Works fine with Xilinx s/w.

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
The University of Southampton, UK

The University is not responsible for my opinions
Article: 15452
Subject: Re: big/little endian mishap
From: mench@mench.com
Date: 24 Mar 1999 12:45:05 -0500
Links: << >>  << T >>  << A >>
jmorken <foster@uvic.ca> wrote:
> Here is the code that is acting up.  In the simulator when I try to
> assign "reg_x <= in_port" (x = a,b,c, or d) the value on the inport
> is inverted.  Thanks for your time.

I see nothing wrong with your code.  Dare I suggest a bug in your
simulator?

BTW, just to confirm, by inverted, you don't mean that

	reg_x <= in_port;

gives you

	reg_x <= not in_port;

but gives you instead

	reg_x <= reverse( in_port );

where reverse exchanges the msb for the lsb, and so on.  That is,

if in_port = "1111000101010" you get "0101010001111", not "0000111010101".

What software are you using?

Regards,

Paul

-- 
Paul Menchini          | mench@mench.com | "Non si vive se non il
OrCAD                  | www.orcad.com   |  tempo che si ama."
P.O. Box 71767         | 919-479-1670[v] |  --Claude Adrien Helvetius
Durham, NC  27722-1767 | 919-479-1671[f] |
Article: 15453
Subject: Re: HDL-307 error
From: Bob Sefton <rsefton@home.com>
Date: Wed, 24 Mar 1999 17:58:25 GMT
Links: << >>  << T >>  << A >>
It's very possible the architecture you're targeting doesn't
support async reset and async load in the same register. In that
case the compiler has to use more resources to implement your
logic.

Try synchronizing your load signal and re-code your incrementer
with synchronous load.

Bob

Jamie Morken wrote:
> 
> Ya, that looks familiar all right :)  What is the best way you found to fix
> this $%^&% error?  I have tried 20 different ways to load increment and
> reset a single register with no luck yet.   Thanks for your time.
> Jamie Morken
Article: 15454
Subject: Re: big/little endian mishap
From: jmorken <foster@uvic.ca>
Date: Wed, 24 Mar 1999 10:41:47 -0800
Links: << >>  << T >>  << A >>
Hi,

If in_port = "1111000" I get "0001111" stored in the selected internal
register,
and if c_bus_in = "1101000" I get "0001011" stored in the selected internal
register.  There is no reversing from the internal registers to the output
busses.  I am using Xilinx 1.5i functional simulation and I create a macro for
that VHDL code.  Here is code that will compile without a package of constants
I made, if anyone wants to verify what is going on here.  Thanks for your
time.

Jamie Morkn

Article: 15455
Subject: Re: big/little endian mishap
From: jmorken <foster@uvic.ca>
Date: Wed, 24 Mar 1999 10:43:03 -0800
Links: << >>  << T >>  << A >>
woops.. here is the code :)

-- Register File Module

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY reg_file IS
 PORT (
  reset_in   : IN std_logic;
    oe      : IN std_logic_vector(1 DOWNTO 0);
  read_write  : IN  std_logic;
  clear_reg   : IN  std_logic;
  sel_a_reg   : IN std_logic_vector(1 DOWNTO 0);
  sel_b_reg   : IN std_logic_vector(1 DOWNTO 0);
  write_sel_reg : IN std_logic_vector(1 DOWNTO 0);
  c_bus_in   : IN std_logic_vector(7 DOWNTO 0);

  a_bus_out   : OUT std_logic_vector(7 DOWNTO 0);
  b_bus_out   : OUT std_logic_vector(7 DOWNTO 0);

  -- Input and Output Port Signals
  in_port      : IN   std_logic_vector(7 DOWNTO 0);
  out_port      : OUT   std_logic_vector(7 DOWNTO 0);
  io_rw     : IN  std_logic

      );
 END;

ARCHITECTURE rtl OF reg_file IS

SIGNAL reg_a    : std_logic_vector(7 DOWNTO 0);
SIGNAL reg_b    : std_logic_vector(7 DOWNTO 0);
SIGNAL reg_c    : std_logic_vector(7 DOWNTO 0);
SIGNAL reg_d    : std_logic_vector(7 DOWNTO 0);

BEGIN

 -- Read from register and write value onto out_port when enabled ie) io_rw = '1'
 out_port <=   reg_a WHEN  (sel_a_reg = "00")
   ELSE reg_b WHEN  (sel_a_reg = "01")
   ELSE reg_c WHEN  (sel_a_reg = "10")
   ELSE reg_d WHEN  (sel_a_reg = "11")
   ELSE (OTHERS => 'Z');

 -- Assign output to a_bus_out
 a_bus_out <= (OTHERS => 'Z') WHEN (oe(0) = '1')
   ELSE reg_a WHEN  (oe(0)='0') AND (read_write = '1') AND (sel_a_reg = "00")
   ELSE reg_b WHEN  (oe(0)='0') AND (read_write = '1') AND (sel_a_reg = "01")
   ELSE reg_c WHEN  (oe(0)='0') AND (read_write = '1') AND (sel_a_reg = "10")
   ELSE reg_d WHEN  (oe(0)='0') AND (read_write = '1') AND (sel_a_reg = "11")
   ELSE (OTHERS => 'Z');

 -- Assign output to b_bus_out
 b_bus_out <= (OTHERS => 'Z') WHEN (oe(1) = '1')
   ELSE reg_a WHEN  (oe(1)='0') AND (read_write = '1') AND  (sel_b_reg = "00")
   ELSE reg_b WHEN  (oe(1)='0') AND (read_write = '1') AND  (sel_b_reg = "01")
   ELSE reg_c WHEN  (oe(1)='0') AND (read_write = '1') AND  (sel_b_reg = "10")
   ELSE reg_d WHEN  (oe(1)='0') AND (read_write = '1') AND  (sel_b_reg = "11")
   ELSE (OTHERS => 'Z');

 -- Assign reg_a
 reg_a <= (OTHERS => '0') WHEN (reset_in = '0')
     ELSE (OTHERS => '0') WHEN (write_sel_reg="00" AND clear_reg='0')
     ELSE in_port     WHEN (write_sel_reg="00" AND io_rw = '0' AND read_write
='1')
     ELSE c_bus_in     WHEN (write_sel_reg="00" AND io_rw = '1' AND read_write
='0')
     ELSE reg_a;

 -- Assign reg_b
 reg_b <= (OTHERS => '0') WHEN (reset_in = '0')
     ELSE (OTHERS => '0') WHEN (write_sel_reg="01" AND clear_reg='0')
     ELSE in_port     WHEN (write_sel_reg="01" AND io_rw = '0' AND read_write
/='0')
     ELSE c_bus_in     WHEN (write_sel_reg="01" AND io_rw /= '0' AND read_write
='0')
     ELSE reg_b;

 -- Assign reg_c
 reg_c <= (OTHERS => '0') WHEN (reset_in = '0')
     ELSE (OTHERS => '0') WHEN (write_sel_reg="10" AND clear_reg='0')
     ELSE in_port     WHEN (write_sel_reg="10" AND io_rw = '0' AND read_write
/='0')
     ELSE c_bus_in     WHEN (write_sel_reg="10" AND io_rw /= '0' AND read_write
='0')
     ELSE reg_c;

 -- Assign reg_d
 reg_d <= (OTHERS => '0') WHEN (reset_in = '0')
     ELSE (OTHERS => '0') WHEN (write_sel_reg="11" AND clear_reg='0')
     ELSE in_port     WHEN (write_sel_reg="11" AND io_rw = '0' AND read_write
/='0')
     ELSE c_bus_in     WHEN (write_sel_reg="11" AND io_rw /= '0' AND read_write
='0')
     ELSE reg_d;

END rtl;

Article: 15456
Subject: Re: Info about FPGA/PLD
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 24 Mar 1999 11:10:35 -0800
Links: << >>  << T >>  << A >>
FFabio wrote:

> Hi,
>
> I'm a joung electronic engineer (MT), my work is on
> power electronics, but for teoretical study the
> control can be feed on FPGA or PLD device.
>
> Could you please send me some information about this?
> What is the adavantage of one type of device instead of
> the
> other one?
>  

CPLDs are derived from PALs and thus have an AND-OR
structure which makes them easy to understand. They have few
flip-flops, but can decode wide inputs. This makes them
popular for control and decode structures and state
machines.CPLDs are fast pin-to-pin, but consume far more
power than FPGAs.

FPGAs have a more versatile structure with lots and lots of
flip-flops. Static power consumption is zero, it's all
dynamic and thus proportional to clock rate. The design
methodology is not as intuitively obvious as for CPLDs, but
there is now pretty good software that isolates you from the
implementation details.

Both types of devices are very fast, with max clock rates
above 100 MHz.
As far as price goes, there is a large overlap. The cheapest
FPGAs are far cheaper than the most expensive CPLDs, but at
the low end, below 5 dollars, there are more CPLDs than
FPGAs.

Good software starts at less than 100 dollars.
The distinction between "free" and 99 dollars is irrelevant
to the professional user, quality and learning curve are far
more important.

Peter Alfke, Xilinx Applications
  
 

Article: 15457
Subject: Re: DIY Xilinx Download Cable
From: bibico <pobox303@usa.net>
Date: Wed, 24 Mar 1999 22:20:04 +0100
Links: << >>  << T >>  << A >>
Yes, you can also build a 100% passive download cable.
Match the cable impedance with a series resistor at the parallel port side
for outgoing signals (TCK;TMS;TDI).
and for incomming signals ( TDO and VCC detect) connect a series resistor at
the CPLD end.
Use flat band cable and be sure to route one ground signal between all
signals.
Do the bridges between D6 and ... as in the DLC5 cable.
This will fake a parallel port download cable.
At least for one single device JTAG chain this works perfectly.

Tim Forcer wrote:

> Leon Heller wrote:
> >
> > Having just attended a Xilinx symposium, and now being
> > the proud owner of the Software Sampler CD-ROM, which
> > includes development tools for some of the Spartan range,
> > I need a download cable. On the Xilinx web site I found a
> > schematic of what appears to be a suitable cable:
> >
> >     www.xilinx.com/support/programr/jtag_cable.pdf
> >
> > Can anyone confirm that this is the correct cable for these
> > devices?
>
> That circuit diagram is of the "pod" of the Xilinx DLC5 parallel port
> download cable.  You can clone it and it will work.  But in many
> situations you can get away with a *MUCH* simpler download interface:
> XESS Corp <http://www.xess.com/FPGA/ho02000.html> simply connects TDI
> (DIN) and TMS (/PROG) direct to the parallel port pins, with TCK (CCLK)
> driven via an LS14 Schmitt and TDO (D/P) driving via another LS14
> Schmitt.  Downloading is then using XESS s/w "xsload" rather than Xilinx
> s/w.
>
> For a recent design using XC9572 CPLDs I cloned the Xilinx DLC5 but used
> a single HCT367 rather than two HC125s.  Works fine with Xilinx s/w.
>
> --
> Tim Forcer               tmf@ecs.soton.ac.uk
> The University of Southampton, UK
>
> The University is not responsible for my opinions



Article: 15458
Subject: Re: DIY Xilinx Download Cable
From: bibico <pobox303@usa.net>
Date: Wed, 24 Mar 1999 22:22:40 +0100
Links: << >>  << T >>  << A >>
PS: BE CAREFUL THIS APPLIES ONLY FOR 5 VOLTS CPLD DEVICES.

bibico wrote:

> Yes, you can also build a 100% passive download cable.
> Match the cable impedance with a series resistor at the parallel port side
> for outgoing signals (TCK;TMS;TDI).
> and for incomming signals ( TDO and VCC detect) connect a series resistor at
> the CPLD end.
> Use flat band cable and be sure to route one ground signal between all
> signals.
> Do the bridges between D6 and ... as in the DLC5 cable.
> This will fake a parallel port download cable.
> At least for one single device JTAG chain this works perfectly.
>
> Tim Forcer wrote:
>
> > Leon Heller wrote:
> > >
> > > Having just attended a Xilinx symposium, and now being
> > > the proud owner of the Software Sampler CD-ROM, which
> > > includes development tools for some of the Spartan range,
> > > I need a download cable. On the Xilinx web site I found a
> > > schematic of what appears to be a suitable cable:
> > >
> > >     www.xilinx.com/support/programr/jtag_cable.pdf
> > >
> > > Can anyone confirm that this is the correct cable for these
> > > devices?
> >
> > That circuit diagram is of the "pod" of the Xilinx DLC5 parallel port
> > download cable.  You can clone it and it will work.  But in many
> > situations you can get away with a *MUCH* simpler download interface:
> > XESS Corp <http://www.xess.com/FPGA/ho02000.html> simply connects TDI
> > (DIN) and TMS (/PROG) direct to the parallel port pins, with TCK (CCLK)
> > driven via an LS14 Schmitt and TDO (D/P) driving via another LS14
> > Schmitt.  Downloading is then using XESS s/w "xsload" rather than Xilinx
> > s/w.
> >
> > For a recent design using XC9572 CPLDs I cloned the Xilinx DLC5 but used
> > a single HCT367 rather than two HC125s.  Works fine with Xilinx s/w.
> >
> > --
> > Tim Forcer               tmf@ecs.soton.ac.uk
> > The University of Southampton, UK
> >
> > The University is not responsible for my opinions



Article: 15459
Subject: Re: Info about FPGA/PLD
From: Ray Andraka <randraka@ids.net>
Date: Wed, 24 Mar 1999 19:16:54 -0500
Links: << >>  << T >>  << A >>


Peter Alfke wrote:

> FPGAs have a more versatile structure with lots and lots of
> flip-flops. Static power consumption is zero, it's all
> dynamic and thus proportional to clock rate.

Really?!! Where can I get some of these FPGAs with zero static
dissipation.  Last I checked, seems that the majority of devices had
static currents of 5-10mA

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15460
Subject: Re: Booth or Wallace Trees Multipliers
From: Ray Andraka <randraka@ids.net>
Date: Wed, 24 Mar 1999 19:29:48 -0500
Links: << >>  << T >>  << A >>
A wallace tree is not appropriate for FPGAs with fast carry chains.  You only
get a speed up with a wallace tree if the final adder is faster than the
adders you would use in a row.  Routing in the FPGA kills any marginal gains
you might have gotten.  Booth multipliers do OK, although you might look at a
partial product and adder tree architecture.  Take a look at my website for a
page on multiplication in FPGAs.

Dennis Garcia wrote:

> Hi
>
> I working on a design where I'm implementing some DSP function i.e.
> multipliers
> I would like to get information on how to design  mutilpliers  using
> Booth or Wallace Trees algorithms for implementation in Xilinx or Actel
> fpga.
> any reference on  schematic or VHDL are appreciated.
>
> thanks
> Dennis
>
>   ------------------------------------------------------------------------
>
>   Dennis Garcia <d_garcia@routes.com>
>   Electronics Technologist
>   Routes Inc.
>
>   Dennis Garcia
>   Electronics Technologist  <d_garcia@routes.com>
>   Routes Inc.
>   303 Legget Dr.            Work: (613) 592-0748
>   Kanata                    Fax: (613) 592-6553
>   Ontario                   Netscape Conference Address
>   K2K 2B1                   Netscape Conference DLS Server
>   Canada
>   Additional Information:
>   Last Name     Garcia
>   First Name    Dennis
>   Version       2.1



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15461
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: Tim Davis <timdavis@tdcon.com>
Date: Wed, 24 Mar 1999 17:32:14 -0700
Links: << >>  << T >>  << A >>
Richard,

Probably the reason why companies don't give things away for free is that they want to make a
reasonable (or possibly excessive) profit. I was at a VHDL conference, sitting in on a panel
session,  when a boisterous Intel engineer came up to the microphone and demanded to know why tools
cost so much and why vendors didn't just give them away or at least drastically lower the price to
something "reasonable". After he was through I went up to the microphone and asked him when he could
email me the microcode, layouts, tools, etc for their latest processor. Everybody laughed. I hope he
got the point. Intel makes a profit on what they sell so it is only reasonable that the companies
that help them succede should make a profit too.

If you intend to goof around in your garage then I can understand why free tools would be a big deal
to you. Hard to justify to the wife purchasing umpteen thousands of dollars worth of "play" tools.
IMHO if you plan to be in business and sell your services then you should be damn grateful that
somebody out there is willing to write and support the tools you need to stay in business. (If you
are currently in business selling design contracting services then I could actually use some of your
"free" help.)

If you really still want free tools then I suggest doing one of two things:

1. Many universities have "free" tools available. They aren't as nice and polished as some of the
commericial tools but they exist.
2. Convince your Xilinx rep that you can sell 100,000 of their parts in some design you are bidding
on. Tell them that the deal will go through but only if you get "free" tools. They will probably
give them to you and might even knock off some maintenance.
3. Simply write your own "free" tools and give them away. Much like Linus Torvald did with Linux.
That would be very useful to all of us.

Richard Guerin wrote:

> Would anyone care comment on why Xilinx doesn't offer some type of free
> PC based vendor tools  ? ... it seems like every other FPGA/CPLD vendor
> does :-)

--

Tim Davis
Timothy Davis Consulting

TimDavis@TDCon.com - +1 (303) 426-0800 - Fax +1 (303) 426-1023


Article: 15462
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: Tim Davis <timdavis@tdcon.com>
Date: Wed, 24 Mar 1999 17:37:17 -0700
Links: << >>  << T >>  << A >>
Richard,

Probably the reason why companies don't give things away for free is that they want to make a
reasonable (or possibly excessive) profit. I was at a VHDL conference, sitting in on a panel
session,  when a boisterous Intel engineer came up to the microphone and demanded to know why tools
cost so much and why vendors didn't just give them away or at least drastically lower the price to
something "reasonable". After he was through I went up to the microphone and asked him when he could
email me the microcode, layouts, tools, etc for their latest processor. Everybody laughed. I hope he
got the point. Intel makes a profit on what they sell so it is only reasonable that the companies
that help them succeed should make a profit too.

If you intend to goof around in your garage then I can understand why free tools would be a big deal
to you. Hard to justify to the wife purchasing umpteen thousands of dollars worth of "play" tools.
IMHO if you plan to be in business and sell your services then you should be damn grateful that
somebody out there is willing to write and support the tools you need to stay in business. (If you
are currently in business selling design contracting services then I could actually use some of your
"free" help.) I certainly don't like paying excessive prices for tools and sometimes the maintenance
seems steep for what you actually get but those tools help me to stay in business and make a
reasonable life for my family.

If you really still want free tools then I suggest doing one of two things:

1. Many universities have "free" tools available. They aren't as nice and polished as some of the
commercial tools but they exist.
2. Convince your Xilinx rep that you can sell 100,000 of their parts in some design you are bidding
on. Tell them that the deal will go through but only if you get "free" tools. They will probably
give them to you and might even knock off some maintenance.
3. Simply write your own "free" tools and give them away. Much like Linus Torvald did with Linux.
That would be very useful to all of us.

Richard Guerin wrote:

> Would anyone care comment on why Xilinx doesn't offer some type of free
> PC based vendor tools  ? ... it seems like every other FPGA/CPLD vendor
> does :-)

--

Tim Davis
Timothy Davis Consulting

TimDavis@TDCon.com - +1 (303) 426-0800 - Fax +1 (303) 426-1023


Article: 15463
Subject: FPGA Express Synthesis Problem
From: "Adam J. Elbirt" <aelbirt@nac.net>
Date: Wed, 24 Mar 1999 22:06:31 -0500
Links: << >>  << T >>  << A >>
Hi all - have a synthesis question for you.  I'm using FPGA Express
targetting a Xilinx Virtex chip.  My design has four large
look-up-tables, each having 256 addresses and outputs a 32-bit data
word.  I had figured this would be trivial to synthesize as a RAM
(really a PROM) and that I would either continuously load the constants
that the tables would output or use the GSR to reset/preset the
registers to the constants and than route the outputs to the inputs.  In
either case, FPGA Express takes forever to complete - I killed it after
waiting 48 hours using a K6-300 MHz system with 128 MB RAM and 1.2 GB
swap space.  However, if I change the table to be implemented as a
massive decoder comprised entirely of combinatorial logic, it finishes
inside of an hour.  Any ideas as to why the RAM/register implementation
causes the tool to choke?

Thanks.

Adam

Article: 15464
Subject: Re: Xilinx Version Control?
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Wed, 24 Mar 1999 19:27:37 -0800
Links: << >>  << T >>  << A >>
By version control, I think we mean that Xilinx feature that uses your old
version files when it build a new version.

I hit the synthesis button, hit New Version, and it doesn't re-analyse the
files. It just re-elaborates the old stuff.  What a piece of s**t!

Looks like 1.5i has a synthesis scripting capability.  I'll be trying that
real soon!

bruce


Rick wrote in message <36F7C4B8.8651112D@algor.co.uk>...
>Bruce Nepple wrote:
>>
>> Do you have a batchfile that will work with Foundation Express HDL flow?
>> Is there a sample batchfile in that mess somewhere that I've missed?
>>
>> bruce
>>
>> Peter <z80@ds2.com> wrote in article
>> <36f54871.333079883@news.netcomuk.co.uk>...
>> | I can't agree more, especially for projects which one needs to revisit
>> | years later.
>>
>
>Absolutely. The GUI usefulness just barely extends beyond the demo you
>got from the salesman. As soon as you try and do anything serious it
>becomes more and more of an obstruction.
>
>To the original poster: Even though it looks pretty intimidating its
>really worth puting in the effort to at least learn the basics of
>``make''. If you've got a PC version of emacs you could teach yourself a
>lot from the info section on g(nu)make.
>Or plead with a s/w engineer for a morning's basic instruction. [Why are
>tools such as make, RCS, CVS considered by the EDA vendors to be beyond
>the scope of h/w engineers ? I, personally, consider that insulting]
>
>Once you have got at least some of it understood it makes design
>integration very simple. In my case I use it not only to keep track of
>the synthesis but also to keep synth and simulation in synchronisation.
>
>BTW: What Xilinx verion control ? As far as I'm aware all it does is
>archive a routed design with absolutely no record of how  and from what
>the design was built.


Article: 15465
Subject: keeping an Altera EAB register in synplicity
From: Ray Andraka <randraka@ids.net>
Date: Thu, 25 Mar 1999 00:15:35 -0500
Links: << >>  << T >>  << A >>
I'm trying to use the registers in the altera EAB from synplicity.
Works fine, but one bit in my ROM happens to always be zero, so
synplicity is optimizing that out to a soft-buf.  I've tried to use the
SYN_PRESERVE attribute, but it doesn't want to keep the errant
register.  The result is the table is getting implemented in LEs
instead.  Has anyone else seen this?  Any ideas on how to make it stay?

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15466
Subject: Info about VHDL syntesis
From: "FFabio" <filippa@tekel.it>
Date: Thu, 25 Mar 1999 08:54:52 +0100
Links: << >>  << T >>  << A >>
Hi,

I need some information about VHDL language,
literature and free tool for develop simple start application
with Xilinx isp1016.

Thanks and regards,
Fabio


Article: 15467
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: Hamish Moffatt <hamish@rising.com.au>
Date: 25 Mar 1999 09:27:46 GMT
Links: << >>  << T >>  << A >>
Tim Davis <timdavis@tdcon.com> wrote:
> session,  when a boisterous Intel engineer came up to the microphone and demanded to know why tools
> cost so much and why vendors didn't just give them away or at least drastically lower the price to
> something "reasonable". After he was through I went up to the microphone and asked him when he could
> email me the microcode, layouts, tools, etc for their latest processor. Everybody laughed. I hope he

Hardly the same thing. Nobody is asking for the design details of 
the FPGA hardware. Plenty of companies give away Intel-targetted development
software though, which IS equivalent.

> If you intend to goof around in your garage then I can understand why free tools would be a big deal
> to you. Hard to justify to the wife purchasing umpteen thousands of dollars worth of "play" tools.

Indeed. Unfortunately, the current reply to people wanting tools for this
reason is: bad luck.

> 3. Simply write your own "free" tools and give them away. Much like Linus Torvald did with Linux.
> That would be very useful to all of us.

Sure. You can get the specs for a PC and the i386 easily, or hardware
vendors provide enough information to write drivers, or write it themselves.
But Xilinx don't publish their bitstream format, do they? So you can't
write your own complete software.


Hamish
-- 
Hamish Moffatt       Mobile: +61 412 011 176       hamish@rising.com.au

Rising Software Australia Pty. Ltd. 
Developers of music education software including Auralia & Musition.
31 Elmhurst Road, Blackburn, Victoria Australia, 3130
Phone: +61 3 9894 4788  Fax: +61 3 9894 3362  USA Toll Free: 1-888-667-7839
Internet: http://www.rising.com.au/
Article: 15468
Subject: Re: keeping an Altera EAB register in synplicity
From: Hans Christian =?iso-8859-1?Q?L=F8nstad?=
Date: Thu, 25 Mar 1999 11:51:52 +0100
Links: << >>  << T >>  << A >>
Ray Andraka wrote:

> I'm trying to use the registers in the altera EAB from synplicity.
> Works fine, but one bit in my ROM happens to always be zero, so
> synplicity is optimizing that out to a soft-buf.  I've tried to use the=

> SYN_PRESERVE attribute, but it doesn't want to keep the errant
> register.  The result is the table is getting implemented in LEs
> instead.  Has anyone else seen this?  Any ideas on how to make it stay?=

>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka

To my knowledge Synplify can't infer ROM into EABs (at least up to versio=
n
5.0.7). I've had to use a "black box" workaround calling a LPM macro in t=
he
Altera library. This has the unfortunate effect that you have to supply a=
n
additional simulation model for direct VHDL, VERILOG simulation.


--
Hans Christian L=F8nstad       Data Respons AS
                             Sandviksveien 26
Real Time                    1322 H=F8vik
Professionals                Norway

mailto:Hans.Christian.Lonstad@datarespons.no
http://www.datarespons.no


Article: 15469
Subject: Singapore Job Opportunity : ASIC Design Engineer
From: "Infraglobe Pte Ltd" <infrag@singnet.com.sg>
Date: Thu, 25 Mar 1999 19:27:34 +0800
Links: << >>  << T >>  << A >>
On behalf of our client, a large US MNC, we are interested in recruiting a
senior ASIC Design Engineer as follows :

Associate Principal Engineer

Candidates must have about 7 years relevant work experience
with at least 1 year as Project Leader.

Location : Singapore.

Exposure to Quarter-Micron Technology preferred.

The selected candidates will be involved in:

1. Architectural Definition & Device Specification for ASICs for Mass
Storage Applications.
2. Design & Development of ASICs
3. Prototype Validation
4. Liaison with other departments & vendors

Pls apply with a detailed CV (including current/expected salaries) to :

Mrigank Ojha
Vice President
Infraglobe Pte Ltd
16 Raffles Quay, #33-03
Hong Leong Building
Singapore 048581

Fax : (65) 323-0581
E-Mail : infrag@singnet.com.sg



Article: 15470
Subject: Re: FPGA Express Synthesis Problem
From: jerry english <jenglish@planetc.com>
Date: Thu, 25 Mar 1999 08:22:36 -0500
Links: << >>  << T >>  << A >>
Adam J. Elbirt wrote:

> Hi all - have a synthesis question for you.  I'm using FPGA Express
> targetting a Xilinx Virtex chip.  My design has four large
> look-up-tables, each having 256 addresses and outputs a 32-bit data
> word.  I had figured this would be trivial to synthesize as a RAM
> (really a PROM) and that I would either continuously load the constants
> that the tables would output or use the GSR to reset/preset the
> registers to the constants and than route the outputs to the inputs.  In
> either case, FPGA Express takes forever to complete - I killed it after
> waiting 48 hours using a K6-300 MHz system with 128 MB RAM and 1.2 GB
> swap space.  However, if I change the table to be implemented as a
> massive decoder comprised entirely of combinatorial logic, it finishes
> inside of an hour.  Any ideas as to why the RAM/register implementation
> causes the tool to choke?
>
> Thanks.
>
> Adam

  I have seen this type of behavior when I tried to synthesize ram in an
Xilinx XC4000
also using Synopsys. More than likely all synthisis tools will do this
"extended" computation.
I got around it by instantiation of ram modules from the Xilinx library.

Jerry



Article: 15471
Subject: Re: keeping an Altera EAB register in synplicity
From: Ray Andraka <randraka@ids.net>
Date: Thu, 25 Mar 1999 09:28:46 -0500
Links: << >>  << T >>  << A >>
Synplicity 5.08, which you can download from their site, correctly infers a ROM
into EAB if you use the ALTERA_IMPLEMENT_IN_EAB attribute on the block you want
to put in the EAB.  If that block includes registers at the output, the EAB
registers get invoked.  If any bit is registered, then all bits must be
registered, or it can't be implemented in an EAB.  The problem I am having is
that one of the bits in the ROM is 'stuck at zero' so the register gets
optimized off that bit.  Since one bit is now unregistered, the whole thing
gets thrown out of the EAB.  I've got another instance of the same component,
different data that implements just fine.

I'd rather avoid having to instantiate the EAB as a black box if I can.  It's
kind of a pain in the patoot at the system level.

Hans Christian Lønstad wrote:

> Ray Andraka wrote:
>
> > I'm trying to use the registers in the altera EAB from synplicity.
> > Works fine, but one bit in my ROM happens to always be zero, so
> > synplicity is optimizing that out to a soft-buf.  I've tried to use the
> > SYN_PRESERVE attribute, but it doesn't want to keep the errant
> > register.  The result is the table is getting implemented in LEs
> > instead.  Has anyone else seen this?  Any ideas on how to make it stay?
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email randraka@ids.net
> > http://users.ids.net/~randraka
>
> To my knowledge Synplify can't infer ROM into EABs (at least up to version
> 5.0.7). I've had to use a "black box" workaround calling a LPM macro in the
> Altera library. This has the unfortunate effect that you have to supply an
> additional simulation model for direct VHDL, VERILOG simulation.
>
> --
> Hans Christian Lønstad       Data Respons AS
>                              Sandviksveien 26
> Real Time                    1322 Høvik
> Professionals                Norway
>
> mailto:Hans.Christian.Lonstad@datarespons.no
> http://www.datarespons.no



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15472
Subject: Re: Info about VHDL syntesis
From: Ray Andraka <randraka@ids.net>
Date: Thu, 25 Mar 1999 09:43:56 -0500
Links: << >>  << T >>  << A >>
The isp1016 is a Lattice Semiconductor part, not Xilinx.  Go to the
lattice website www.latticesemi.com for more info on the device and the
tools.  Lattice used to give away a crippled version of Synario that
would handle the isp1016 fine.  I don't know what they are offering in
the way of free tools today.

FFabio wrote:

> Hi,
>
> I need some information about VHDL language,
> literature and free tool for develop simple start application
> with Xilinx isp1016.
>
> Thanks and regards,
> Fabio



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15473
Subject: Re: keeping an Altera EAB register in synplicity
From: Ray Andraka <randraka@ids.net>
Date: Thu, 25 Mar 1999 09:50:13 -0500
Links: << >>  << T >>  << A >>
Forgot to mention it.  HDL analyst shows the register in the RTL view, but it is
stripped out and replaced with a soft buffer in the technology view.  Without the
SYN_PRESERVE attribute, the register is optimized out in the RTL view too.

Ray Andraka wrote:

> Synplicity 5.08, which you can download from their site, correctly infers a ROM
> into EAB if you use the ALTERA_IMPLEMENT_IN_EAB attribute on the block you want
> to put in the EAB.  If that block includes registers at the output, the EAB
> registers get invoked.  If any bit is registered, then all bits must be
> registered, or it can't be implemented in an EAB.  The problem I am having is
> that one of the bits in the ROM is 'stuck at zero' so the register gets
> optimized off that bit.  Since one bit is now unregistered, the whole thing
> gets thrown out of the EAB.  I've got another instance of the same component,
> different data that implements just fine.
>
> I'd rather avoid having to instantiate the EAB as a black box if I can.  It's
> kind of a pain in the patoot at the system level.
>
> Hans Christian Lønstad wrote:
>
> > Ray Andraka wrote:
> >
> > > I'm trying to use the registers in the altera EAB from synplicity.
> > > Works fine, but one bit in my ROM happens to always be zero, so
> > > synplicity is optimizing that out to a soft-buf.  I've tried to use the
> > > SYN_PRESERVE attribute, but it doesn't want to keep the errant
> > > register.  The result is the table is getting implemented in LEs
> > > instead.  Has anyone else seen this?  Any ideas on how to make it stay?
> > >
> > > --
> > > -Ray Andraka, P.E.
> > > President, the Andraka Consulting Group, Inc.
> > > 401/884-7930     Fax 401/884-7950
> > > email randraka@ids.net
> > > http://users.ids.net/~randraka
> >
> > To my knowledge Synplify can't infer ROM into EABs (at least up to version
> > 5.0.7). I've had to use a "black box" workaround calling a LPM macro in the
> > Altera library. This has the unfortunate effect that you have to supply an
> > additional simulation model for direct VHDL, VERILOG simulation.
> >
> > --
> > Hans Christian Lønstad       Data Respons AS
> >                              Sandviksveien 26
> > Real Time                    1322 Høvik
> > Professionals                Norway
> >
> > mailto:Hans.Christian.Lonstad@datarespons.no
> > http://www.datarespons.no
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15474
Subject: DesignWorks now available direct in Europe from EuroEDA
From: info <info@euro-eda.com>
Date: Thu, 25 Mar 1999 17:57:39 +0000
Links: << >>  << T >>  << A >>
DesignWorks by Capilano Computing Inc. is now available direct in Europe
from EuroEDA Limited.

DesignWorks is a low-cost, Windows-based tool set for FPGA design,
digital simulation and general purpose board design.

Contact us at info@euro-eda.com for more information, or visit our web
site at http://www.euro-eda.com.

All software tools supplied by EuroEDA are available to Universities and
other educational establishments for teaching/research use at
substantially reduced prices. Contact us for details of our educational
packages.
-- 
EuroEDA Limited
Phone:  +44 (0)1933 676373
Fax:    +44 (0)1933 676372
Email:  info@euro-eda.com
Web:    http://www.euro-eda.com 


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