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Messages from 15475

Article: 15475
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: Joel.Kolstad@USA.Net
Date: Thu, 25 Mar 1999 19:17:52 GMT
Links: << >>  << T >>  << A >>
In article <7dcvii$iah$1@arachne.labyrinth.net.au>,
  Hamish Moffatt <hamish@rising.com.au> wrote:
> Sure. You can get the specs for a PC and the i386 easily, or hardware
> vendors provide enough information to write drivers, or write it themselves.

Not quite.  Many standards are readily available, but I defy you to obtain the
following information and publish it publically:

-- Intel's writeup of the performance counters/registers in Pentiums
-- Their documentation of the reprogrammable parts of a Pentium, and the
encrypted bitstream needed to access them
-- Register layouts/explanations of the 3D acceleration features of any 3DFX
PCI video card, or an NVidia Riva TNT/TNT2-based card.

> But Xilinx don't publish their bitstream format, do they?

It's not like they're doing this to be mean to you...  I also believe that if
you actually got the point of having developed working software to target
Xilinx parts, and only needed the bitstream format to finish it off, Xilinx
would be pretty willing to talk to you under NDA.

> So you can't
> write your own complete software.

Sure you can, NeoCAD reverse engineered the bitstream, you can too!

---Joel Kolstad

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 15476
Subject: Re: Info about FPGA/PLD
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Thu, 25 Mar 1999 11:29:56 -0800
Links: << >>  << T >>  << A >>
If we're going to be picky, might as well also point out that the
Philips "zero power" CPLDs have static current specs in the tens
of microamps (e.g. 35 uA for the PZ3032C). Quite a bit closer to
zero. Not meaning to disparage Peter's generally helpful quick
summary for the neophyte.

Ray Andraka wrote:
> 
> Peter Alfke wrote:
> 
> > FPGAs have a more versatile structure with lots and lots of
> > flip-flops. Static power consumption is zero, it's all
> > dynamic and thus proportional to clock rate.
> 
> Really?!! Where can I get some of these FPGAs with zero static
> dissipation.  Last I checked, seems that the majority of devices had
> static currents of 5-10mA
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka

 
Tom Burgess
Article: 15477
Subject: Re: DIY Xilinx Download Cable
From: Richard.Radix@BTinternet.com (Richard Dungan)
Date: Thu, 25 Mar 1999 19:46:31 GMT
Links: << >>  << T >>  << A >>
"Leon Heller" <leon_heller@hotmail.com> wrote:

>Having just attended a Xilinx symposium,

Hi, Leon.

Were you at the Bracknell do?

Richard

------------Richard Dungan-------------
Radix Electronic Designs, Orpington, UK
      Spamtrapped: Remove the XY
---------------------------------------
Article: 15478
Subject: Re: FPGA Express Synthesis Problem
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 25 Mar 1999 20:03:09 +0000
Links: << >>  << T >>  << A >>


"Adam J. Elbirt" wrote:

> Hi all - have a synthesis question for you.  I'm using FPGA Express
> targetting a Xilinx Virtex chip.  My design has four large
> look-up-tables, each having 256 addresses and outputs a 32-bit data
> word.  I had figured this would be trivial to synthesize as a RAM
> (really a PROM) and that I would either continuously load the constants
> that the tables would output or use the GSR to reset/preset the
> registers to the constants and than route the outputs to the inputs.  In
> either case, FPGA Express takes forever to complete - I killed it after
> waiting 48 hours using a K6-300 MHz system with 128 MB RAM and 1.2 GB
> swap space.  However, if I change the table to be implemented as a
> massive decoder comprised entirely of combinatorial logic, it finishes
> inside of an hour.  Any ideas as to why the RAM/register implementation
> causes the tool to choke?
>
> Thanks.
>
> Adam

The problem is that FPGA Express [and its big brother DC-Compiler] has no
memory inference engine and so cannot determine from the RTL source that it
should use one of the Xilinx ``Select-RAMs''. In theory it should be able to
infer a RAM16X1D from the following
Verilog code:

    reg [7:0] mem [15:0]
    always @(posedge clk) begin
       if (write_en)
            mem[write_addr] <= data_in;
    end

   assign data_out = mem[read_addr];

Which both the Synplify tool we use and Leonardo Spectrum do quite happily.
In fact the F-Express app note on implementing memory in Xilinx parts tell
you to use the LOGIBLOX macro generator and instantiate the result.

Article: 15479
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 25 Mar 1999 12:24:35 -0800
Links: << >>  << T >>  << A >>
Joel.Kolstad@USA.Net wrote:

>   Hamish Moffatt <hamish@rising.com.au> wrote:
> > So you can't write your own complete software.
>
> Sure you can, NeoCAD reverse engineered the bitstream, you
> can too!
>  

Just grab a few experienced guys, spend a few dozen
man-years, and then find out that there is no way to make
money. If that's your idea of fun, go ahead...

Peter Alfke

Article: 15480
Subject: "WHATíS THAT ROTTEN SMELL IN PHOENIX?"...We need your help!
From: cealone@aol.com
Date: Thursday, 25 Mar 1999 17:53:42 -0600
Links: << >>  << T >>  << A >>
"WHATíS THAT ROTTEN SMELL IN PHOENIX?" Thatís the title of a featured story in TIME Magazine http://cgi.pathfinder.com/time/magazine/1998/dom/981123/special_report.corporat5a.html (11/23/98 issue) and the reason TIME came to Phoenix to find out why a BRILLIANT grass roots group is making such a big stink about an even bigger one. BLATANT air pollution, toxic spills, illegal zoning, corporate welfare from a single huge SUMITOMO SITIX factory smack dab in the middle of a residential area! Our relentless group has won every single legal battle against them. We are ready to go to trial for certain victory, EXCEPT, we just donít have enough money! Donít let another corporate giant get away with bullying another innocent neighborhood. PLEASE DONATE.  We need your help!  Any contribution over $50.00 will be returned to donor when we win and should we collect our legal fees.

Please send donations to Sumitomo Legal Fund, Citizen's Environmental Awareness League, P.O. Box 30333, Phoenix, AZ 85046-0333.  Please include your name and address if you want your donation returned when we collect our legal fees.

For more information about our orgainziation and our fight please visit our web site at http://www.ceal.com.


LBvK2NPath: ix.netcom.com!su-news-hub1.bbnplanet.com!cpk-news-hub1.bbnplanet.com!news.gtei.net!news-peer.gip.net!news-lond.gip.net!news.gsl.net!gip.net!dispose.news.demon.net!demon!news.demon.co.uk!demon!mudchute.algor.co.uk!not-for-mail
Article: 15481
Subject: Re: Info about VHDL syntesis
From: "Mike Roberts" <mfroberts@mediaone.net>
Date: Thu, 25 Mar 1999 18:48:16 -0600
Links: << >>  << T >>  << A >>
Lattice offers their ispEXPERT system free. It includes the Synario dev.
Enviroment, Schematic Capture, ABEL-HDL compiler and functional simuation.
It's a lot less crippled than before, only the 1016, 2032 and GALs were
supported.  Now any part up to 500 macrocells is supported.


Ray Andraka <randraka@ids.net> wrote in message
news:36FA4BAC.431636FE@ids.net...
> The isp1016 is a Lattice Semiconductor part, not Xilinx.  Go to the
> lattice website www.latticesemi.com for more info on the device and the
> tools.  Lattice used to give away a crippled version of Synario that
> would handle the isp1016 fine.  I don't know what they are offering in
> the way of free tools today.
>
> FFabio wrote:
>
> > Hi,
> >
> > I need some information about VHDL language,
> > literature and free tool for develop simple start application
> > with Xilinx isp1016.
> >
> > Thanks and regards,
> > Fabio
>
>
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
>
>


Article: 15482
Subject: Re: FPGA Express FSM Synthesis Concern
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Thu, 25 Mar 1999 18:13:52 -0800
Links: << >>  << T >>  << A >>
Sorry, I used the word process incorrectly.  I'm a Verilog person, so I
related to "process" as a verilog "alway @ ()" construct.  You can't mix
ff's and comb in a single "always" that a synthesis tool will accept.

Will a synthesizer accept your example?

bruce


Brian Boorman wrote in message <36F7F165.3480CCBE@harris.com>...
>Not true. You can mix comnbinational and registered ouptuts in same
>process.
>
>For example...
>
>pTest: process (reset, clock, {comb. signals})
>begin
>  if (reset = '1') then
>    ...reset registered sig's here
>  elsif (rising_edge(clock)) then
>    ...registered sig assigns
>  end if;
>  ... comb assigns here
>end process;
>
>Bruce Nepple wrote:
>>
>> I don't think that can be done.  If you have 1 output that is the OR of
two
>> states, then you need a comb. output.  If you are inferring flip-fops in
a
>> process you can't have comb. outputs.
>>
>> bruce
>>
>
>--
>Brian C. Boorman
>Harris RF Communications
>Rochester, NY 14610
>XYZ.bboorman@harris.com
><Remove the XYZ. for valid address>


Article: 15483
Subject: Re: FPGA Express Synthesis Problem
From: "Adam J. Elbirt" <aelbirt@nac.net>
Date: Thu, 25 Mar 1999 21:43:34 -0500
Links: << >>  << T >>  << A >>
At one point I actually tried to use Logiblox to get around this problem (as
both you and Jerry described).  Unfortunately, Xilinx doesn't support Logiblox
for the Virtex family and that is the only line of parts in which I can fit my
design (~100k gates).  I did receive email from Joe Maloney of Xilinx about a
way to get around the problem by directly instantiating a LUT - he pointed me to
http://www.xilinx.com/xapp/xapp130.pdf for an app note about this type of
problem for anyone who is interested.

Thanks to all and especially Joe!

Adam

Rick Filipkiewicz wrote:

> "Adam J. Elbirt" wrote:
>
> > Hi all - have a synthesis question for you.  I'm using FPGA Express
> > targetting a Xilinx Virtex chip.  My design has four large
> > look-up-tables, each having 256 addresses and outputs a 32-bit data
> > word.  I had figured this would be trivial to synthesize as a RAM
> > (really a PROM) and that I would either continuously load the constants
> > that the tables would output or use the GSR to reset/preset the
> > registers to the constants and than route the outputs to the inputs.  In
> > either case, FPGA Express takes forever to complete - I killed it after
> > waiting 48 hours using a K6-300 MHz system with 128 MB RAM and 1.2 GB
> > swap space.  However, if I change the table to be implemented as a
> > massive decoder comprised entirely of combinatorial logic, it finishes
> > inside of an hour.  Any ideas as to why the RAM/register implementation
> > causes the tool to choke?
> >
> > Thanks.
> >
> > Adam
>
> The problem is that FPGA Express [and its big brother DC-Compiler] has no
> memory inference engine and so cannot determine from the RTL source that it
> should use one of the Xilinx ``Select-RAMs''. In theory it should be able to
> infer a RAM16X1D from the following
> Verilog code:
>
>     reg [7:0] mem [15:0]
>     always @(posedge clk) begin
>        if (write_en)
>             mem[write_addr] <= data_in;
>     end
>
>    assign data_out = mem[read_addr];
>
> Which both the Synplify tool we use and Leonardo Spectrum do quite happily.
> In fact the F-Express app note on implementing memory in Xilinx parts tell
> you to use the LOGIBLOX macro generator and instantiate the result.

Article: 15484
Subject: Re: Info about FPGA/PLD
From: rk <stellare@erols.com.NOSPAM>
Date: Thu, 25 Mar 1999 22:03:27 -0500
Links: << >>  << T >>  << A >>
hi,

i think a lot just, well, depends.

many of the fpga's i use (q-logic, actel) normally have a static current
of around hundred or so uA and that's from an on-chip charge pump.  i
normally measure this with the inputs held at either Vcc or GND so there
is no totem pole current.  a good quality cmos part should have a very low
static current.  perhaps with some FPGAs there are some on-chip
oscillators that are running or some inputs that are being driven with TTL
logic '1' levels.

the cmos asics i have had made (chipx qyh500, cx2001, and cx3001) mostly
all had currents that were in the noise level of the adc on the power
supply, which is tens of uA.  i measured a few with a good current shunt
and they were very low, as would be expected.

the altera's that i have running are, well, let us say, warm to the touch
(they're pretty old, didn't do the intial design, don't know much about
them - 5192) and the dl5000 was quite a heater (bicmos process @ ~50mW or
so per enabled logic block).

the "cmos" pals that i have used were obviously not fully "cmos."

just a thought,

rk

______________________________

Tom Burgess wrote:

> If we're going to be picky, might as well also point out that the
> Philips "zero power" CPLDs have static current specs in the tens
> of microamps (e.g. 35 uA for the PZ3032C). Quite a bit closer to
> zero. Not meaning to disparage Peter's generally helpful quick
> summary for the neophyte.
>
> Ray Andraka wrote:
> >
> > Peter Alfke wrote:
> >
> > > FPGAs have a more versatile structure with lots and lots of
> > > flip-flops. Static power consumption is zero, it's all
> > > dynamic and thus proportional to clock rate.
> >
> > Really?!! Where can I get some of these FPGAs with zero static
> > dissipation.  Last I checked, seems that the majority of devices had
> > static currents of 5-10mA
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email randraka@ids.net
> > http://users.ids.net/~randraka
>
>
> Tom Burgess



Article: 15485
Subject: Re: Free Xilinx Vendor Tools ... JBits
From: Steve Casselman <sc@vcc.com>
Date: Thu, 25 Mar 1999 20:04:22 -0800
Links: << >>  << T >>  << A >>
> But Xilinx don't publish their bitstream format, do they? So you can't
> write your own complete software.
>

With JBits you won't need to know the exact bit format.  People
are starting to write their own tools that bypass the Xilinx software
altogether.

It may be that soon, 1-2 yrs, you will have free tools
that can program the latest Xilinx parts (Virtex).
By creating an API into the Xilinx bit stream
Steven Guccione and Delon Levi have developed
a powerful new tool that will give users a whole
new level of access to FPGAs.


--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 15486
Subject: Re: We require your help please
From: thor@sm.luth.se (Jonas Thor)
Date: Fri, 26 Mar 1999 05:33:40 GMT
Links: << >>  << T >>  << A >>
Hi,

Why not try the answers database at http:/support.xilinx.com ?
You might find what you are looking for...

/ Jonas

On 25 Mar 1999 19:15:26 GMT, <garryg@super.net.uk> wrote:

>My Friend and I are trying to trace the following information:
>
>1. The Lyrics to a song called "Somewhere in Time"    (from a musical not sure.)
>contact vanda@netscape.net
>http://www.vandaking.com
>
>2. The Sheet Music to a song called OH HAPPY DAYS a gospel song from sister act film I think?
>contact garryg@super.net.uk
>http://user.super.net.uk/~garryg
>
>
>
>Thanks  Garry
>

Article: 15487
Subject: Re: keeping an Altera EAB register in synplicity
From: Hans Christian =?iso-8859-1?Q?L=F8nstad?=
Date: Fri, 26 Mar 1999 08:27:12 +0100
Links: << >>  << T >>  << A >>
How do you specify (in VHDL) the content of the ROM? I have used an integ=
er array (as
GENERIC) for a "black box" approach and externally computed a memory cont=
ent file.
The MAXPLUS tool requires a memory content file for initialization of the=
 EAB ROM.
Does Synplify create this for you?.
One way of circumventing the problem might be to specify a randomized con=
tent to the
synthesis phase, then replacing the ROM content file with the wanted one =
prior to
place and route in MAXPLUS.


Ray Andraka wrote:

> Forgot to mention it.  HDL analyst shows the register in the RTL view, =
but it is
> stripped out and replaced with a soft buffer in the technology view.  W=
ithout the
> SYN_PRESERVE attribute, the register is optimized out in the RTL view t=
oo.
>
> Ray Andraka wrote:
>
> > Synplicity 5.08, which you can download from their site, correctly in=
fers a ROM
> > into EAB if you use the ALTERA_IMPLEMENT_IN_EAB attribute on the bloc=
k you want
> > to put in the EAB.  If that block includes registers at the output, t=
he EAB
> > registers get invoked.  If any bit is registered, then all bits must =
be
> > registered, or it can't be implemented in an EAB.  The problem I am h=
aving is
> > that one of the bits in the ROM is 'stuck at zero' so the register ge=
ts
> > optimized off that bit.  Since one bit is now unregistered, the whole=
 thing
> > gets thrown out of the EAB.  I've got another instance of the same co=
mponent,
> > different data that implements just fine.
> >
> > I'd rather avoid having to instantiate the EAB as a black box if I ca=
n.  It's
> > kind of a pain in the patoot at the system level.
> >
> > Hans Christian L=F8nstad wrote:
> >
> > > Ray Andraka wrote:
> > >
> > > > I'm trying to use the registers in the altera EAB from synplicity=
=2E
> > > > Works fine, but one bit in my ROM happens to always be zero, so
> > > > synplicity is optimizing that out to a soft-buf.  I've tried to u=
se the
> > > > SYN_PRESERVE attribute, but it doesn't want to keep the errant
> > > > register.  The result is the table is getting implemented in LEs
> > > > instead.  Has anyone else seen this?  Any ideas on how to make it=
 stay?
> > > >
> > > > --
> > > > -Ray Andraka, P.E.
> > > > President, the Andraka Consulting Group, Inc.
> > > > 401/884-7930     Fax 401/884-7950
> > > > email randraka@ids.net
> > > > http://users.ids.net/~randraka
> > >
> > > To my knowledge Synplify can't infer ROM into EABs (at least up to =
version
> > > 5.0.7). I've had to use a "black box" workaround calling a LPM macr=
o in the
> > > Altera library. This has the unfortunate effect that you have to su=
pply an
> > > additional simulation model for direct VHDL, VERILOG simulation.
> > >
> > > --
> > > Hans Christian L=F8nstad       Data Respons AS
> > >                              Sandviksveien 26
> > > Real Time                    1322 H=F8vik
> > > Professionals                Norway
> > >
> > > mailto:Hans.Christian.Lonstad@datarespons.no
> > > http://www.datarespons.no
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email randraka@ids.net
> > http://users.ids.net/~randraka
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka




--
Hans Christian L=F8nstad       Data Respons AS
                             Sandviksveien 26
Real Time                    1322 H=F8vik
Professionals                Norway

mailto:Hans.Christian.Lonstad@datarespons.no
http://www.datarespons.no


Article: 15488
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: Richard Guerin <guerin2@home.com>
Date: Fri, 26 Mar 1999 07:46:25 GMT
Links: << >>  << T >>  << A >>
Let me try to clarify where I'm coming from:

First, let me point out that I never suggested that FPGA vendors are not
entitled to make a profit.  In fact, I completely agree that FPGA
vendors who provide low cost development tool suites should be fairly
compensated (PLEASE NOTE: that I'm referring to a tool suite that
includes design entry, synthesis, simulation, place & route). I believe
that this is service that enables new FPGA designers to participate in
the market by breaking down barriers of entry (especially capital
barriers). I especially support the practice of providing affordable
tools to students.

My view diverges, however, when it comes to place-and-route tools. IMHO,
P&R tools and FPGA devices exist in symbiosis and should therefore be
considered as one body of work. After all, what real good is a P&R tool
unless your going to make chip ... conversely, what good is chip unless
you have a P&R tool to crunch your netlist ? So, who would benefit from
a free P&R tool .... Hmmmmmm, how about someone who was going to burn an
FPGA ... someone who was going to PAY for an FPGA ?  Does it seem
logical that the largest FPGA vendor in the world would be in the best
competitive position to roll software development costs into the price
of their products ?  I'm pretty sure that Intel passes on charges to you
for new compiler development each time they introduce a new CPU
architecture.

What I'm suggesting is that Xilinx should go one step further in become
the leading enabler of the FPGA development community by offering a free
downloadable version of an Aliance-like tool ... no fancy green box...
no fat 6 CD ROM package that includes installation CDs for OSs that you
don't own ... no free ModelSim eval CD ... perhaps even limit the number
of device libraries that can be downloaded.  

BTW .... I don't argue this point for myself. I work for a very large
global corporation  ... in fact, a key element of the Dow Jones
Industrial 30. I get all free FPGA development tools (including Xilinx)
that I can stand :-)  Rather, I argue this point as a matter of
principle.
Article: 15489
Subject: Re: FPGA Express Synthesis Problem
From: "Gary Cook" <gc@adv.sonybpe.com>
Date: Fri, 26 Mar 1999 08:34:44 -0000
Links: << >>  << T >>  << A >>
Actually Xilinx does support LogicBlox for the Virtex family but only for
memory elements, nothing else  at present. You have to set the family
type to xc4000xl in the LogiBlox setup and the resulting RAM modules
will work for Virtex. I've done this quite successfully using a number of
different RAMs. You can also get block RAM through the Core generator.

Gary Cook.
Oxford, UK.


Adam J. Elbirt wrote in message <36FAF456.AA13AB9F@nac.net>...
>At one point I actually tried to use Logiblox to get around this problem
(as
>both you and Jerry described).  Unfortunately, Xilinx doesn't support
Logiblox
>for the Virtex family and that is the only line of parts in which I can fit
my
>design (~100k gates).  I did receive email from Joe Maloney of Xilinx about
a
>way to get around the problem by directly instantiating a LUT - he pointed
me to
>http://www.xilinx.com/xapp/xapp130.pdf for an app note about this type of
>problem for anyone who is interested.
>
>Thanks to all and especially Joe!
>
>Adam
>
>Rick Filipkiewicz wrote:
>
>> "Adam J. Elbirt" wrote:
>>
>> > Hi all - have a synthesis question for you.  I'm using FPGA Express
>> > targetting a Xilinx Virtex chip.  My design has four large
>> > look-up-tables, each having 256 addresses and outputs a 32-bit data
>> > word.  I had figured this would be trivial to synthesize as a RAM
>> > (really a PROM) and that I would either continuously load the constants
>> > that the tables would output or use the GSR to reset/preset the
>> > registers to the constants and than route the outputs to the inputs.
In
>> > either case, FPGA Express takes forever to complete - I killed it after
>> > waiting 48 hours using a K6-300 MHz system with 128 MB RAM and 1.2 GB
>> > swap space.  However, if I change the table to be implemented as a
>> > massive decoder comprised entirely of combinatorial logic, it finishes
>> > inside of an hour.  Any ideas as to why the RAM/register implementation
>> > causes the tool to choke?
>> >
>> > Thanks.
>> >
>> > Adam
>>
>> The problem is that FPGA Express [and its big brother DC-Compiler] has no
>> memory inference engine and so cannot determine from the RTL source that
it
>> should use one of the Xilinx ``Select-RAMs''. In theory it should be able
to
>> infer a RAM16X1D from the following
>> Verilog code:
>>
>>     reg [7:0] mem [15:0]
>>     always @(posedge clk) begin
>>        if (write_en)
>>             mem[write_addr] <= data_in;
>>     end
>>
>>    assign data_out = mem[read_addr];
>>
>> Which both the Synplify tool we use and Leonardo Spectrum do quite
happily.
>> In fact the F-Express app note on implementing memory in Xilinx parts
tell
>> you to use the LOGIBLOX macro generator and instantiate the result.
>


Article: 15490
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: Richard Guerin <guerin2@home.com>
Date: Fri, 26 Mar 1999 08:48:04 GMT
Links: << >>  << T >>  << A >>


Joel.Kolstad@USA.Net wrote:
> 

> It's nice that other vendors give away their lower ends tools for free -- I've
> certainly taken advantage of this myself, and encourage others to do so.

I concur :-)

> Heck, I bet most distributors will gladly give you a copy of
> the $99 package if you're buying 100 parts per month on a continuous basis.

Doesn't seem like a fair trade to me. Commit to spending approx
$10-30K/Month for a $99 tool ?


> Perhaps they figure that, for $99, you'll at least
> spend some time to fully evaluate their tool set and get to know its power --
> despite its quirks -- instead of just grabbing the nice free piece of P&R
> software that you can get your hands on?

Charging $99 or $0.99 provides little value added for the tools at this
end of the market.
BTW: As I write this, FPGAS that were developed with FREE place and
route tools 
are being used to deliver bombs overseas with pinpoint accuracy ! 
FREE TOOLS HELPING TO KEEP THE WORLD FREE !!!!!!!!

> Cisco spend millions of dollars per year with Xilinx, and I can't imagine
> that $5K for the tools was at all a high priority in their selection criteria.

I can't imagine that after spending millions of dollars that Cisco still
has to pay $5K  for
Xilinx specific tools ! BTW I didn't realize that Xilinx Place & Route
tools were so expensive.
I got my Alliance tool for free ;-)
Article: 15491
Subject: Re: FPGA Express Synthesis Problem
From: Le mer Michel <michel.lemer@ago.fr>
Date: Fri, 26 Mar 1999 10:58:44 +0100
Links: << >>  << T >>  << A >>
Adam J. Elbirt wrote:

> Hi all - have a synthesis question for you.  I'm using FPGA Express
> targetting a Xilinx Virtex chip.  My design has four large
> look-up-tables, each having 256 addresses and outputs a 32-bit data
> word.  I had figured this would be trivial to synthesize as a RAM
> (really a PROM) and that I would either continuously load the constants
> that the tables would output or use the GSR to reset/preset the
> registers to the constants and than route the outputs to the inputs.  In
> either case, FPGA Express takes forever to complete - I killed it after
> waiting 48 hours using a K6-300 MHz system with 128 MB RAM and 1.2 GB
> swap space.  However, if I change the table to be implemented as a
> massive decoder comprised entirely of combinatorial logic, it finishes
> inside of an hour.  Any ideas as to why the RAM/register implementation
> causes the tool to choke?
>
> Thanks.
>
> Adam

The ram16x1s or ram16x1d are recognized has ram module to instantiate by
FPGA express, for 4000 and virtex family. Others modules like 16x4d or
32x2s ... are in the xilinx library  and recognized by FPGA express but I
am not sure of the target.

One easy way to see which are the component in the library is to open a
schematic entry and call the components. You can see the exact name and
port name of the components. After, you will only need to instantiate them
in your vhdl file.

Here is an example to instantiate a 5 bits wide by 16 bit depth single port
memory, this can be placed into 4000 and virtex target (and may be other
chips).

component ram16x1s
port (a3, a2, a1, a0, d : in std_logic;
        o : out std_logic;
        we, wclk : in std_logic);
end component;

begin

blabla : for i in 0 to 4 generate
 my_ram : ram16x1s port map
(a3 => a3,
 a2 => a2,
 a1 => a1,
 a0 => a0,
 d => data(i),
 we => my_we,
 wclk => my_clk);
end generate;

good luck.
Hope this helps,

Michel Le Mer
Gerpi sa (Xilinx Xpert)
3, rue du Bosphore
Alma city
35000 Rennes
France
(02 99 51 17 18)
http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm

Article: 15492
Subject: Re: FPGA Express Synthesis Problem
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 26 Mar 1999 11:03:59 +0000
Links: << >>  << T >>  << A >>


Le mer Michel wrote:The ram16x1s or ram16x1d are recognized has ram module to
instantiate by

> FPGA express, for 4000 and virtex family. Others modules like 16x4d or
> 32x2s ... are in the xilinx library  and recognized by FPGA express but I
> am not sure of the target.

This is o.k. as far as it goes but its not portable, unlike the architecture
independent Verilog
description.

BTW: Is there a common standard for memory inference from Verilog/VHDL ? Is one
emerging ?


Article: 15493
Subject: Re: What do you think about philips XPLA?
From: "Dr. Peter Schulz" <p.schulz@signaal.de>
Date: Fri, 26 Mar 1999 12:04:41 +0100
Links: << >>  << T >>  << A >>
The tools are easy to use and the CoolRunners
are "real" low power devices.

NO-SPAM (damiano) schrieb in Nachricht ...
>They seem low cost available and with low cost tools.
>But performance compared to Xilinx and others?
>
>Damiano Rullo
>Trezzano S/N
>Milan, Italy
>http://members.it.tripod.de/Damianoux/index.html
>mailto: dmn@cheerful.com
>mailto: damiano@mclink.it
>


Article: 15494
Subject: Re: Reconfigurable computing thesis on the web
From: zik@zikzak.net (Zik Saleeba)
Date: 26 Mar 1999 22:24:50 +1100
Links: << >>  << T >>  << A >>
mikesw@whiterose.net (M Sweger) writes:

>Question: I haven't read the paper yet, but how does this differ from the
> fault tolerant computers from a few years back? And if the paper describes

The thesis doesn't actually tackle the problem of fault tolerance at
all, though that's certainly an excellent idea. I can conceive of an
architecture where normal foundry defects are quite acceptable and
worked around at runtime as a matter of course. The result - even
high density wafers with flaws would be acceptable and the silicon
would be very cheap to make since there would be few rejects.

But like I say, this wasn't part of my thesis - I'm just extemporising
from your mention of fault tolerance...

The reconfigurability of the system was focussed at a computational
end rather than fault-tolerance in this case.

Zik
Article: 15495
Subject: xilinx virtex parallel download from SUN
From: Stefan Schmid <Stefan.Schmid@eedn.ericsson.se>
Date: Fri, 26 Mar 1999 12:56:30 +0100
Links: << >>  << T >>  << A >>
Does anybody know how can i download bitfile to a Xilinx Virtex device
via a "parallel download cable" from a SUN Solaris machine.
Xilinx does not support this feature on unix machines.

I tried to write the bit file to the parallel device file /dev/bpp0
but i got the error message :
   cat: write error: No such device or address


Regards
Stefan Schmid
Article: 15496
Subject: Re: keeping an Altera EAB register in synplicity
From: Ray Andraka <randraka@ids.net>
Date: Fri, 26 Mar 1999 07:26:38 -0500
Links: << >>  << T >>  << A >>
In this case, the content is a Log table.  Synplicity doesn't seem to handle reals too
well, so I wrote a C program that generates a VHDL package containing arrays of integer
constants, as well as some of the numeric constants and parameters for the design,
produced using the log function and fp arithmetic in C.  Synplicity takes the integer
array and actually generates a gate level representation of the rom array.  I need to
keep this within the VHDL for simulation sake.

Hans Christian LÝnstad wrote:

> How do you specify (in VHDL) the content of the ROM? I have used an integer array (as
> GENERIC) for a "black box" approach and externally computed a memory content file.
> The MAXPLUS tool requires a memory content file for initialization of the EAB ROM.
> Does Synplify create this for you?.
> One way of circumventing the problem might be to specify a randomized content to the
> synthesis phase, then replacing the ROM content file with the wanted one prior to
> place and route in MAXPLUS.
>
>

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15497
Subject: Re: xilinx virtex parallel download from SUN
From: Achim Gratz <gratz@ite.inf.tu-dresden.de>
Date: 26 Mar 1999 15:32:25 +0100
Links: << >>  << T >>  << A >>
Stefan Schmid <Stefan.Schmid@eedn.ericsson.se> writes:

> I tried to write the bit file to the parallel device file /dev/bpp0
> but i got the error message :
>    cat: write error: No such device or address

If that's a Sun with PCI bus, try /dev/ecpp0.  That said, just sending
the bit file to the parallel port will not work.  If Xilinx gave out
the source code for their DOS software it should be no problem to port
it to Suns.


Achim Gratz.

--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW:    http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone:  +49 351 463 - 8325
Article: 15498
Subject: IBM 600MHz FPGA
From: Mike Scott <mike-scott@mediaone.net>
Date: Fri, 26 Mar 1999 09:44:53 -0500
Links: << >>  << T >>  << A >>
I have heard rumors about a 600MHz FPGA from IBM floating around.
I did a search but have not been able to find anything on the
subject.  Could someone who knows anything about this please
comment (via email as well).  We would be extremely interested.

Thanks,
Mike Scott
Article: 15499
Subject: Re: FPGA Express FSM Synthesis Concern
From: Brian Boorman <XZY.bboorman@harris.com>
Date: Fri, 26 Mar 1999 09:56:03 -0500
Links: << >>  << T >>  << A >>
Exemplar Leonardo sure does. :-)

I had to learn Verilog for a graduate class I took, so I understand what
you are saying from that point. After having used both I think I'll
stick to VHDL. (Please, no language wars... just my pref).

Bruce Nepple wrote:
> 
> Sorry, I used the word process incorrectly.  I'm a Verilog person, so I
> related to "process" as a verilog "alway @ ()" construct.  You can't mix
> ff's and comb in a single "always" that a synthesis tool will accept.
> 
> Will a synthesizer accept your example?
> 
> bruce
> 

-- 
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>


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