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Messages from 156300

Article: 156300
Subject: Re: How to find power supply pins in Lattice Diamond projects
From: LM <sala.nimi@mail.com>
Date: Tue, 11 Feb 2014 14:27:05 -0800 (PST)
Links: << >>  << T >>  << A >>
On Tuesday, February 11, 2014 10:33:02 PM UTC+2, Gabor wrote:
> LM wrote:
> 
> > I have a Mach02 demo board and am driving it with Lattice Diamond. With some searching I found io pin list of the device, but there are no power supply pins in that list. Probably something else is missing on that list too.
> 
> > 
> 
> > There are many many data sheets and app notes from Lattice, but this is missing. Perhaps one good would have been better.
> 
> > 
> 
> > The chip in the Mach02 board is Lcmx02-1200ze 1tg144, by the way.
> 
> 
> 
> The Device data sheet says:
> 
> 
> 
> "For further information regarding logic signal connections for various
> 
> packages please refer to the MachXO2 Device Pinout Files."
> 
> 
> 
> But of course there's no link, and on their website under:
> 
> Products --> MachXO2 --> documents --> datasheets
> 
> the files are called "Package Migration Files" instead...
> 
> 
> 
> See:
> 
> 
> 
> http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2144-PinTQFPPackageMigrationFile.CSV
> 
> 
> 
> -- 
> 
> Gabor

Continuing my former message. 

This is probably not news to anyone, but I think that exporting this file from the project I could the my own pin names there too. This matters when there are a lot of used pins. Less errors and faster.

Article: 156301
Subject: Re: DSP with sensor i2c interface
From: sudheerpaniyur@gmail.com
Date: Tue, 11 Feb 2014 22:03:11 -0800 (PST)
Links: << >>  << T >>  << A >>
iam using camera fpga dsp i hav problem in sendind i2c cmd from dsp, if i use i cmd is working if u send more than 1 cmd its not working pls give soltion.
this is dsp code it send to fpga to camera control reg


int z;
	*(unsigned short *)(SERVO_ADDR + 2 ) =  0x1003; //HEIGT
	*(unsigned short *)(SERVO_ADDR + 4 ) =0x08;
	for(z=0;z<=0xCCCC;z++);

	*(unsigned short *)(SERVO_ADDR + 2 ) =0x1107; hand shake signals
	*(unsigned short *)(SERVO_ADDR + 4 ) =0x1234;
	for(z=0;z<=0x28F5C;z++);

	*(unsigned short *)(SERVO_ADDR + 2 ) = 0x1004;//WIDTH
	*(unsigned short *)(SERVO_ADDR + 4 ) =0x1004;
	for(z=0;z<=0xCCCC;z++);

	*(unsigned short *)(SERVO_ADDR + 2 ) = 0x1107; hand shake signal
	*(unsigned short *)(SERVO_ADDR + 4 ) =0x1234;
	for(z=0;z<=0x28F5C;z++);

	*(unsigned short *)(SERVO_ADDR + 2 ) = 0x1005;//HB
	*(unsigned short *)(SERVO_ADDR + 4 ) =0x015A;
	for(z=0;z<=0xCCCC;z++);

Article: 156302
Subject: Re: How to find power supply pins in Lattice Diamond projects
From: LM <sala.nimi@mail.com>
Date: Wed, 12 Feb 2014 13:47:12 -0800 (PST)
Links: << >>  << T >>  << A >>
On Wednesday, February 12, 2014 12:27:05 AM UTC+2, LM wrote:
> On Tuesday, February 11, 2014 10:33:02 PM UTC+2, Gabor wrote:
>=20
> > LM wrote:
>=20
> >=20
>=20
> > > I have a Mach02 demo board and am driving it with Lattice Diamond. Wi=
th some searching I found io pin list of the device, but there are no power=
 supply pins in that list. Probably something else is missing on that list =
too.
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > There are many many data sheets and app notes from Lattice, but this =
is missing. Perhaps one good would have been better.
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > The chip in the Mach02 board is Lcmx02-1200ze 1tg144, by the way.
>=20
> >=20
>=20
> >=20
>=20
> >=20
>=20
> > The Device data sheet says:
>=20
> >=20
>=20
> >=20
>=20
> >=20
>=20
> > "For further information regarding logic signal connections for various
>=20
> >=20
>=20
> > packages please refer to the MachXO2 Device Pinout Files."
>=20
> >=20
>=20
> >=20
>=20
> >=20
>=20
> > But of course there's no link, and on their website under:
>=20
> >=20
>=20
> > Products --> MachXO2 --> documents --> datasheets
>=20
> >=20
>=20
> > the files are called "Package Migration Files" instead...
>=20
> >=20
>=20
> >=20
>=20
> >=20
>=20
> > See:
>=20
> >=20
>=20
> >=20
>=20
> >=20
>=20
> > http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO=
2144-PinTQFPPackageMigrationFile.CSV
>=20
> >=20
>=20
> >=20
>=20
> >=20
>=20
> > --=20
>=20
> >=20
>=20
> > Gabor
>=20
>=20
>=20
> Continuing my former message.=20
>=20
>=20
>=20
> This is probably not news to anyone, but I think that exporting this file=
 from the project I could the my own pin names there too. This matters when=
 there are a lot of used pins. Less errors and faster.

Mentor Pads seems to be quite picky about file format. I could not use the =
file I got. Only 144 pins to do manually now.

By the way, I seem to think faster than write. My previous message should b=
e something like this: Exporting pin list from IDE, I could use some sensib=
le pin names. Then there would less change for errors. After all, the IDE k=
nows very well what package I am using.

Article: 156303
Subject: Re: Monostable multivibrator
From: hodunov07@gmail.com
Date: Thu, 13 Feb 2014 06:52:15 -0800 (PST)
Links: << >>  << T >>  << A >>
0YfQtdGC0LLQtdGA0LMsIDgg0LDQstCz0YPRgdGC0LAgMTk5NsKg0LMuLCAxMDowMDowMCBVVEMr
MyDQv9C+0LvRjNC30L7QstCw0YLQtdC70YwgdGhvbWFzINC90LDQv9C40YHQsNC7Og0KPiBIaSAs
DQo+IA0KPiBJIG5lZWQgdG8gaW1wbGVtZW50IGEgbW9uby1zdGFibGUgTVZCIGluc2lkZSBhbiBB
bHRlcmEgUExELiBDb3VsZCBhbnlvbmUgDQo+IGhlbHAgPz8NCj4gDQo+IExFRQ0KDQpJIG5lZWQg
dG9vISEhIQ==

Article: 156304
Subject: Re: Monostable multivibrator
From: Tom Gardner <spamjunk@blueyonder.co.uk>
Date: Thu, 13 Feb 2014 15:45:45 +0000
Links: << >>  << T >>  << A >>
On 13/02/14 14:52, hodunov07@gmail.com wrote:
> четверг, 8 августа 1996 г., 10:00:00 UTC+3 пользователь thomas написал:
>> Hi ,
>>
>> I need to implement a mono-stable MVB inside an Altera PLD. Could anyone
>> help ??
>>
>> LEE
>
> I need too!!!!
>

I doubt that your problem (whatever it is) can only be
solved by a monostable.

Define /what/ you want to achieve, not /how/ you want
to achieve it. Then it will become obvious how to use
a PLD.



Article: 156305
Subject: Re: Monostable multivibrator
From: Brian Drummond <brian3@shapes.demon.co.uk>
Date: Thu, 13 Feb 2014 16:13:16 GMT
Links: << >>  << T >>  << A >>
On Thu, 13 Feb 2014 15:45:45 +0000, Tom Gardner wrote:

> On 13/02/14 14:52, hodunov07@gmail.com wrote:
>> четверг, 8 августа 1996 г., 10:00:00 UTC+3 пользователь thomas написал:
>>> Hi ,
>>>
>>> I need to implement a mono-stable MVB inside an Altera PLD. Could
>>> anyone help ??
>>>
>>> LEE
>>
>> I need too!!!!
>>
>>
> I doubt that your problem (whatever it is) can only be solved by a
> monostable.

8 August 1996 ... is this a record?

- Brian

Article: 156306
Subject: Re: Monostable multivibrator
From: Tom Gardner <spamjunk@blueyonder.co.uk>
Date: Thu, 13 Feb 2014 17:11:21 +0000
Links: << >>  << T >>  << A >>
On 13/02/14 16:13, Brian Drummond wrote:
> On Thu, 13 Feb 2014 15:45:45 +0000, Tom Gardner wrote:
>
>> On 13/02/14 14:52, hodunov07@gmail.com wrote:
>>> четверг, 8 августа 1996 г., 10:00:00 UTC+3 пользователь thomas написал:
>>>> Hi ,
>>>>
>>>> I need to implement a mono-stable MVB inside an Altera PLD. Could
>>>> anyone help ??
>>>>
>>>> LEE
>>>
>>> I need too!!!!
>>>
>>>
>> I doubt that your problem (whatever it is) can only be solved by a
>> monostable.
>
> 8 August 1996 ... is this a record?

<Swear words> I doubt it.

I looked at the headers in the repeated posting,
but skipped over the cyrllic!


Article: 156307
Subject: Re: Monostable multivibrator
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 13 Feb 2014 18:55:19 +0000 (UTC)
Links: << >>  << T >>  << A >>
Brian Drummond <brian3@shapes.demon.co.uk> wrote:
> On Thu, 13 Feb 2014 15:45:45 +0000, Tom Gardner wrote:
>> On 13/02/14 14:52, hodunov07@gmail.com wrote:
>>> ??????????????, 8 ?????????????? 1996 ??., 10:00:00 UTC+3 ???????????????????????? thomas ??????????????:
(snip)

> 8 August 1996 ... is this a record?

Or someone forgot to set the clock on the computer.

I believe my posting host will refuse posts that are even a little
off, but not all will.

The exact 10:00:00 looks suspicious.

-- glen

Article: 156308
Subject: Re: Monostable multivibrator
From: Tim Wescott <tim@seemywebsite.really>
Date: Thu, 13 Feb 2014 13:35:03 -0600
Links: << >>  << T >>  << A >>
On Thu, 13 Feb 2014 06:52:15 -0800, hodunov07 wrote:

> четверг, 8 августа 1996 г., 10:00:00 UTC+3 пользователь thomas написал:
>> Hi ,
>> 
>> I need to implement a mono-stable MVB inside an Altera PLD. Could
>> anyone help ??
>> 
>> LEE
> 
> I need too!!!!

Is there a prize available for the oldest dredged-up newsgroup posting?

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com


Article: 156309
Subject: Re: Monostable multivibrator
From: Les Cargill <lcargill99@comcast.com>
Date: Thu, 13 Feb 2014 18:32:13 -0600
Links: << >>  << T >>  << A >>
Brian Drummond wrote:
> On Thu, 13 Feb 2014 15:45:45 +0000, Tom Gardner wrote:
>
>> On 13/02/14 14:52, hodunov07@gmail.com wrote:
>>> четверг, 8 августа 1996 г., 10:00:00 UTC+3 пользователь thomas написал:
>>>> Hi ,
>>>>
>>>> I need to implement a mono-stable MVB inside an Altera PLD. Could
>>>> anyone help ??
>>>>
>>>> LEE
>>>
>>> I need too!!!!
>>>
>>>
>> I doubt that your problem (whatever it is) can only be solved by a
>> monostable.
>
> 8 August 1996 ... is this a record?
>
> - Brian
>


Google Froups has breached the time-space continuum.

-- 
Les Cargill


Article: 156310
Subject: Online Hardware Design Competition: Kode Da Circuit
From: Ajit Mathew <ajitmathew04@gmail.com>
Date: Fri, 14 Feb 2014 05:55:34 -0800 (PST)
Links: << >>  << T >>  << A >>
Felicity '14, brings brings to you one of it's kind, Online VHDL Coding Competition, Kode Da Circuit. In this contest, participants have to come up with hardware solution for given problems which will be simulated using VHDL. 

This is a 24 hour event. The online judge will be using GHDL(http://ghdl.free.fr/) to simulate the VHDL codes. Problems will vary from designing simple circuits to complex hardware used for acceleration. 

We are currently running a familiarization phase (at 
http://felicity.iiit.ac.in/threads/kodedacircuit/) 
so that participants can be comfortable with the judge and the scoring system of the contest. 

The main event will be held on 15th of February at 2:30pm UTC. 

Cash prizes woth Rs 10,000 are up for grab. 

If you have any question reply to this thread. 

Ajit Mathew 
Organiser 

Article: 156311
Subject: How to implement Ethernet packet classification with vhdl on FPGA?
From: tinaliu9089@gmail.com
Date: Sat, 15 Feb 2014 06:28:32 -0800 (PST)
Links: << >>  << T >>  << A >>
I'm working on implement the basic ethernet switch on FPGA. But I don't kno=
w how to parse packet when they enter to switch. I have already used ip cor=
e (Ethernet MAC and fifo )to receive and transmit packet. Does any one has =
vhdl code or referene? Thank you 

Article: 156312
Subject: micro blaze
From: mohamed.benabdeladhim@gmail.com
Date: Sun, 16 Feb 2014 04:44:02 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi all how can we run a set of instructions (application) with Micro Blaz.

Article: 156313
Subject: Re: How to find power supply pins in Lattice Diamond projects
From: Alex <enginven@gmail.com>
Date: Tue, 18 Feb 2014 15:33:25 -0800 (PST)
Links: << >>  << T >>  << A >>
On Wednesday, February 12, 2014 2:47:12 PM UTC-7, LM wrote:
> On Wednesday, February 12, 2014 12:27:05 AM UTC+2, LM wrote:
>=20
> > On Tuesday, February 11, 2014 10:33:02 PM UTC+2, Gabor wrote:
>=20
> >=20
>=20
> > > LM wrote:
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > I have a Mach02 demo board and am driving it with Lattice Diamond. =
With some searching I found io pin list of the device, but there are no pow=
er supply pins in that list. Probably something else is missing on that lis=
t too.
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > There are many many data sheets and app notes from Lattice, but thi=
s is missing. Perhaps one good would have been better.
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > The chip in the Mach02 board is Lcmx02-1200ze 1tg144, by the way.
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > The Device data sheet says:
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > "For further information regarding logic signal connections for vario=
us
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > packages please refer to the MachXO2 Device Pinout Files."
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > But of course there's no link, and on their website under:
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > Products --> MachXO2 --> documents --> datasheets
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > the files are called "Package Migration Files" instead...
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > See:
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/Mach=
XO2144-PinTQFPPackageMigrationFile.CSV
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > --=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > Gabor
>=20
> >=20
>=20
> >=20
>=20
> >=20
>=20
> > Continuing my former message.=20
>=20
> >=20
>=20
> >=20
>=20
> >=20
>=20
> > This is probably not news to anyone, but I think that exporting this fi=
le from the project I could the my own pin names there too. This matters wh=
en there are a lot of used pins. Less errors and faster.
>=20
>=20
>=20
> Mentor Pads seems to be quite picky about file format. I could not use th=
e file I got. Only 144 pins to do manually now.
>=20
>=20
>=20
> By the way, I seem to think faster than write. My previous message should=
 be something like this: Exporting pin list from IDE, I could use some sens=
ible pin names. Then there would less change for errors. After all, the IDE=
 knows very well what package I am using.

This is possible (starting since Diamond 2.2, at least): In Diamond GUI Ope=
n the Spread-sheet view, the go to File>export..

Article: 156314
Subject: Re: How to find power supply pins in Lattice Diamond projects
From: LM <sala.nimi@mail.com>
Date: Tue, 25 Feb 2014 12:33:10 -0800 (PST)
Links: << >>  << T >>  << A >>
On Wednesday, February 19, 2014 1:33:25 AM UTC+2, Alex wrote:
> On Wednesday, February 12, 2014 2:47:12 PM UTC-7, LM wrote:
>=20
> > On Wednesday, February 12, 2014 12:27:05 AM UTC+2, LM wrote:
>=20
> >=20
>=20
> > > On Tuesday, February 11, 2014 10:33:02 PM UTC+2, Gabor wrote:
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > LM wrote:
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > > I have a Mach02 demo board and am driving it with Lattice Diamond=
. With some searching I found io pin list of the device, but there are no p=
ower supply pins in that list. Probably something else is missing on that l=
ist too.
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > > There are many many data sheets and app notes from Lattice, but t=
his is missing. Perhaps one good would have been better.
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > > The chip in the Mach02 board is Lcmx02-1200ze 1tg144, by the way.
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > The Device data sheet says:
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > "For further information regarding logic signal connections for var=
ious
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > packages please refer to the MachXO2 Device Pinout Files."
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > But of course there's no link, and on their website under:
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > Products --> MachXO2 --> documents --> datasheets
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > the files are called "Package Migration Files" instead...
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > See:
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > > http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/Ma=
chXO2144-PinTQFPPackageMigrationFile.CSV
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
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> > > Continuing my former message.=20
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> > > This is probably not news to anyone, but I think that exporting this =
file from the project I could the my own pin names there too. This matters =
when there are a lot of used pins. Less errors and faster.
>=20
> >=20
>=20
> >=20
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> >=20
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> > Mentor Pads seems to be quite picky about file format. I could not use =
the file I got. Only 144 pins to do manually now.
>=20
> >=20
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> >=20
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> >=20
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> > By the way, I seem to think faster than write. My previous message shou=
ld be something like this: Exporting pin list from IDE, I could use some se=
nsible pin names. Then there would less change for errors. After all, the I=
DE knows very well what package I am using.
>=20
>=20
>=20
> This is possible (starting since Diamond 2.2, at least): In Diamond GUI O=
pen the Spread-sheet view, the go to File>export..

It works, thank you. I have to try in a real project first, but it looks go=
od.

Article: 156315
Subject: Re: How to find power supply pins in Lattice Diamond projects
From: LM <sala.nimi@mail.com>
Date: Tue, 25 Feb 2014 15:30:02 -0800 (PST)
Links: << >>  << T >>  << A >>
On Tuesday, February 25, 2014 10:33:10 PM UTC+2, LM wrote:
> On Wednesday, February 19, 2014 1:33:25 AM UTC+2, Alex wrote:
>=20
> > On Wednesday, February 12, 2014 2:47:12 PM UTC-7, LM wrote:
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> >=20
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> > > On Wednesday, February 12, 2014 12:27:05 AM UTC+2, LM wrote:
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> > >=20
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> > > > On Tuesday, February 11, 2014 10:33:02 PM UTC+2, Gabor wrote:
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> > > > > LM wrote:
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> > > > > > I have a Mach02 demo board and am driving it with Lattice Diamo=
nd. With some searching I found io pin list of the device, but there are no=
 power supply pins in that list. Probably something else is missing on that=
 list too.
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> > > > > > There are many many data sheets and app notes from Lattice, but=
 this is missing. Perhaps one good would have been better.
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> > > > > > The chip in the Mach02 board is Lcmx02-1200ze 1tg144, by the wa=
y.
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> > > > > The Device data sheet says:
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> > > > > "For further information regarding logic signal connections for v=
arious
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> > > > > packages please refer to the MachXO2 Device Pinout Files."
>=20
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> > > > > But of course there's no link, and on their website under:
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> > > > > Products --> MachXO2 --> documents --> datasheets
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> > > > > the files are called "Package Migration Files" instead...
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> > > > > See:
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> > > > > http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/=
MachXO2144-PinTQFPPackageMigrationFile.CSV
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> > > > Continuing my former message.=20
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> > > > This is probably not news to anyone, but I think that exporting thi=
s file from the project I could the my own pin names there too. This matter=
s when there are a lot of used pins. Less errors and faster.
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
>=20
> > >=20
>=20
> >=20
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> > > Mentor Pads seems to be quite picky about file format. I could not us=
e the file I got. Only 144 pins to do manually now.
>=20
> >=20
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> > >=20
>=20
> >=20
>=20
> > >=20
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> >=20
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> > >=20
>=20
> >=20
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> > > By the way, I seem to think faster than write. My previous message sh=
ould be something like this: Exporting pin list from IDE, I could use some =
sensible pin names. Then there would less change for errors. After all, the=
 IDE knows very well what package I am using.
>=20
> >=20
>=20
> >=20
>=20
> >=20
>=20
> > This is possible (starting since Diamond 2.2, at least): In Diamond GUI=
 Open the Spread-sheet view, the go to File>export..
>=20
>=20
>=20
> It works, thank you. I have to try in a real project first, but it looks =
good.

Did a quick project and I can see my pin names on the list. Very good.

Now I just have to reinvent the wheel or remember what I did a couple of ye=
ars ago when I last did some work with the chip.

Article: 156316
Subject: New Lattice FPGAs on 40nm ?
From: Brane2 <brankob@avtomatika.com>
Date: Sat, 1 Mar 2014 04:34:01 -0800 (PST)
Links: << >>  << T >>  << A >>
I'm playing with Lattice's MachXO2 and ECP3 for a few months now and now that MachXO3 is about to come out I wonder what happened to ECP4.

As I understand it, Lattice found its market niche in low-power/low-cost branch, especially now when they bought BlueSilicon and incprporated their program in ice40 series.

Knowing that they try to keep the cost down by using one process for all of their models and that MachXO2/ECP3 were done on 65 nm, while new ice40 and MachXO3 are on 40nm node, one would expect to see their high-end ECP4 on 40nm, too.

If main selling point of ECP3 was as cheapest FPGA with fast transceivers, this is diminishing now as MachXO3 will get those, too ( beside other upgrades).

But there is nothing on ECP4. Googling around shows 2 year old failed launch ( they obviously changed their mind) and nothing more.

Will there be ECP4 on 40nm and if so, what will be the update - faster transceivers or perhaps some cool ( preferably MIPS) core hardmacro onboard?

Or is Xilinx pushing too hard on that part of the market with Spartan-6 ?

I know there isn't anything official on the matter, I'm looking for more or less substantiated rumours...

Article: 156317
Subject: FLASH on MachXO2/3
From: Brane2 <brankob@avtomatika.com>
Date: Sat, 1 Mar 2014 10:42:13 -0800 (PST)
Links: << >>  << T >>  << A >>
Part of MachXO2 attraction for me was in internal, user accessible FLASH.

I thought that I could use it for program of some small CPU I could build.

But as far as I can tell, accessing this FLASH is mindoggingly awkward.

I was expectiong to see something like FLASH equivalen of BRAM block, on which I could set depth and width.

After reading the user manual and my first dissapointment I thought that I could still use it, even when acessing it through 8-bit bus.

But now it seems that for each byte I want to read I have to go through whole charade, so I can't just read one 8-bit cell just by putting its adress on some pins, setting adress enable and cycling the clock.

Is this about right or did I misread something ?

Are there any changes in MachXO3 on that matter ?

Article: 156318
Subject: Oberon Operating System + Compiler + Graphic on a Spartan 3 FPGA
From: "MGreim" <99555@embeddedrelated>
Date: Sun, 02 Mar 2014 07:51:06 -0600
Links: << >>  << T >>  << A >>
Hi folks,

Professor Wirth, some may know his name as the inventor of Pascal and
Oberon etc., has published recently, together with Jürg Gutknecht and Paul
Reed,  an exciting project at:

http://www.projectoberon.com/

Its a complete computer including a graphical operating system in a small
FPGA. 
Its including all sources in Oberon and Verilog!
The complete Oberon Code has less then 10000 lines, including the
Compiler!
The team has also developed his own RISC processor design, called RISC5. 
Its running on a Spartan 3 eval. board. 
I have tested it, an it really works! A picture of my personal system at: 
http://www.schleibinger.com/bilder/oberon.jpg

Regards

Markus




	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 156319
Subject: Re: New Lattice FPGAs on 40nm ?
From: Sean Durkin <news_MONTH@tuxroot.de>
Date: Tue, 04 Mar 2014 14:36:56 +0100
Links: << >>  << T >>  << A >>
Brane2 wrote:
> I know there isn't anything official on the matter, I'm looking for
> more or less substantiated rumours...

That I can provide... :)

We were planning on using ECP4 for a product and got early access to
documentation and silicon in the fall of 2012, I think. Lattice back
then was very eager to push this new family and were willing to provide
us with everything we needed for getting something up and running
quickly. Then suddenly out of the blue they let us know that upper
management had decided to scrap the family altogether.
Supposedly, the early engineering samples we received had no major
issues (at least there was nothing serious in the errata), so it seems
there were no technical reasons for this decision; but with Artix and
Cyclone competing, management thought they wouldn't stand a chance with
that family.

We were told Lattice would in the future concentrate on the
low-power/low-cost market, since mid-range and high-end were occupied by
X and A and they were just too small to e.g. get access to sub-40nm
technology that would be necessary to compete in that market. They told
us back then that there will not be an ECP4 with the promised
specifications, ever (which mainly meant the 6G SerDes), only maybe a
stripped-down, low-power version with maybe 3G SerDes, more like an
ECP4-L. Back then they hadn't yet made up their mind on that issue.

To be honest, since then I haven't looked into Lattice. A decision was
made to not use any Lattice parts for any products ever again after that
stunt they pulled. One of their sales people still calls from time to
time to promote the iCE devices (which are nice but completely useless
in our applications), and I think they would've let me know if there
were plans for a family like the ECP4 that was originally planned; so
far nothing...

HTH,
Sean

Article: 156320
Subject: Re: New Lattice FPGAs on 40nm ?
From: Brane2 <brankob@avtomatika.com>
Date: Tue, 4 Mar 2014 17:54:42 -0800 (PST)
Links: << >>  << T >>  << A >>
Thanks. 

Any thoughts on MachXO2/3 ?

Are they serious with that or are they retreating to reserve defence line ?




Article: 156321
Subject: Re: New Lattice FPGAs on 40nm ?
From: Sean Durkin <news_MONTH@tuxroot.de>
Date: Wed, 05 Mar 2014 08:21:26 +0100
Links: << >>  << T >>  << A >>
Brane2 wrote:
> Thanks. 
> 
> Any thoughts on MachXO2/3 ?
> 
> Are they serious with that or are they retreating to reserve defence line ?

No idea. Those parts weren't mentioned in our discussions with them.

I'd recommend contacting your local sales rep and/or Lattice FAE, but in
our case they also didn't know what hit them when ECP4 was cancelled, so
I'm not really sure how much sales reps and FAEs are "in the loop"
nowadays...

cu,
Sean


Article: 156322
Subject: Re: Oberon Operating System + Compiler + Graphic on a Spartan 3 FPGA
From: "rupertlssmith@googlemail.com" <rupertlssmith@googlemail.com>
Date: Wed, 5 Mar 2014 01:04:22 -0800 (PST)
Links: << >>  << T >>  << A >>
On Sunday, March 2, 2014 1:51:06 PM UTC, MGreim wrote:
> http://www.projectoberon.com/
> Its a complete computer including a graphical operating system in a small
> FPGA. 

Very cool. What is the daughter board for? If its just PS/2 mouse and SD card connector, I have some more sophisticated Xilinx eval boards with those already on them. It might not be too hard to get it running on one of them.

Rupert

Article: 156323
Subject: Re: New soft processor core paper publisher?
From: Eric Wallin <tammie.eric@gmail.com>
Date: Wed, 5 Mar 2014 12:05:29 -0800 (PST)
Links: << >>  << T >>  << A >>
Just wanted people to know that my Hive processor now has 8 stacks, somewhat different opcodes, a UART, and I implemented a single thread simulator for it in Excel.

Article: 156324
Subject: Re: Oberon Operating System + Compiler + Graphic on a Spartan 3 FPGA
From: "Robert F. Jarnot" <Robert.F.Jarnot@jpl.nasa.gov>
Date: Wed, 05 Mar 2014 14:49:53 -0800
Links: << >>  << T >>  << A >>
If you manage to get this running on a more modern Xilinx Eval board, 
please let us know -- I would love to try it out.  Everything that I 
have every seen from Niklaus Wirth has been excellent.

On 03/05/2014 01:04 AM, rupertlssmith@googlemail.com wrote:
> On Sunday, March 2, 2014 1:51:06 PM UTC, MGreim wrote:
>> http://www.projectoberon.com/
>> Its a complete computer including a graphical operating system in a small
>> FPGA.
>
> Very cool. What is the daughter board for? If its just PS/2 mouse and SD card connector, I have some more sophisticated Xilinx eval boards with those already on them. It might not be too hard to get it running on one of them.
>
> Rupert
>




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