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Messages from 156600

Article: 156600
Subject: Re: The USB FPGA?
From: langwadt@fonz.dk
Date: Thu, 8 May 2014 08:52:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
Den tirsdag den 6. maj 2014 15.17.25 UTC+2 skrev Allan Herriman:
> On Tue, 06 May 2014 01:12:34 +0100, Theo Markettos wrote:
> 
> 
> 
> > Allan Herriman <allanherriman@hotmail.com> wrote:
> 
> >> I'll second the "USB is crap" comment.
> 
> > 
> 
> > It may be.
> 
> 
> 
> I should clarify.  I've made many boards over the years, using a variety 
> 
> of interface standards.  USB has never struck me as being elegant or 
> 
> efficient.  Its ubiquity, low cost (in volume), a robust connector and 
> 
> power on the same cable as the signals seem to be its biggest plusses.
> 
> 
> 
> The USB physical layer isn't too bad, IMO.  Most of the issues 
> 
> encountered during development are to do with the (software) drivers.  
> 
> That and the reuse of VID / PID values by cheap knock-off clone gizmos 
> 
> that don't quite match the functionality of the original, yet are still 
> 
> expected to work.  (That isn't the fault of the USB standard though.)
> 
> 
> 
> 
> 
> Other posters mentioned the need to purchase an official VID / PID.  The 
> 
> process is too expensive for low volume or hobby projects.
> 
> 
> 
> USB isn't alone there - for example my current employer owns an Ethernet 
> 
> OUI (a big block of MAC addresses) as well as an Ethertype (protocol 
> 
> specifier).  Both of those cost money, but it's a modest once-off cost 
> 
> unlike the annual charge from USB-IF.
> 
> Another thing to consider is that for (e.g.) Ethernet, there are MAC 
> 
> addresses and Ethertypes that you can use for your hobby projects and 
> 
> experimental protocols that won't get you into trouble.  The USB-IF don't 
> 
> provide VID / PID values intended for a similar purpose.  (I understand 
> 
> that if you buy a VID with the purpose of making it "free" they will come 
> 
> after you.)
> 
> 
> 
> > But look at your FPGA.  How do you connect it to your PC?
> 
> > It might have ethernet or PCIe, but almost invariably what comes first
> 
> > is USB.
> 
> 
> 
> It's the opposite for me.  If one of my boards with an FPGA on it is 
> 
> connecting to a PC, it'll be via Ethernet.
> 
> 
> 
> During debugging, I might rarely use USB to connect a JTAG pod to my PC 
> 
> though.
> 
> 
> 
> >> If you must use USB2, I recommend using external PHY parts.
> 
> > 
> 
> > This is the wrong solution
> 
> 
> 
> I respectfully disagree.  One thing that you might like to consider is 
> 
> the I/O required for USB2.  It matches well to the sort of process that 
> 
> you would use for a $2 microcontroller, but not so well to the low 
> 
> voltage I/O that you'd find on a 28nm FPGA.
> 
> There are also analog functions that are needed that you will not find on 
> 
> an FPGA.  FPGA vendors don't like including anything that doesn't have 
> 
> wide applicability.
> 
> 
> 
> OTOH USB3 uses serial signalling that might be a good match for FPGA 
> 
> transceivers.  I haven't looked closely enough at the standard to know 
> 
> for sure, but I suspect there will be problems with idle or sleep (or 
> 
> something like that).  OTOH, FPGA transceivers now have support for the 
> 
> analog signalling for SATA, so if there's enough demand in the 
> 
> marketplace, anything can happen.
> 
> I only put a USB3 controller into a product once - a (then new) NEC / 
> 
> Renesas part that connected to my system using PCIe, so I can't claim to 
> 
> be a USB3 expert.
> 
> 
> 
> I'm also aware that low speed (1.5Mb/s) USB can be bit-bashed in software 
> 
> on a cheap microcontroller.  I don't think it would be compliant with the 
> 
> spec but it does seem to work and is extremely cheap.
> 
> That really sounds like it could easily fit into an FPGA, possibly with 
> 
> the addition of some external level translators.
> 
 

I tried the opencores 12Mbit USB years ago, it was easy enough to get running 

The design was intended to use a phy but I just used a bit of logic an a 
differential input in parallel with two tristate outputs, it is all 3.3V


Doesn't even the latest and greatest FPGAs have some IOs capable of 3.3V? 


480Mbit would be harder, doubt you just do 4x sampling to recover clock
like you can with 12Mbit

> 
> > because those [PHY] chips are never there when you
> 
> > need them.
> 
> 
> 
> I know you're talking about boards, but if you were talking about part 
> 
> availability, that would be a good point.  USB is used in consumer 
> 
> products, and this means that the parts sometimes have short production 
> 
> lives.
> 
> Some years ago I designed a USB2 hub from ST-Ericcson into a product.  
> 
> They had been made obsolete before our second production run.  Now 
> 
> there's an SMSC one in its place.  Since then, SMSC has been bought by 
> 
> Microchip and who knows what's going to happen.
> 
> 
> 
> Those issues can apply to any part on your board though, and aren't 
> 
> unique to USB.  (Has anyone tried to get DDR3 RAM chips when some company 
> 
> in China is manufacturing a large batch of tablets?)
> 
> 
> 
> > If you're doing your own board you can put on one, but many
> 
> > dev boards don't have them.
> 
> 
> 
> I don't use dev boards, so I really shouldn't comment.
> 
> 
> 
> > Why isn't USB2 an FPGA programming option (in addition to JTAG)?
> 
> 
> 
> Substitute the string "PCIe" for "USB2" and you have a question I asked 
> 
> of the local Altera and Xilinx reps about five years ago.
> 
> 
> 
> I'm still waiting for a good solution to that problem that doesn't 
> 
> involve putting a "bootloader" NVM on the board to configure the FPGA 
> 
> just so it can talk PCIe to get the rest of the configuration.
> 
> 
> 
> My guess: USB2 - never.  USB3 - a very remote possibility.
> 
> 
> 
> Regards,
> 
> Allan

-Lasse

Article: 156601
Subject: Re: DDR speed of the XUPV2P Board from Digilent
From: impana <impanaeng@gmail.com>
Date: Thu, 8 May 2014 09:31:10 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Thursday, May 8, 2014 8:10:49 PM UTC+5:30, Gabor wrote:
> impanaeng@gmail.com wrote:
> 
> > sir 
> 
> > i am working on image processing project with deals with implementation of it on xc2vp30
> 
> > device but to to run my code on board i need to set pins AC11 and AD11 can you please tell
> 
>  > can i find the pin on board . i have searched in all data sheets and 
> 
> cannot find the pin location.
> 
> > 
> 
> > thank you in advance
> 
> 
> 
> The schematics are at:
> 
> 
> 
> http://www.xilinx.com/univ/XUPV2P/Documentation/EXTERNAL_REV_C_SCHEMATICS.pdf
> 
> 
> 
> The two pins you mentioned connect to DIP switch SW7.  I'm not
> 
> sure what that has to do with the DDR speed.  Did you expect these
> 
> pins to supply a clock?
> 
> 
> 
> -- 
> 
> Gabor

thank you for your reply

the pins ac11 and ad11 which i have assigned are for reset and to start the block which need to be varied after each clock pulse.so i thought it should be given as data inputs to the board.

Article: 156602
Subject: Re: The USB FPGA?
From: Tim Wescott <tim@seemywebsite.please>
Date: Sat, 10 May 2014 14:22:22 -0500
Links: << >>  << T >>  << A >>
On Sun, 04 May 2014 12:50:28 -0700, Brane2 wrote:

> Dne nedelja, 04. maj 2014 15:02:44 UTC je oseba Theo Markettos napisala:
> 
> <SNIP>
> 
>> But there's an elephant in this room: why is USB on FPGA so hard?
> 
> First, USB is crap.
> 
> Second, you need license from USB consortium in order to get you
> manufacturer ID code spans etc. And IIRC it was on the order of EURO
> 4-5K
> 
> If your inteface was a hard macro or built into a microcontroller, you
> might be able to get an ID or two free of charge from the producer of
> the chip, but without it you have to plunge the dough by yourself if you
> want to sell the thing as USB compatible.
> 
> Ethernet MAC span is both cheaper and less neccessary.

If the customer wants USB, then USB is the right way to go.

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

Article: 156603
Subject: need coding
From: Saqib Saqi <saqi0313saqi@gmail.com>
Date: Sun, 11 May 2014 07:58:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
 TITLE
Implementation of CCSDS based Telemetry Encoder on FPGA
OBJECTIVES
Design and development of CCSDS based Telemetry Encoder on FPGA using VHDL, for satellite applications.
 OUTLINE
The project will comprise of three phases. 
First phase will be the   know how development of CCSDS Packet TM encoding Standard. 
The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.
Finally all the modules will be integrated as a system in the third phase of the project. Complete working TM Encoder will be demonstrated on FPGA kit.
MAJOR EQUIPMENT & SOFTWARE REQUIRED

Hardware: FPGA kit (Spartan-3 or Virtex)
Software: Xilinx ISE


Article: 156604
Subject: Re: need coding
From: Nicolas Matringe <nicolas.matringe@fre.fre>
Date: Sun, 11 May 2014 21:52:58 +0200
Links: << >>  << T >>  << A >>
Le 11/05/2014 16:58, Saqib Saqi a 閏rit :
>   TITLE
> Implementation of CCSDS based Telemetry Encoder on FPGA
> OBJECTIVES
> Design and development of CCSDS based Telemetry Encoder on FPGA using VHDL, for satellite applications.
>   OUTLINE
> The project will comprise of three phases.
> First phase will be the   know how development of CCSDS Packet TM encoding Standard.
> The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.
> Finally all the modules will be integrated as a system in the third phase of the project. Complete working TM Encoder will be demonstrated on FPGA kit.
> MAJOR EQUIPMENT & SOFTWARE REQUIRED
>
> Hardware: FPGA kit (Spartan-3 or Virtex)
> Software: Xilinx ISE
>

Yes, it definitely looks like you need to start coding.

Nicolas

Article: 156605
Subject: Re: need coding
From: =?ISO-8859-1?Q?Adam_G=F3rski?= <gorskiamalpa@wpkropkapl>
Date: Mon, 12 May 2014 11:03:30 +0200
Links: << >>  << T >>  << A >>
W dniu 2014-05-11 16:58, Saqib Saqi pisze:
>   TITLE
> Implementation of CCSDS based Telemetry Encoder on FPGA
> OBJECTIVES
> Design and development of CCSDS based Telemetry Encoder on FPGA using VHDL, for satellite applications.
>   OUTLINE
> The project will comprise of three phases.
> First phase will be the   know how development of CCSDS Packet TM encoding Standard.
> The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.
> Finally all the modules will be integrated as a system in the third phase of the project. Complete working TM Encoder will be demonstrated on FPGA kit.
> MAJOR EQUIPMENT & SOFTWARE REQUIRED
>
> Hardware: FPGA kit (Spartan-3 or Virtex)
> Software: Xilinx ISE
>

Interesting project. I could join in if you can pay ....

BR

Adam

Article: 156606
Subject: Re: need coding
From: Saqib Saqi <saqi0313saqi@gmail.com>
Date: Mon, 12 May 2014 05:48:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Monday, May 12, 2014 2:03:30 PM UTC+5, Adam G=F3rski wrote:
> W dniu 2014-05-11 16:58, Saqib Saqi pisze:
>=20
> >   TITLE
>=20
> > Implementation of CCSDS based Telemetry Encoder on FPGA
>=20
> > OBJECTIVES
>=20
> > Design and development of CCSDS based Telemetry Encoder on FPGA using V=
HDL, for satellite applications.
>=20
> >   OUTLINE
>=20
> > The project will comprise of three phases.
>=20
> > First phase will be the   know how development of CCSDS Packet TM encod=
ing Standard.
>=20
> > The second phase will be the implementation of all layers of standard o=
n FPGA using the VHDL language. Each layer will be implemented as a separat=
e module and simulation will be performed.
>=20
> > Finally all the modules will be integrated as a system in the third pha=
se of the project. Complete working TM Encoder will be demonstrated on FPGA=
 kit.
>=20
> > MAJOR EQUIPMENT & SOFTWARE REQUIRED
>=20
> >
>=20
> > Hardware: FPGA kit (Spartan-3 or Virtex)
>=20
> > Software: Xilinx ISE
>=20
> >
>=20
>=20
>=20
> Interesting project. I could join in if you can pay ....
>=20
>=20
>=20
> BR
>=20
>=20
>=20
> Adam

yes i can u can email me muhammadsaqib10cs52@hotmail.com

or FB account on Search type=20
saqi0313saqi@yahoo.com you  can add me=20


i'm w8ing for ur resposnse

Article: 156607
Subject: Re: need coding
From: Saqib Saqi <saqi0313saqi@gmail.com>
Date: Mon, 12 May 2014 05:50:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Monday, May 12, 2014 12:52:58 AM UTC+5, Nicolas Matringe wrote:
> Le 11/05/2014 16:58, Saqib Saqi a =EF=BF=BDcrit :
>=20
> >   TITLE
>=20
> > Implementation of CCSDS based Telemetry Encoder on FPGA
>=20
> > OBJECTIVES
>=20
> > Design and development of CCSDS based Telemetry Encoder on FPGA using V=
HDL, for satellite applications.
>=20
> >   OUTLINE
>=20
> > The project will comprise of three phases.
>=20
> > First phase will be the   know how development of CCSDS Packet TM encod=
ing Standard.
>=20
> > The second phase will be the implementation of all layers of standard o=
n FPGA using the VHDL language. Each layer will be implemented as a separat=
e module and simulation will be performed.
>=20
> > Finally all the modules will be integrated as a system in the third pha=
se of the project. Complete working TM Encoder will be demonstrated on FPGA=
 kit.
>=20
> > MAJOR EQUIPMENT & SOFTWARE REQUIRED
>=20
> >
>=20
> > Hardware: FPGA kit (Spartan-3 or Virtex)
>=20
> > Software: Xilinx ISE
>=20
> >
>=20
>=20
>=20
> Yes, it definitely looks like you need to start coding.
>=20
>=20
>=20
> Nicolas

kindly help me in packet telemetry encoder  ...i need to encode all the enc=
oder or just telemetry encoder ...help me if u can

Article: 156608
Subject: Re: need coding
From: Tim Wescott <tim@seemywebsite.really>
Date: Mon, 12 May 2014 16:25:29 -0500
Links: << >>  << T >>  << A >>
On Sun, 11 May 2014 07:58:17 -0700, Saqib Saqi wrote:

> TITLE Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
> Design and development of CCSDS based Telemetry Encoder on FPGA using
> VHDL, for satellite applications.
>  OUTLINE
> The project will comprise of three phases.
> First phase will be the   know how development of CCSDS Packet TM
> encoding Standard.
> The second phase will be the implementation of all layers of standard on
> FPGA using the VHDL language. Each layer will be implemented as a
> separate module and simulation will be performed.
> Finally all the modules will be integrated as a system in the third
> phase of the project. Complete working TM Encoder will be demonstrated
> on FPGA kit.
> MAJOR EQUIPMENT & SOFTWARE REQUIRED
> 
> Hardware: FPGA kit (Spartan-3 or Virtex)
> Software: Xilinx ISE

University final project?

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com


Article: 156609
Subject: Re: need coding
From: Tim Wescott <tim@seemywebsite.really>
Date: Mon, 12 May 2014 16:26:46 -0500
Links: << >>  << T >>  << A >>
On Mon, 12 May 2014 11:03:30 +0200, Adam G贸rski wrote:

> W dniu 2014-05-11 16:58, Saqib Saqi pisze:
>>   TITLE
>> Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
>> Design and development of CCSDS based Telemetry Encoder on FPGA using
>> VHDL, for satellite applications.
>>   OUTLINE
>> The project will comprise of three phases.
>> First phase will be the   know how development of CCSDS Packet TM
>> encoding Standard.
>> The second phase will be the implementation of all layers of standard
>> on FPGA using the VHDL language. Each layer will be implemented as a
>> separate module and simulation will be performed.
>> Finally all the modules will be integrated as a system in the third
>> phase of the project. Complete working TM Encoder will be demonstrated
>> on FPGA kit.
>> MAJOR EQUIPMENT & SOFTWARE REQUIRED
>>
>> Hardware: FPGA kit (Spartan-3 or Virtex)
>> Software: Xilinx ISE
>>
>>
> Interesting project. I could join in if you can pay ....
> 
> BR
> 
> Adam

If he's offering to pay you to do his senior project, consider that 
you'll be helping to graduate one more incompetent manager.

Wouldn't you rather he was one department over, in sales or something?

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com


Article: 156610
Subject: Re: need coding
From: =?UTF-8?B?QWRhbSBHw7Nyc2tp?= <gorskiamalpa@wpkropkapl>
Date: Tue, 13 May 2014 10:47:21 +0200
Links: << >>  << T >>  << A >>
W dniu 2014-05-12 23:26, Tim Wescott pisze:
> On Mon, 12 May 2014 11:03:30 +0200, Adam G贸rski wrote:
>
>> W dniu 2014-05-11 16:58, Saqib Saqi pisze:
>>>    TITLE
>>> Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
>>> Design and development of CCSDS based Telemetry Encoder on FPGA using
>>> VHDL, for satellite applications.
>>>    OUTLINE
>>> The project will comprise of three phases.
>>> First phase will be the   know how development of CCSDS Packet TM
>>> encoding Standard.
>>> The second phase will be the implementation of all layers of standard
>>> on FPGA using the VHDL language. Each layer will be implemented as a
>>> separate module and simulation will be performed.
>>> Finally all the modules will be integrated as a system in the third
>>> phase of the project. Complete working TM Encoder will be demonstrated
>>> on FPGA kit.
>>> MAJOR EQUIPMENT & SOFTWARE REQUIRED
>>>
>>> Hardware: FPGA kit (Spartan-3 or Virtex)
>>> Software: Xilinx ISE
>>>
>>>
>> Interesting project. I could join in if you can pay ....
>>
>> BR
>>
>> Adam
>
> If he's offering to pay you to do his senior project, consider that
> you'll be helping to graduate one more incompetent manager.
>
> Wouldn't you rather he was one department over, in sales or something?
>

If this is any kind of school project - I'm not interested ( no way). 
I'm not going to take it for 100$. My time is much more expensive.
If this is space application for serius client ( like NASA or something 
) and is interesting , "beam me up Scotty".


BR

Adam

Article: 156611
Subject: Re: need coding
From: HT-Lab <hans64@htminuslab.com>
Date: Tue, 13 May 2014 10:26:25 +0100
Links: << >>  << T >>  << A >>
On 13/05/2014 09:47, Adam G贸rski wrote:
> W dniu 2014-05-12 23:26, Tim Wescott pisze:
>> On Mon, 12 May 2014 11:03:30 +0200, Adam G贸rski wrote:
>>
>>> W dniu 2014-05-11 16:58, Saqib Saqi pisze:
>>>>    TITLE
>>>> Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
>>>> Design and development of CCSDS based Telemetry Encoder on FPGA using
>>>> VHDL, for satellite applications.
>>>>    OUTLINE
>>>> The project will comprise of three phases.
>>>> First phase will be the   know how development of CCSDS Packet TM
>>>> encoding Standard.
>>>> The second phase will be the implementation of all layers of standard
>>>> on FPGA using the VHDL language. Each layer will be implemented as a
>>>> separate module and simulation will be performed.
>>>> Finally all the modules will be integrated as a system in the third
>>>> phase of the project. Complete working TM Encoder will be demonstrated
>>>> on FPGA kit.
>>>> MAJOR EQUIPMENT & SOFTWARE REQUIRED
>>>>
>>>> Hardware: FPGA kit (Spartan-3 or Virtex)
>>>> Software: Xilinx ISE
>>>>
>>>>
>>> Interesting project. I could join in if you can pay ....
>>>
>>> BR
>>>
>>> Adam
>>
>> If he's offering to pay you to do his senior project, consider that
>> you'll be helping to graduate one more incompetent manager.
>>
>> Wouldn't you rather he was one department over, in sales or something?
>>
>
> If this is any kind of school project - I'm not interested ( no way).
> I'm not going to take it for 100$. My time is much more expensive.
> If this is space application for serius client ( like NASA or something
> ) and is interesting , "beam me up Scotty".
>
I am pretty sure Nasa already has in-house CCSDS cores, for any other 
smaller space company I believe they can get the ESA CCSDS VHDL design 
(for free?) under a license agreement.

I also believe (but haven't checked as I no longer work in the space 
industry) that you can get most CCSDS modules (turbo codecs excluded?) 
from Gaisler research.

Hans
www.ht-lab.com



>
> BR
>
> Adam


Article: 156612
Subject: Re: need coding
From: =?UTF-8?B?QWRhbSBHw7Nyc2tp?= <gorskiamalpa@wpkropkapl>
Date: Tue, 13 May 2014 13:32:55 +0200
Links: << >>  << T >>  << A >>
W dniu 2014-05-13 11:26, HT-Lab pisze:
> On 13/05/2014 09:47, Adam G贸rski wrote:
>> W dniu 2014-05-12 23:26, Tim Wescott pisze:
>>> On Mon, 12 May 2014 11:03:30 +0200, Adam G贸rski wrote:
>>>
>>>> W dniu 2014-05-11 16:58, Saqib Saqi pisze:
>>>>>    TITLE
>>>>> Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
>>>>> Design and development of CCSDS based Telemetry Encoder on FPGA using
>>>>> VHDL, for satellite applications.
>>>>>    OUTLINE
>>>>> The project will comprise of three phases.
>>>>> First phase will be the   know how development of CCSDS Packet TM
>>>>> encoding Standard.
>>>>> The second phase will be the implementation of all layers of standard
>>>>> on FPGA using the VHDL language. Each layer will be implemented as a
>>>>> separate module and simulation will be performed.
>>>>> Finally all the modules will be integrated as a system in the third
>>>>> phase of the project. Complete working TM Encoder will be demonstrated
>>>>> on FPGA kit.
>>>>> MAJOR EQUIPMENT & SOFTWARE REQUIRED
>>>>>
>>>>> Hardware: FPGA kit (Spartan-3 or Virtex)
>>>>> Software: Xilinx ISE
>>>>>
>>>>>
>>>> Interesting project. I could join in if you can pay ....
>>>>
>>>> BR
>>>>
>>>> Adam
>>>
>>> If he's offering to pay you to do his senior project, consider that
>>> you'll be helping to graduate one more incompetent manager.
>>>
>>> Wouldn't you rather he was one department over, in sales or something?
>>>
>>
>> If this is any kind of school project - I'm not interested ( no way).
>> I'm not going to take it for 100$. My time is much more expensive.
>> If this is space application for serius client ( like NASA or something
>> ) and is interesting , "beam me up Scotty".
>>
> I am pretty sure Nasa already has in-house CCSDS cores, for any other
> smaller space company I believe they can get the ESA CCSDS VHDL design
> (for free?) under a license agreement.
>
> I also believe (but haven't checked as I no longer work in the space
> industry) that you can get most CCSDS modules (turbo codecs excluded?)
> from Gaisler research.

I'm sure it is true :)

Adam

Article: 156613
Subject: Re: need coding
From: Saqib Saqi <saqi0313saqi@gmail.com>
Date: Tue, 13 May 2014 07:40:56 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Tuesday, May 13, 2014 2:26:25 PM UTC+5, HT-Lab wrote:
> On 13/05/2014 09:47, Adam G=F3rski wrote:
>=20
> > W dniu 2014-05-12 23:26, Tim Wescott pisze:
>=20
> >> On Mon, 12 May 2014 11:03:30 +0200, Adam G=F3rski wrote:
>=20
> >>
>=20
> >>> W dniu 2014-05-11 16:58, Saqib Saqi pisze:
>=20
> >>>>    TITLE
>=20
> >>>> Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
>=20
> >>>> Design and development of CCSDS based Telemetry Encoder on FPGA usin=
g
>=20
> >>>> VHDL, for satellite applications.
>=20
> >>>>    OUTLINE
>=20
> >>>> The project will comprise of three phases.
>=20
> >>>> First phase will be the   know how development of CCSDS Packet TM
>=20
> >>>> encoding Standard.
>=20
> >>>> The second phase will be the implementation of all layers of standar=
d
>=20
> >>>> on FPGA using the VHDL language. Each layer will be implemented as a
>=20
> >>>> separate module and simulation will be performed.
>=20
> >>>> Finally all the modules will be integrated as a system in the third
>=20
> >>>> phase of the project. Complete working TM Encoder will be demonstrat=
ed
>=20
> >>>> on FPGA kit.
>=20
> >>>> MAJOR EQUIPMENT & SOFTWARE REQUIRED
>=20
> >>>>
>=20
> >>>> Hardware: FPGA kit (Spartan-3 or Virtex)
>=20
> >>>> Software: Xilinx ISE
>=20
> >>>>
>=20
> >>>>
>=20
> >>> Interesting project. I could join in if you can pay ....
>=20
> >>>
>=20
> >>> BR
>=20
> >>>
>=20
> >>> Adam
>=20
> >>
>=20
> >> If he's offering to pay you to do his senior project, consider that
>=20
> >> you'll be helping to graduate one more incompetent manager.
>=20
> >>
>=20
> >> Wouldn't you rather he was one department over, in sales or something?
>=20
> >>
>=20
> >
>=20
> > If this is any kind of school project - I'm not interested ( no way).
>=20
> > I'm not going to take it for 100$. My time is much more expensive.
>=20
> > If this is space application for serius client ( like NASA or something
>=20
> > ) and is interesting , "beam me up Scotty".
>=20
> >
>=20
> I am pretty sure Nasa already has in-house CCSDS cores, for any other=20
>=20
> smaller space company I believe they can get the ESA CCSDS VHDL design=20
>=20
> (for free?) under a license agreement.
>=20
>=20
>=20
> I also believe (but haven't checked as I no longer work in the space=20
>=20
> industry) that you can get most CCSDS modules (turbo codecs excluded?)=20
>=20
> from Gaisler research.
>=20
>=20
>=20
> Hans
>=20
> www.ht-lab.com
>=20
>=20
>=20
>=20
>=20







>=20
>=20
> >
>=20
> > BR
>=20
> >
>=20
> > Adam

i'm university student and i want me to do this project

Article: 156614
Subject: Re: need coding
From: Saqib Saqi <saqi0313saqi@gmail.com>
Date: Tue, 13 May 2014 08:18:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Tuesday, May 13, 2014 1:47:21 PM UTC+5, Adam G=F3rski wrote:
> W dniu 2014-05-12 23:26, Tim Wescott pisze:
>=20
> > On Mon, 12 May 2014 11:03:30 +0200, Adam G=F3rski wrote:
>=20
> >
>=20
> >> W dniu 2014-05-11 16:58, Saqib Saqi pisze:
>=20
> >>>    TITLE
>=20
> >>> Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
>=20
> >>> Design and development of CCSDS based Telemetry Encoder on FPGA using
>=20
> >>> VHDL, for satellite applications.
>=20
> >>>    OUTLINE
>=20
> >>> The project will comprise of three phases.
>=20
> >>> First phase will be the   know how development of CCSDS Packet TM
>=20
> >>> encoding Standard.
>=20
> >>> The second phase will be the implementation of all layers of standard
>=20
> >>> on FPGA using the VHDL language. Each layer will be implemented as a
>=20
> >>> separate module and simulation will be performed.
>=20
> >>> Finally all the modules will be integrated as a system in the third
>=20
> >>> phase of the project. Complete working TM Encoder will be demonstrate=
d
>=20
> >>> on FPGA kit.
>=20
> >>> MAJOR EQUIPMENT & SOFTWARE REQUIRED
>=20
> >>>
>=20
> >>> Hardware: FPGA kit (Spartan-3 or Virtex)
>=20
> >>> Software: Xilinx ISE
>=20
> >>>
>=20
> >>>
>=20
> >> Interesting project. I could join in if you can pay ....
>=20
> >>
>=20
> >> BR
>=20
> >>
>=20
> >> Adam
>=20
> >
>=20
> > If he's offering to pay you to do his senior project, consider that
>=20
> > you'll be helping to graduate one more incompetent manager.
>=20
> >
>=20
> > Wouldn't you rather he was one department over, in sales or something?
>=20
> >
>=20
>=20
>=20
> If this is any kind of school project - I'm not interested ( no way).=20
>=20
> I'm not going to take it for 100$. My time is much more expensive.
>=20
> If this is space application for serius client ( like NASA or something=
=20
>=20
> ) and is interesting , "beam me up Scotty".
>=20
>=20
>=20
>=20
>=20
> BR
>=20
>=20
>=20
> Adam

if u have command on this ..then i can pay ..this is my univ.level project
if u can help this is very humble kindness for this thing

Article: 156615
Subject: virtex4 software reset problem.
From: Jasim Khan <khan990@gmail.com>
Date: Tue, 13 May 2014 14:39:47 -0700 (PDT)
Links: << >>  << T >>  << A >>
HI 


I made a small amendment to a tutorial I found online "http://www.fpgadeveloper.com/2008/02/integrating-vhdl-design-into-peripheral-2.html" (which worked fine), but it is not working as one could expect. Can anyone tell me why?

Please see my C code area with asterisk to find the problem.
I am guessing the problem is with software reset. If yes, How do I fix this?


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity multiplier is
  port(
    clk : in std_logic;
	rst : in std_logic;
    a   : in std_logic_vector(15 downto 0);
    b   : in std_logic_vector(15 downto 0);
    p   : out std_logic_vector(31 downto 0)
  );
end multiplier;

architecture IMP of multiplier is

begin
  process (clk, rst)
  begin
	if(rst = '1') then
		p <= B"10101010101010101010101010101010";
    elsif (clk'event and clk = '1') then
      p <= unsigned(a) * unsigned(b);
    end if;
  end process;
end IMP;






#include "xmk.h"
#include "sys/init.h"
#include "platform.h"
#include "xparameters.h"
#include "xbasic_types.h"
#include "xstatus.h"
#include "testplb_02.h"
#include <stdio.h>

Xuint32 *baseaddr_p = (Xuint32 *)XPAR_TESTPLB_02_0_BASEADDR;

int main()
{
	Xuint32 baseaddr;
	Xuint32 DataIN = 0;
	Xuint32 DataOUT = 0;

    init_platform();

	// Check that the peripheral exists
	XASSERT_NONVOID(baseaddr_p != XNULL);
	baseaddr = (Xuint32) baseaddr_p;

	TESTPLB_02_mReset(baseaddr);

	// Reset read and write packet FIFOs to initial state
	TESTPLB_02_mResetWriteFIFO(baseaddr);
	TESTPLB_02_mResetReadFIFO(baseaddr);


	DataOUT = TESTPLB_02_mReadFromFIFO(baseaddr, 0);
//**************************************
// DataOUT is 0, where as it should be B"101010...." as in the reset.
// So in a nut shell, FPGA doesnot reset correctly.
// Rest of the code works fine.
//***************************************
	DataIN = 131074;		//2*2
	TESTPLB_02_mWriteToFIFO(baseaddr, 0, DataIN);

	DataOUT = TESTPLB_02_mReadFromFIFO(baseaddr, 0);

	if(DataOUT != 4)
	{
		DataOUT = DataOUT;
	}

	DataIN = 327685;		//5*5
	TESTPLB_02_mWriteToFIFO(baseaddr, 0, DataIN);

	DataOUT = TESTPLB_02_mReadFromFIFO(baseaddr, 0);

	if(DataOUT != 25)
	{
		DataOUT = DataOUT;
	}

	DataIN = 524296;		//8*8
	TESTPLB_02_mWriteToFIFO(baseaddr, 0, DataIN);

	DataOUT = TESTPLB_02_mReadFromFIFO(baseaddr, 0);

	if(DataOUT != 64)
	{
		DataOUT = DataOUT;
	}

	DataIN = 524295;		//7*8
	TESTPLB_02_mWriteToFIFO(baseaddr, 0, DataIN);

	DataOUT = TESTPLB_02_mReadFromFIFO(baseaddr, 0);

	if(DataOUT != 56)
	{
		DataOUT = DataOUT;
	}


	// Stay in an infinite loop
	while(1){
	}


	// Reset the read and write FIFOs
	TESTPLB_02_mResetWriteFIFO(baseaddr);
	TESTPLB_02_mResetReadFIFO(baseaddr);


    return 0;
}

Article: 156616
Subject: Re: need coding
From: Tim Wescott <tim@seemywebsite.really>
Date: Tue, 13 May 2014 17:07:40 -0500
Links: << >>  << T >>  << A >>
On Tue, 13 May 2014 08:18:51 -0700, Saqib Saqi wrote:

> if u have command on this ..then i can pay ..this is my univ.level
> project if u can help this is very humble kindness for this thing

But here's the thing: university projects are assigned assuming that YOU 
will do the work.  If you pay someone else to do the work and pass it off 
as yours, then that's cheating.  You won't learn how to be a productive 
engineer by cheating (engineers actually have to use the knowledge they 
gain at school), you'll just get a piece of paper that says you are.

When you try to get an actual job and are asked to DO the things that you 
should have learned getting your degree, you'll fail.  Then you'll either 
get fired, or you'll get made into a manager.  You won't be a good 
manager -- you'll be a horrid manager.  You'll be the kind of manager who 
cheats his boss (which makes his employees look bad), and cheats his 
employees (which makes them look bad), and generally makes life hell for 
every honest person within his event horizon.

I think I'm speaking for most of us here when I say that we take a very 
dim view of cheating.  Even those of us who are amoral enough to not care 
about the actual cheating don't want to have to work under the kind of 
manager who cheats his way through school because he can't or won't do 
engineering.  Since engineers tend to think in the long term, that means 
that we're not interested in a little bit of money today to foster a 
worse work environment for the rest of your life.

Now, if you want to actually DO the work, and all you want is some help 
to understand HOW to do the work (because god knows, not every professor 
is created equal, and some of them couldn't teach their way out of a 
paper bag), then by all means change your approach to "I've been assigned 
this project, and I need help figuring out how to get it done".

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com


Article: 156617
Subject: Re: need coding
From: =?ISO-8859-1?Q?Adam_G=F3rski?= <gorskiamalpa@wpkropkapl>
Date: Wed, 14 May 2014 11:50:02 +0200
Links: << >>  << T >>  << A >>
W dniu 2014-05-13 17:18, Saqib Saqi pisze:
> On Tuesday, May 13, 2014 1:47:21 PM UTC+5, Adam G髍ski wrote:
>> W dniu 2014-05-12 23:26, Tim Wescott pisze:
>>
>>> On Mon, 12 May 2014 11:03:30 +0200, Adam G髍ski wrote:
>>
>>>
>>
>>>> W dniu 2014-05-11 16:58, Saqib Saqi pisze:
>>
>>>>>     TITLE
>>
>>>>> Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
>>
>>>>> Design and development of CCSDS based Telemetry Encoder on FPGA using
>>
>>>>> VHDL, for satellite applications.
>>
>>>>>     OUTLINE
>>
>>>>> The project will comprise of three phases.
>>
>>>>> First phase will be the   know how development of CCSDS Packet TM
>>
>>>>> encoding Standard.
>>
>>>>> The second phase will be the implementation of all layers of standard
>>
>>>>> on FPGA using the VHDL language. Each layer will be implemented as a
>>
>>>>> separate module and simulation will be performed.
>>
>>>>> Finally all the modules will be integrated as a system in the third
>>
>>>>> phase of the project. Complete working TM Encoder will be demonstrated
>>
>>>>> on FPGA kit.
>>
>>>>> MAJOR EQUIPMENT & SOFTWARE REQUIRED
>>
>>>>>
>>
>>>>> Hardware: FPGA kit (Spartan-3 or Virtex)
>>
>>>>> Software: Xilinx ISE
>>
>>>>>
>>
>>>>>
>>
>>>> Interesting project. I could join in if you can pay ....
>>
>>>>
>>
>>>> BR
>>
>>>>
>>
>>>> Adam
>>
>>>
>>
>>> If he's offering to pay you to do his senior project, consider that
>>
>>> you'll be helping to graduate one more incompetent manager.
>>
>>>
>>
>>> Wouldn't you rather he was one department over, in sales or something?
>>
>>>
>>
>>
>>
>> If this is any kind of school project - I'm not interested ( no way).
>>
>> I'm not going to take it for 100$. My time is much more expensive.
>>
>> If this is space application for serius client ( like NASA or something
>>
>> ) and is interesting , "beam me up Scotty".
>>
>>
>>
>>
>>
>> BR
>>
>>
>>
>> Adam
>
> if u have command on this ..then i can pay ..this is my univ.level project
> if u can help this is very humble kindness for this thing
>

So , sorry then. I can help you in some difficult points if you give me 
right questions.
If you cannot even start with this project - it is not for you.
I completely agree with Tim. You should start with information what kind 
of project is it.


BR

Adam

Article: 156618
Subject: Re: need coding
From: Saqib Saqi <saqi0313saqi@gmail.com>
Date: Wed, 14 May 2014 06:37:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Wednesday, May 14, 2014 2:50:02 PM UTC+5, Adam G=F3rski wrote:
> W dniu 2014-05-13 17:18, Saqib Saqi pisze:
>=20
> > On Tuesday, May 13, 2014 1:47:21 PM UTC+5, Adam G=EF=BF 1/2 rski wrote:
>=20
> >> W dniu 2014-05-12 23:26, Tim Wescott pisze:
>=20
> >>
>=20
> >>> On Mon, 12 May 2014 11:03:30 +0200, Adam G=EF=BF 1/2 rski wrote:
>=20
> >>
>=20
> >>>
>=20
> >>
>=20
> >>>> W dniu 2014-05-11 16:58, Saqib Saqi pisze:
>=20
> >>
>=20
> >>>>>     TITLE
>=20
> >>
>=20
> >>>>> Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
>=20
> >>
>=20
> >>>>> Design and development of CCSDS based Telemetry Encoder on FPGA usi=
ng
>=20
> >>
>=20
> >>>>> VHDL, for satellite applications.
>=20
> >>
>=20
> >>>>>     OUTLINE
>=20
> >>
>=20
> >>>>> The project will comprise of three phases.
>=20
> >>
>=20
> >>>>> First phase will be the   know how development of CCSDS Packet TM
>=20
> >>
>=20
> >>>>> encoding Standard.
>=20
> >>
>=20
> >>>>> The second phase will be the implementation of all layers of standa=
rd
>=20
> >>
>=20
> >>>>> on FPGA using the VHDL language. Each layer will be implemented as =
a
>=20
> >>
>=20
> >>>>> separate module and simulation will be performed.
>=20
> >>
>=20
> >>>>> Finally all the modules will be integrated as a system in the third
>=20
> >>
>=20
> >>>>> phase of the project. Complete working TM Encoder will be demonstra=
ted
>=20
> >>
>=20
> >>>>> on FPGA kit.
>=20
> >>
>=20
> >>>>> MAJOR EQUIPMENT & SOFTWARE REQUIRED
>=20
> >>
>=20
> >>>>>
>=20
> >>
>=20
> >>>>> Hardware: FPGA kit (Spartan-3 or Virtex)
>=20
> >>
>=20
> >>>>> Software: Xilinx ISE
>=20
> >>
>=20
> >>>>>
>=20
> >>
>=20
> >>>>>
>=20
> >>
>=20
> >>>> Interesting project. I could join in if you can pay ....
>=20
> >>
>=20
> >>>>
>=20
> >>
>=20
> >>>> BR
>=20
> >>
>=20
> >>>>
>=20
> >>
>=20
> >>>> Adam
>=20
> >>
>=20
> >>>
>=20
> >>
>=20
> >>> If he's offering to pay you to do his senior project, consider that
>=20
> >>
>=20
> >>> you'll be helping to graduate one more incompetent manager.
>=20
> >>
>=20
> >>>
>=20
> >>
>=20
> >>> Wouldn't you rather he was one department over, in sales or something=
?
>=20
> >>
>=20
> >>>
>=20
> >>
>=20
> >>
>=20
> >>
>=20
> >> If this is any kind of school project - I'm not interested ( no way).
>=20
> >>
>=20
> >> I'm not going to take it for 100$. My time is much more expensive.
>=20
> >>
>=20
> >> If this is space application for serius client ( like NASA or somethin=
g
>=20
> >>
>=20
> >> ) and is interesting , "beam me up Scotty".
>=20
> >>
>=20
> >>
>=20
> >>
>=20
> >>
>=20
> >>
>=20
> >> BR
>=20
> >>
>=20
> >>
>=20
> >>
>=20
> >> Adam
>=20
> >
>=20
> > if u have command on this ..then i can pay ..this is my univ.level proj=
ect
>=20
> > if u can help this is very humble kindness for this thing
>=20
> >
>=20
>=20
>=20
> So , sorry then. I can help you in some difficult points if you give me=
=20
>=20
> right questions.
>=20
> If you cannot even start with this project - it is not for you.
>=20
> I completely agree with Tim. You should start with information what kind=
=20
>=20
> of project is it.
>=20
>=20
>=20
>=20
>=20
> BR
>=20
>=20
>=20
> Adam

@Tim @Adam=20
then i need some help regarding my project=20
the help is that ....
we just encode telemetry or on the Other Hand=20
Packet telemetry encoder listed 8 thing ....

The Packet Telemetry Encoder (PTME) VHDL model comprises several encoders a=
nd modulators implementing the Consultative Committee for Space Data System=
s (CCSDS) recommendations and the European Space Agency (ESA) Procedures, S=
tandards and  Specifications (PSS) for telemetry and channel coding. The Pa=
cket Telemetry Encoder (PTME) VHDL model comprises the following:
* Telemetry Encoder (TME)
* Reed-Solomon Encoder (RSE)
* Turbo Encoder (TE)
* Pseudo-Randomiser (PSR)
* Non-Return-to-Zero Mark encoder (NRZ)
* Convolutional Encoder (CE)
* Split-Phase Level modulator (SP)
* Clock Divider (CD)
we encode just Telemetry encoder or=20
all of the other encoder=20
i'm confuse

Article: 156619
Subject: Undriven outputs of a module in Quartus II Synthesis
From: Ang Zhi Ping <angzhiping@gmail.com>
Date: Wed, 14 May 2014 21:37:50 +0800
Links: << >>  << T >>  << A >>
I have a module which does not drive certain output ports for certain
operation modes, and that simulates fine in Modelsim. How would Quartus
II (or any other synthesis software) handle undriven ports? Will it
synthesize into something which may cause logic to behave in an
unpredictable manner?

---
This email is free from viruses and malware because avast! Antivirus protection is active.
http://www.avast.com


Article: 156620
Subject: Re: Undriven outputs of a module in Quartus II Synthesis
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 14 May 2014 14:15:15 +0000 (UTC)
Links: << >>  << T >>  << A >>
Ang Zhi Ping <angzhiping@gmail.com> wrote:

> I have a module which does not drive certain output ports for certain
> operation modes, and that simulates fine in Modelsim. How would Quartus
> II (or any other synthesis software) handle undriven ports? Will it
> synthesize into something which may cause logic to behave in an
> unpredictable manner?

If you drive them Z, the outputs should tristate, if X then they
will be either 0 or 1, whatever the synthesis finds easier.

What to you mean by "unpredictable"?

-- glen

Article: 156621
Subject: Re: Undriven outputs of a module in Quartus II Synthesis
From: "mnentwig" <24789@embeddedrelated>
Date: Wed, 14 May 2014 09:16:19 -0500
Links: << >>  << T >>  << A >>
Hi,

two constructs come to mind, "undefined" and "tri-state".
For the first, I tell the synthesis tool "do what you like, I don't care".
During operation, the logic value can be anything. Assign "undefined"
explicitly to enable better optimizations.

The other one is "tri-state". For an off-chip connection, you can tell the
output driver "go into high-impedance state", possibly with some
pullup-/down resistor. This is hardware-dependent. 
The simulator can put "tri-state" on any wire but the synthesis tool will
not allow you to create floating nodes within the FPGA, at least not
physically.

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 156622
Subject: Re: need coding
From: Tom Gardner <spamjunk@blueyonder.co.uk>
Date: Wed, 14 May 2014 16:16:32 +0100
Links: << >>  << T >>  << A >>
On 14/05/14 14:37, Saqib Saqi wrote:
> we encode just Telemetry encoder or
> all of the other encoder
> i'm confuse

Only your teacher can resolve that confusion. Ask him
what he expects you to complete in order that he will
give you full marks.

Article: 156623
Subject: Re: Undriven outputs of a module in Quartus II Synthesis
From: KJ <kkjennings@sbcglobal.net>
Date: Wed, 14 May 2014 08:50:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Wednesday, May 14, 2014 9:37:50 AM UTC-4, Ang Zhi Ping wrote:
> I have a module which does not drive certain output ports for certain
> operation modes, and that simulates fine in Modelsim. How would Quartus
> II (or any other synthesis software) handle undriven ports? 

Run Quartus and you will find out.  What you will see in the synthesis report is that those undefined outputs will be driven to 0.

> Will it synthesize into something which may cause logic to behave in an
> unpredictable manner?
> 

No, it will behave as if you had explicitly set the outputs to 0.

Kevin Jennings

Article: 156624
Subject: Re: need coding
From: Tim Wescott <tim@seemywebsite.really>
Date: Wed, 14 May 2014 22:09:00 -0500
Links: << >>  << T >>  << A >>
On Wed, 14 May 2014 06:37:19 -0700, Saqib Saqi wrote:

>>> ethics discussion snipped <<<

> @Tim @Adam then i need some help regarding my project the help is that
> ....
> we just encode telemetry or on the Other Hand Packet telemetry encoder
> listed 8 thing ....
> 
> The Packet Telemetry Encoder (PTME) VHDL model comprises several
> encoders and modulators implementing the Consultative Committee for
> Space Data Systems (CCSDS) recommendations and the European Space Agency
> (ESA) Procedures, Standards and  Specifications (PSS) for telemetry and
> channel coding. The Packet Telemetry Encoder (PTME) VHDL model comprises
> the following:
> * Telemetry Encoder (TME)
> * Reed-Solomon Encoder (RSE)
> * Turbo Encoder (TE)
> * Pseudo-Randomiser (PSR)
> * Non-Return-to-Zero Mark encoder (NRZ)
> * Convolutional Encoder (CE)
> * Split-Phase Level modulator (SP)
> * Clock Divider (CD)
> we encode just Telemetry encoder or all of the other encoder i'm confuse

Like Tom said, you need to ask your prof.  This is a pretty good 
simulation of engineering in the real world: your boss, or a customer, or 
Sales, or whoever, will ask you to do something in general terms that 
turn out to be ambiguous.  You need to deliver something very specific, 
so it's your job to take that English-language (or whatever language) and 
translate it into Engineering-English.

You want to do this BEFORE you've spent much time on actual design -- 
because any time spent designing the wrong thing is just time wasted.

The whole list of things there would be a pretty daunting task for one 
student to undertake as a project.  It's not totally undoable, but I 
would hope that your prof is thinking more along the lines of having you 
build a piece of it, either to go onto something that someone else has 
done, or to serve as a foundation for someone else's work.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com




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2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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