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On Friday, August 5, 2016 at 12:04:52 AM UTC+3, rickman wrote: > > I know that the simulators are intentionally speed crippled to encourage > users to upgrade to paid versions. I don't know if they do the same > thing with synthesis tools or not. > > -- > > Rick C We are talking about X&A own integrated synthesis. I don't believe that there is a difference between "paid" and "free" tools except that "free" tools can't target certain devices. Anyway, all my Quartus measurements were "paid". Vivado measurements were sort of paid too - license came due to voucher that was attached to Zync Eval. board.Article: 159126
On 8/7/2016 10:20 AM, already5chosen@yahoo.com wrote: > On Friday, August 5, 2016 at 12:04:52 AM UTC+3, rickman wrote: >> >> I know that the simulators are intentionally speed crippled to encourage >> users to upgrade to paid versions. I don't know if they do the same >> thing with synthesis tools or not. >> >> -- >> >> Rick C > > We are talking about X&A own integrated synthesis. I don't believe that there is a difference between "paid" and "free" tools except that "free" tools can't target certain devices. > Anyway, all my Quartus measurements were "paid". > Vivado measurements were sort of paid too - license came due to voucher that was attached to Zync Eval. board. I didn't realize Vivado was a Xilinx product. I haven't done much with Xilinx in some time. Diamond does include a Lattice synthesis tool, but I always use the Synopsis tool which is third party. I seem to recall Xilinx stopped offering third party synthesis with the free tools some time back, but I seem to recall they had something different. But then many years ago a Xilinx person pointed out to me they spend more money on software development than they do software, or maybe they used more people or something like that. The point was they are a software company that collects revenue from selling the hardware that the software supports. -- Rick CArticle: 159127
Interesting. I used your files and got the same results: 15s for synth, 4= 0s for PAR. I wonder why yours is so much faster. I reduced the clock per= iod in yours to 2.7ns, and the synth time went to 35s, but the PAR was stil= l about 45s. I'm using Verilog and a different part. Curious. I also hav= e a bunch of other files in my project, but they're not in the build hierar= chy, so that shouldn't make a difference.Article: 159128
I am pursuing the possibility of this being a licensing error. I found when I reinstalled the tool I had wiped out the license file. Oddly enough Diamond starts up happily, maybe because it found the license file for Diamond 3.3 which has not yet expired. I can't see anything different about those lines in the license files other than the date and the key numbers. I found that Diamond has a license debug facility and it has found a different NIC than the one I was using. When I type IPCONFIG /ALL on a command line I get the following sections.... Wireless LAN adapter Local Area Connection* 14: Ethernet adapter Ethernet: Wireless LAN adapter Wi-Fi: The old license files were using the Ethernet adapter physical address. The license debug tool sees the NIC under Wireless LAN adapter Wi-Fi. There is a NIC under Wireless LAN adapter Local Area Connection* 14: which is apparently a software thing rather than a real physical address. So why was the licensing working ok with the Ethernet adapter NIC but now insists on the Wi-Fi NIC? -- Rick CArticle: 159129
Hi, I have written a Mico32 application in C. Now I want to simulate my Mico32 system in the Modelsim simulator including the C application (toggling some LEDs, ISR for controling 7 SEGMENT display). As I have found out (by reading the Mico32 HW/SW handbook) I can create a memory initialization file which is 148MByte after generation. For that I have used the Mico32 Software Deployment Tools -> Mico32 On Chip Memory Deployment. My quesiton: What do I have to do next to simulate it in Modelsim? The Mico32 handbooks are not very helpful concerning that point. Thanks, NoroArticle: 159130
Anyone interested or need additional help using the BASYS 3 board? I have created a course on Udemy, here is a link for more information and a $10 coupon. If you have additional questions feel free to message me. https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=TIGER10 Thanks, Jordan ChristmanArticle: 159131
Is 148MB the size of the final contents of the on chip memory? If so, you m= ay be doing something very wrong; I don't think I know of any FPGA has on c= hip memory anywhere near that large! C code for toggling LEDs and such shou= ld not compile to such a huge file. To simulate it, you should just need a test bench in your chosen HDL that a= sserts all the inputs and hooks up all the outputs so you can see them plot= ted. In principle, if your vendor has hooked everything up right, then the pre-s= ynthesis simulation should already be accounting for the program code sitti= ng in your on-chip memory. Be sure to generate all the clocks and reset sig= nals, if everything doesn't get a reset in the beginning of sim, modelsim t= ends to leave signals in an indeterminate state rather than assuming they s= hould start at some default values. On Friday, August 12, 2016 at 6:58:24 AM UTC-7, noreeli...@gmail.com wrote: > Hi, >=20 > I have written a Mico32 application in C. >=20 > Now I want to simulate my Mico32 system in the Modelsim simulator includi= ng the C application (toggling some LEDs, ISR for controling 7 SEGMENT disp= lay). > As I have found out (by reading the Mico32 HW/SW handbook) I can create a= memory initialization file which is 148MByte after generation. For that I = have used > the Mico32 Software Deployment Tools -> Mico32 On Chip Memory Deployment. >=20 > My quesiton: What do I have to do next to simulate it in Modelsim? The Mi= co32 handbooks are not very helpful concerning that point. >=20 >=20 > Thanks, NoroArticle: 159132
>To simulate it, you should just need a test bench in your chosen HDL that >asserts all the inputs and hooks up all the outputs so you can see them plotted. But how do I get the C program sequence into my HDL design (FPGA embedded memory blocks) for functional simulation if the generated memory ini file is shooting FPGA ressources?Article: 159133
Additional point: The .elf file which is used to generate the memory ini file has 100 KB.Article: 159134
On 8/16/2016 6:09 AM, noreeli.schmidt@gmail.com wrote: >> To simulate it, you should just need a test bench in your chosen HDL that >asserts all the inputs and hooks up all the outputs so you can see them plotted. > > But how do I get the C program sequence into my HDL design (FPGA embedded memory blocks) for functional simulation if the generated memory ini file is shooting FPGA ressources? It is very likely that if you wish to simulate such a large program that it won't fit on FPGA resources, it may not be practical to run in the HDL simulator. Keep in mind the simulation will run many orders of magnitude slower than real time. -- Rick CArticle: 159135
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Yes, their memory is more of "virtual" multiport than actual multiport. I'= ve been studying some multiport architectures, because I may need a blockRA= M that has 4 ports (2 read, 2 write). It seems this quadruples the BRAM re= quirements. E.g., I need 4 36kb dual-port BRAMs to make a single 36kb quad= -port. Plus, I need additional flag/semaphore logic implemented in LUT-RAM= .Article: 159138
On 18/08/2016 20:46, Kevin Neilson wrote: > Yes, their memory is more of "virtual" multiport than actual multiport. I've been studying some multiport architectures, because I may need a blockRAM that has 4 ports (2 read, 2 write). It seems this quadruples the BRAM requirements. E.g., I need 4 36kb dual-port BRAMs to make a single 36kb quad-port. Plus, I need additional flag/semaphore logic implemented in LUT-RAM. > Can't see the rest of the thread, but if your required access times are lower than the BRAM you can have single data/address buffers on input and output of a single DP RAM and mux in as many ins and outs as you have time for, on a sequential basis. Depends how tight the BRAM availability is in your design I guess.Article: 159139
I'd call that more of a virtual multiport. In my case I need accesses every cycle, and my clock rate is high enough that I wouldn't be able to use a 2x clock for the BRAMs.Article: 159140
On 18/08/2016 20:46, Kevin Neilson wrote: > Yes, their memory is more of "virtual" multiport than actual > multiport. I've been studying some multiport architectures, because > I may need a blockRAM that has 4 ports (2 read, 2 write). It seems > this quadruples the BRAM requirements. E.g., I need 4 36kb dual-port > BRAMs to make a single 36kb quad-port. Plus, I need additional > flag/semaphore logic implemented in LUT-RAM. I also can't see the original post. It would be most helpful if you could quote sufficient to add some context to your post. I don't know of any BRAM quad port memories. I think you would need to consider an alternative method such as FIFOs and some arbitration or if the data is sequential to use this property to have BRAMs for odd and even addresses. -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.ukArticle: 159141
Hi, Does anyone have a PADS-PCB part (schematic+pcb decal) for the 484-ball ZYNQ? -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.comArticle: 159142
My project needs to program a Xilinx XC7336 44PLCC. I have the software now and the HW-130 programming unit. Also have the HW-137-PC44/VQ44 adapter which I assumed would work with the XC7336, but as it turns out it does not. So I need to find the adapter(s) below. If anyone can help out please let me know. HW-133-PC44 HW-133-PC68 HW-133-PC84 For reference here is webpage showing the HW-133-PC68 adapter (middle image): http://www.digital-circuitry.com/MyLAB_IC_PROG_HW-130.htm Also at this Xilinx support page http://www.xilinx.com/support/answers/961.html it mentions the HW-120 adapters are mostly compatible with the HW-130 programmer. So I could alternatively use these adapters if anyone has them: HW-126-PC44 HW-126-PC68 HW-126-PC84 Thanks for any help you may offer!Article: 159143
I am implementing four-bit-counter but I am getting value of x for Port_co= unter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and http:/= /pastebin.com/2kY3hQAN (testbench). I already finished the two flip-flop in= VHDL. I am now stuck with simulation. http://i.imgur.com/WXFQC5f.png Someone told me that the usual reason for an undefined output is failure t= o initialize all signal. So, I uncommented the clock_enable process and ch= ange the VHDL source to http://pastebin.com/y0j5iBBL ,but simulation just w= on't stop. Did I code my clock_enable process correctly? even after I manually stop the simulation, the waveform window is EMPTY Any help ?Article: 159144
I am implementing four-bit-counter but I am getting value of x for Port_cou= nter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and http://= pastebin.com/2kY3hQAN (testbench). I already finished the two flip-flop in = VHDL. I am now stuck with simulation. http://i.imgur.com/WXFQC5f.png Someone told me that the usual reason for an undefined output is failure to= initialize all signal. So, I uncommented the clock_enable process and cha= nge the VHDL source to http://pastebin.com/y0j5iBBL ,but simulation just wo= n't stop. Did I code my clock_enable process correctly? even after I manually stop the simulation, the waveform window is EMPTY any help ?Article: 159145
On 8/25/2016 10:21 AM, Marvin L wrote: > I am implementing four-bit-counter but I am getting value of x for Port_counter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and http://pastebin.com/2kY3hQAN (testbench). I already finished the two flip-flop in VHDL. I am now stuck with simulation. http://i.imgur.com/WXFQC5f.png > > Someone told me that the usual reason for an undefined output is failure to initialize all signal. So, I uncommented the clock_enable process and change the VHDL source to http://pastebin.com/y0j5iBBL ,but simulation just won't stop. Did I code my clock_enable process correctly? > > even after I manually stop the simulation, the waveform window is EMPTY > > any help ? You are making this far too complex. You have one output signal, Port_Counter. You only need one process to drive that output. A signal should not be driven from more than one process or you get a error. If you have intermediate signals to make your code simpler, you can define those in separate processes, but I don't think that is needed here. There are a lot of inputs which you don't say how they are used. I suggest you start with a simple enabled 4 bit counter and ignore the rest of the inputs for now. Then add code to add the functionality needed for the other inputs. You see no waveforms in simulation likely because you have not added any waveforms to the display. There should be a control somewhere to add *all* the signals to the waveform display. Or you can add them one at a time. You didn't say which simulator you are using. If it is not ActiveHDL I can't help you with that. I suggest you run the simulation for a fixed amount of time rather than expecting it to stop. The clock will prevent the simulation from ever stopping on its own. -- Rick CArticle: 159146
Marvin L wrote: > I am implementing four-bit-counter but I am getting value of x for Port_counter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and http://pastebin.com/2kY3hQAN (testbench). I already finished the two flip-flop in VHDL. I am now stuck with simulation. http://i.imgur.com/WXFQC5f.png > > Someone told me that the usual reason for an undefined output is failure to initialize all signal. So, I uncommented the clock_enable process and change the VHDL source to http://pastebin.com/y0j5iBBL ,but simulation just won't stop. Did I code my clock_enable process correctly? > > even after I manually stop the simulation, the waveform window is EMPTY > > any help ? Your clock_enable process has no sensitivity list. This is OK for synthesis, but in simulation it causes an endless loop since there are no wait statements. If you had coded it as: wait until rising_edge(clk) instead of if rising edge (clk) then the simulation would advance. As written, you should have clk in the sensitivity list. Otherwise simulation will be stuck at time zero. Also heed Rick's advice if you intend to synthesize this code. -- GaborArticle: 159147
So I'm looking at various platforms for general purpose, fairly low-end FPGAs, and it looks like the Lattice ECP5, Xilinx Artix-7, and Altera Cyclone V E all have options in the sort of * 170ish IO * Enough logic to do PLDy sort of tasks * $20ish in ~100p quantity. I've used Vivado, and Vivado's got its issues. I've used the latest Quartus Prime, and Quartus Prime's got its issues. Haven't used Diamond yet, but I'm guessing Diamond's got its issues. Has anyone been playing with any (or even better multiple) of these and got any opinions one way or another on which to go with? Or do I just roll a die? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 159148
On 8/25/2016 8:04 PM, Rob Gaddi wrote: > So I'm looking at various platforms for general purpose, fairly low-end > FPGAs, and it looks like the Lattice ECP5, Xilinx Artix-7, and Altera > Cyclone V E all have options in the sort of > > * 170ish IO > * Enough logic to do PLDy sort of tasks > * $20ish in ~100p quantity. > > I've used Vivado, and Vivado's got its issues. I've used the latest > Quartus Prime, and Quartus Prime's got its issues. Haven't used Diamond > yet, but I'm guessing Diamond's got its issues. > > Has anyone been playing with any (or even better multiple) of these and > got any opinions one way or another on which to go with? Or do I just > roll a die? If you are happy with Lattice you might consider the LFXP2-5E-5FTN256C. 172 I/Os, 5 kLUTs, 18 kB (9 bit bytes) block RAM, 3 DSP blocks and 12 multipliers. It is Flash rather than RAM based (or more accurately both), so no external Flash. The best part is it's $13 at qty 100. Lattice also has their ice40 line which has RAM and one time programmable NV memory. They have two lines, low power and high performance, LP8K and HX8K respectively. Both parts have 7,680 LUTs, 32 block RAMs (4 kbit) and no math components. I haven't used these parts, I've used the XP series. The Diamond software uses Synplicity and ActiveHDL for synthesis and simulation and seems to work ok. VHDL 2008 seems to be supported pretty well. -- Rick CArticle: 159149
Someone told me to use http://i.imgur.com/C5KOrve.png instead of separate processes but it says try to AVOID this. Any advice ?
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