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Messages from 16250

Article: 16250
Subject: Re: High speed reconfigurability
From: M.Vasilko@computer.org
Date: Wed, 12 May 1999 09:13:14 GMT
Links: << >>  << T >>  << A >>
Mark

You might find our Dynamically Reconfigurable Hardware WWW Library a
useful source of infos on these issues. Look at
http://dec.bournemouth.ac.uk/drhw_lib/

Best
--Milan

In article <37166B04.5DB4@xs4all.nl>,
  Mark <mkinsley@xs4all.nl> wrote:
> I like to possibilities offered by reconfigurable FPGAs, but it seems
> most of the devices around are designed to be loaded once on power up,
> and maybe reconfigured to do something different if the designer is
> being really ingenuitive.
>
> I've heard talk of some new FPGAs from Xilinx which alow partial
> reconfigurability (6000 series?), but i don't see these as being
> particularly more useful.... ? Anyone disagree here ?
>
> What i think would be really interesting, is being able to
re-configure
> an entire FPGA really quickly (say 1 system clock period ideally).
This
> translates into the idea of having 'layers' of FPGA config data which
> can be latched into the FPGA config area.  The inactive 'layers' being
> updated or replaced while not in use -> pretty much like a video
display
> where an image is built up in the off screen buffer before the active
> video buffer is toggled.
>
> The implications of such an architecture are of course ghastly amounts
> of configuration data flying around and a squadron of PentiumIV's
> working overtime trying to place, route and load all this into our
> liquid cooled UltraFPGA.  But if applied to a pretty small block of
> reconfigurable logic i think the creative designer could do some
really
> neat things.
>
> ....any comments ?
>
> Are there any such devices out there already ?
>
> Regds,
> Mark K.
>
> -- Life is about wanting what you don't know you don't want. --
>


--== Sent via Deja.com http://www.deja.com/ ==--
---Share what you know. Learn what you don't.---
Article: 16251
Subject: Fancy Dram problem
From: roman pollak <roman.pollak@Sun.COM>
Date: Wed, 12 May 1999 11:44:50 +0200
Links: << >>  << T >>  << A >>
Hi,


I'm currently develope a graphic interface for my 68040 board at home
using FPGA and VDRAM.
But I got a very fancy problem with it, which I can't get of it.
When the CPU is writing to the RAM, sometimes it also overwrite other
locations as well.
For example when the cpu is writing on the line X pos Y, it overwrites
also some other location on the same line. Could it be some kind of
reflection problem? Or some other effects, which I don't know about it? 
I saw in other designs, they use resistors between DRAM and Mux on the
address lines. But some other designs don't. Some use thouse on RAS/CAS,
some don't. What is the point of thouse resistors?

thanks Roman
Article: 16252
Subject: Re: Spartan Metastability parameters
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Wed, 12 May 1999 10:15:14 GMT
Links: << >>  << T >>  << A >>
Hi Peter,
	Are your metastability tests performed on a sample size large
enough to be able to estimate worst case figures?

Even something like a standard deviation would be nice.

So far, all we've been getting have been typical values.  Of course, a
typical value is better than no value at all, but it makes it hard to
employ worst case design methodologies.

Also, are you performing tests over temperature?  I would expect that
the resolution time would be longer at higher temperatures (because
the FF gain would be lower), but I'm just guessing.

Keep up the good work,
Allan.

On Mon, 10 May 1999 09:21:33 -0700, Peter Alfke <peter@xilinx.com>
wrote:

>Allan Herriman wrote:
>
>>  the metastability parameters
>> aren't published in the data sheet.  Nice try, though.
>>
>> Does anyone know why such important parameters *aren't* listed in a
>> datasheet, even as typical values?
>>
>> Allan.
>
>I can only speak for Xilinx:
>
>Because hardly anybody asks for the data.
>I published a fairly detailed explanation of metastability, test methodology,
>and results in the 1989 Xilinx data book, and repeated and improved it in all
>the seven or eight subsequent editions, ( look in the index!) but I have sensed
>very little interest.
>We are about to start a new series of tests, and I will publish the results
>again.
>Nice to hear that somebody is interested.
>
>Peter Alfke, Xilinx Applications
Article: 16253
Subject: Virtex development boards
From: Daryl Bradley <dwb105@ohm.york.ac.uk>
Date: Wed, 12 May 1999 11:56:19 +0100
Links: << >>  << T >>  << A >>
Other than the Nallatech and VCC Virtual Workbench (which we have on
order) boards, does anyone know of any other virtex development boards
that are currently available.

We have money to spend and want to use it now!!!!

Many thanks

Daryl Bradley

--

Bio-Inspired Architectures
Department of Electronics
University of York, UK
http://www-users.york.ac.uk/~dwb105


Article: 16254
Subject: How synthesize tools concern with size of the design?
From: "Tippawan Aranwattananon" <s8014180@kmitl.ac.th>
Date: Wed, 12 May 1999 17:58:44 +0700
Links: << >>  << T >>  << A >>
I have design a small core in VHDL and I would like to know if I use
difference tools to synthesize my VHDL code, will the numbers of CLB from
those tools be difference.
And if you know any excellent tools for synthesize please recommend.

realk@thaimail.com


Article: 16255
Subject: Re: UART Design
From: "Tippawan Aranwattananon" <s8014180@kmitl.ac.th>
Date: Wed, 12 May 1999 18:02:22 +0700
Links: << >>  << T >>  << A >>
I have sent you a UART design demo in Verilog from Exemplar (uart.v) ,hope
it 'll be useful for you.
                            realk@thaimail.com


Dan Oomkes wrote in message <3738805B.CE920511@avionics.bfg.com>...
>I am looking for a simple UART design (without all of the handshaking
>features) in verilog for use in a Xilinx XCS20 device.  Does anybody
>know where I could download a  free design?
>


begin 666 uart.v
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"#0H`
`
end

Article: 16256
Subject: Re: Synchronizer design?
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Wed, 12 May 1999 13:06:44 +0200
Links: << >>  << T >>  << A >>
Jonas Thor wrote:
> 
> Hello,
> I know I can cascade two flip-flops, but are
> there other/better ways?
Adding to all wise things mentioned already I recommend you a 
paper by Charles Seitz and others. 
"Pipeline synchronizers" or something like that.
You find it somewhere on www.myri.com.
Andreas
-- 
---------------------------------------------------------------
                        Andreas C. Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
                        Ratzeburger Allee 160
                        D-23538 Luebeck Germany

		        Tel.: +49 451 500-3741, Fax: -3687
		        Email: doering@iti.mu-luebeck.de
                        Home: http://www.iti.mu-luebeck.de/~doering 
                             quiz, papers, VHDL, music

"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------
Article: 16257
Subject: Re: Fancy Dram problem
From: Chip Brown <REMOVE.ALL.cbrown@mobsec.CAPLETTERS.com>
Date: 12 May 1999 11:35:12 GMT
Links: << >>  << T >>  << A >>
roman pollak <roman.pollak@Sun.COM> wrote in <37394D92.7080B6C0@Sun.COM>:

> Hi,
> 
> 
> I'm currently develope a graphic interface for my 68040 board at home
> using FPGA and VDRAM.
> But I got a very fancy problem with it, which I can't get of it.
> When the CPU is writing to the RAM, sometimes it also overwrite other
> locations as well.
> For example when the cpu is writing on the line X pos Y, it overwrites
> also some other location on the same line. Could it be some kind of
> reflection problem? Or some other effects, which I don't know about it? 
> I saw in other designs, they use resistors between DRAM and Mux on the
> address lines. But some other designs don't. Some use thouse on RAS/CAS,
> some don't. What is the point of thouse resistors?
> 
> thanks Roman

The point of those resistors is to cut over/undershoot by impedance matching 
the wires between the mux source and DRAM destination.  On the DRAM designs 
I've done, it's very important to get this right.  I don't know that this is 
what's causing your problem - the problems caused by overshoot on 
RAS/CAS/Address tend to be very random and non-repeatable.  

If you have a repeatable problem, there's probably a logic error. 
Article: 16258
Subject: Re: Spartan Metastability parameters
From: rk <stellare@erols.com.NOSPAM>
Date: Wed, 12 May 1999 07:40:08 -0400
Links: << >>  << T >>  << A >>
Allan Herriman wrote:

> Hi Peter,
>         Are your metastability tests performed on a sample size large
> enough to be able to estimate worst case figures?
>
> Even something like a standard deviation would be nice.
>
> So far, all we've been getting have been typical values.  Of course, a
> typical value is better than no value at all, but it makes it hard to
> employ worst case design methodologies.
>
> Also, are you performing tests over temperature?  I would expect that
> the resolution time would be longer at higher temperatures (because
> the FF gain would be lower), but I'm just guessing.

a quick fun fact ... got more data somewhere ...

from "metastability of cmos latch/flip-flop" by lee-sup kim, ieee journal of
solid-state circuits, august '90,  ...

"in fig. 14, the measurement results corresponding to t=50, 75, 100, and 125c are
shown, respectively.  as expected, the higher chip temperature gives rise to higher
failure rates.  about 75C of temperature difference causes four orders of magnitude
degradation in MTBF. ... "

have more data, and i know i have some signetics stuff somewhere ...

rk

Article: 16259
Subject: Re: Virtex development boards
From: Christof Teuscher <christof.teuscher@epfl.ch>
Date: Wed, 12 May 1999 14:47:10 +0200
Links: << >>  << T >>  << A >>
We have on order a Virtex based PCI board (RC1010-PP) from

  http://www.embedded-solutions.ltd.uk/

As far as we know, the price will be about $6500 for a board
equipped with a XCV1000.

 Christof



Daryl Bradley wrote:
> 
> Other than the Nallatech and VCC Virtual Workbench (which we have on
> order) boards, does anyone know of any other virtex development boards
> that are currently available.
> 
> We have money to spend and want to use it now!!!!


________________________________________________________________________
Christof Teuscher                      Tel.:  +41 21 693 47 92
Logic Systems Laboratory               Fax:   +41 21 693 37 05
Swiss Federal Institute of Technology  christof.teuscher@epfl.ch
EPFL-DI-LSL                            http://lslwww.epfl.ch/
CH - 1015 Lausanne                     http://www.teuschers.ch/christof
________________________________________________________________________
Article: 16260
Subject: Re: Synchronizer design?
From: Ray Andraka <randraka@ids.net>
Date: Wed, 12 May 1999 09:41:13 -0400
Links: << >>  << T >>  << A >>
Peter, I have to disagree here.  Clock rates in today's systems are quite a bit
higher than they were 10 years ago.  With system clocks near 100 MHz and aynch
inputs with even half that rate, metastability is as scary as ever.  It would be
really nice to have the numbers instead of just guessing.

Peter Alfke wrote:

> There is no way ( NO WAY ! ) to avoid metastability, but modern circuits resolve
> it so fast that metastability is no longer the same scary subject it was ten
> years ago.
>
> Peter Alfke, Xilinx Applications



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 16261
Subject: Re: Synchronizer design?
From: Ray Andraka <randraka@ids.net>
Date: Wed, 12 May 1999 09:44:44 -0400
Links: << >>  << T >>  << A >>
Why not just sample at the lower rate then.  You get considerably more benefit
since the likelyhood of a metastable event lasting a whole clock is smaller.

Jamie Sanderson wrote:

> More often than not, I use the method you've described. Did you read the
> same TI document on metastability I did? If you really want something that
> is bullet-proof and have gates to spare, you can add a "majority logic"
> circuit.
>
> Add one or two stages to your flip-flop chain, bring it to three or four.
> Then take all of the outputs to two logic functions, one which causes the
> output to be high only when all flip-flop outputs are high, and one which
> causes the output to be low only when all flip-flop outputs are low. That
> output signal can also be run through a final flip-flop.
>
> It slows your signal down considerably, but acts like a low-pass filter.
>
> Cheers,
> Jamie
>
> Jonas Thor wrote in message <3737b8af.23247503@news1.tninet.se>...
> >Hello,
> >
> >My digital design books don't cover synchronizers in detail. So I am
> >asking here and hoping for feedback. Basically I have an asynchronous
> >input signal and I want to synchronize this to the FPGA clock. This
> >can of course be done by simply sampling the signal with an input
> >flip-flop and depending on the clock rate and the characteristic of
> >the flip-flop I can estimate a MTBF. But how do I reduce this MTBF by
> >designing synchronizer? I know I can cascade two flip-flops, but are
> >there other/better ways?
> >
> >Btw, this just a general question and there is no specific
> >application.
> >
> >Thanks!
> >Jonas Thor



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 16262
Subject: Re: How synthesize tools concern with size of the design?
From: Ray Andraka <randraka@ids.net>
Date: Wed, 12 May 1999 09:49:08 -0400
Links: << >>  << T >>  << A >>
Different tools (and sometimes even different revisions of the same tool)
will yield different results.  Exemplar and Synplicity are currently the best
ones out there for FPGAs.

Tippawan Aranwattananon wrote:

> I have design a small core in VHDL and I would like to know if I use
> difference tools to synthesize my VHDL code, will the numbers of CLB from
> those tools be difference.
> And if you know any excellent tools for synthesize please recommend.
>
> realk@thaimail.com



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 16263
Subject: Re: Fancy Dram problem
From: acher@informatik.tu-muenchen.de (Georg Acher)
Date: 12 May 1999 15:10:48 GMT
Links: << >>  << T >>  << A >>

In article <37394D92.7080B6C0@Sun.COM>, roman pollak <roman.pollak@Sun.COM> writes:
|> I'm currently develope a graphic interface for my 68040 board at home
|> using FPGA and VDRAM.
|> But I got a very fancy problem with it, which I can't get of it.
|> When the CPU is writing to the RAM, sometimes it also overwrite other
|> locations as well.
|> For example when the cpu is writing on the line X pos Y, it overwrites
|> also some other location on the same line. Could it be some kind of
|> reflection problem? Or some other effects, which I don't know about it? 
|> I saw in other designs, they use resistors between DRAM and Mux on the
|> address lines. But some other designs don't. Some use thouse on RAS/CAS,
|> some don't. What is the point of thouse resistors?

The resistors are some sort of series termination to avoid reflections,
especially useful on RAS/CAS. Modern DRAM can react so fast that they interprete
the RAS ringing as access termination and start. Since the DRAM had no time to
write its line buffer back (precharge), the whole line can be destroyed. The
problem you have is possibly a similar effect: If you violate the RAS-low
access time or the precharge time, you will get everything from one-bit-failures
to 4096bit-failures. 
Try to relax the timing a bit...
-- 
	Bye
         Georg Acher, acher@in.tum.de         
         http://www.in.tum.de/~acher/
          "Oh no, not again !" The bowl of petunias          
Article: 16264
Subject: Re: Fancy Dram problem
From: Mike Treseler <tres@tc.fluke.com>
Date: Wed, 12 May 1999 15:14:42 +0000
Links: << >>  << T >>  << A >>
roman pollak wrote:
> 
> Hi,
> 
> I'm currently develope a graphic interface for my 68040 board at home
> using FPGA and VDRAM.
> But I got a very fancy problem with it, which I can't get of it.
> When the CPU is writing to the RAM, sometimes it also overwrite other
> locations as well.
> For example when the cpu is writing on the line X pos Y, it overwrites
> also some other location on the same line. Could it be some kind of
> reflection problem? Or some other effects, which I don't know about it?
> I saw in other designs, they use resistors between DRAM and Mux on the
> address lines. But some other designs don't. Some use thouse on RAS/CAS,
> some don't. What is the point of thouse resistors?

Sounds like the row and column sizes of the controller do not match
the DRAM. Unlikely that lack of series terminations would cause 
this symptom.

Mike Treseler,  Sr. Staff Engineer
Fluke Corporation                        mailto:tres@tc.fluke.com
PO Box 9090 M/S 279F                             phone:425.356.5409
Everett WA USA 98206-9090                          fax:425.356.5043
Article: 16265
Subject: Re: Synchronizer design?
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Wed, 12 May 1999 12:40:51 -0400
Links: << >>  << T >>  << A >>
That's another way of doing it, but equivalent, really. Unless you have an
external clock that is synchronous to your desired clock, but slower, you'll
have to put in a clock divider anyhow. In other words, you could use up four
flip-flops to re-time the signal several times, or four flip-flops to create
a clock/4 signal.

Either way, I still think that two flip-flops chained together will give you
all the protection from metastability that is needed. Of course, I say this
from my perspective only, I'm not designing equipment for life support or
anything like that.

Cheers,
Jamie

Ray Andraka wrote in message <373985CB.FA9AD40B@ids.net>...
>Why not just sample at the lower rate then.  You get considerably more
benefit
>since the likelyhood of a metastable event lasting a whole clock is
smaller.
>
>Jamie Sanderson wrote:
>
>> More often than not, I use the method you've described. Did you read the
>> same TI document on metastability I did? If you really want something
that
>> is bullet-proof and have gates to spare, you can add a "majority logic"
>> circuit.
>>
>> Add one or two stages to your flip-flop chain, bring it to three or four.
>> Then take all of the outputs to two logic functions, one which causes the
>> output to be high only when all flip-flop outputs are high, and one which
>> causes the output to be low only when all flip-flop outputs are low. That
>> output signal can also be run through a final flip-flop.
>>
>> It slows your signal down considerably, but acts like a low-pass filter.
>>
>> Cheers,
>> Jamie



Article: 16266
Subject: Re: Spartan Metastability parameters
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 12 May 1999 09:42:09 -0700
Links: << >>  << T >>  << A >>
Allan Herriman wrote:

> Hi Peter,
>         Are your metastability tests performed on a sample size large
> enough to be able to estimate worst case figures?
>
> Even something like a standard deviation would be nice.
>
> So far, all we've been getting have been typical values.  Of course, a
> typical value is better than no value at all, but it makes it hard to
> employ worst case design methodologies.
>
> Also, are you performing tests over temperature?  I would expect that
> the resolution time would be longer at higher temperatures (because
> the FF gain would be lower), but I'm just guessing.
>
> Keep up the good work,
> Allan.
>  

Thanks, Allan.
We will test fast and slow devices, room temperature and hot. That should cover
the spread.
These are manually driven and interpreted bench tests, so there is a limit to
the data volume.

The reason these numbers end up in app notes and not the data sheet proper is
that the world expects data sheet information to be 100% tested and guaranteed.
And metastability numbers cannot be tested in production. On the other hand,
there is no reason to expect wild fluctuations. The delay is determined by the
gain-bandwidth product of a tightly-knit design, the master latch only, so it
should be worst at high temperature and low supply voltage and slowest
processing ( lowest speed grade ).

Peter Alfke, Xilinx Applications
 
 

Article: 16267
Subject: Re: Virtex based PCI cards
From: alfred fuchs <alfred.fuchs@siemens.at>
Date: Wed, 12 May 1999 20:09:21 +0200
Links: << >>  << T >>  << A >>
I've just finished the design of a CompactPCI board (6U) with one Virtex1000
and two synchronous SRAM-modules (2Mx72). It mainly uses rear-panel-I/O
(more than 100 signals) and is therefore open for various applications. The
PCI-IF is a PLX9054, the FPGA is configured by the PCI-master.
Pricing is TBD, but we tend to be expensive.

Alfred Fuchs
Siemens Austria
PSE PRO LMS2
+43/1/1707-34113

Atif Zafar schrieb:

> Hello:
>
>     Does anyone know of any development boards (PCI) that use the Virtex
> FPGA? I am interested in a board with preferably several XV800 or XV1000
> devices along with RAM for prototyping a custom graphics pipeline. I
> have heard of the PCI Pamette board, but to my knowledge this does not
> have Virtex silicon. Thanks for any info.
>
> Atif Zafar
> Regenstrief Institute
> Zafar_A@regenstrief.iupui.edu

Article: 16268
Subject: Re: Virtex development boards
From: Jonathan Feifarek <feifarek@removethis.ieee.com>
Date: Wed, 12 May 1999 17:08:21 -0600
Links: << >>  << T >>  << A >>
Daryl,
You might try Annapolis Microsystems at:
http://www.annapmicro.com/PR9126.html - it can be used for development
in Reconfigurable Computing applications.  It has connectors for add-on
boards and various I/O extenders.
Plus, they'll help you spend your money!
Cheers,
Jonathan

Daryl Bradley wrote:
> 
> Other than the Nallatech and VCC Virtual Workbench (which we have on
> order) boards, does anyone know of any other virtex development boards
> that are currently available.
> 
> We have money to spend and want to use it now!!!!
 
-- 
Jonathan F. Feifarek
Consulting and design
Programmable logic solutions
Article: 16269
Subject: Can use pullup in XC9500XL?
From: "basaro" <basaro@fa2.so-net.ne.jp>
Date: Thu, 13 May 1999 08:50:26 +0900
Links: << >>  << T >>  << A >>
Hellow Everyone.

I'm T.Koyama

Can use Pullup in XC9500XL when user operation.

XC9500 does not use Pullup, but XC9500XL?

If it can use, Please teuch me how use.

Thank you
                            T.Koyama (basaro@fa2.so-net.ne.jp)



Article: 16270
Subject: floating points to fixed points on a FPGA
From: Jean-Francois Richard <richard@bell.info.uqam.ca>
Date: Thu, 13 May 1999 00:06:09 GMT
Links: << >>  << T >>  << A >>
I did an algorithm in C language and I want to do 
the implementation on a FPGA.  The algorithm is on
floating points and I would like to
transfert that on fixed points.
  
Any good software that do the conversion AUTOMATICALY ?
Do they calculate the quantization error ?
Article: 16271
Subject: Reference on word lenght quantization
From: Jean-Francois Richard <richard@bell.info.uqam.ca>
Date: Thu, 13 May 1999 00:11:57 GMT
Links: << >>  << T >>  << A >>
I'm looking for some good books or papers on the conversion
floating points to fixed points for a hardware implementation.
I know that L.R.Rabiner is a excellent author, any other one ?
Article: 16272
Subject: Re: floating points to fixed points on a FPGA
From: Steven Casselman <sc@vcc.com>
Date: Wed, 12 May 1999 17:27:28 -0700
Links: << >>  << T >>  << A >>


Jean-Francois Richard wrote:

> I did an algorithm in C language and I want to do
> the implementation on a FPGA.  The algorithm is on
> floating points and I would like to
> transfert that on fixed points.
>
> Any good software that do the conversion AUTOMATICALY ?
> Do they calculate the quantization error ?

There was a really great paper from the Chinese
University of Hong Kong given by M.P. Leong
mpleong@cse.cuhk.edu.hk
called
"Automatic Floating to Fixed Point Translation
and its Application to Post-Rendering 3D Warping"
I was very impressed with the results.


--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 16273
Subject: Re: Synchronizer design?
From: Mark Summerfield <m.summerfield@ee.mu.oz.au>
Date: Thu, 13 May 1999 10:55:06 +1000
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> There is no way ( NO WAY ! ) to avoid metastability...

I used to teach a course in digital design in which I covered 
metastability.  I would stand there in class and say "there is no way
(NO WAY!) to avoid metastability", and I would refer the students
to the same statement and explanation in their textbook, and every 
year at least one student would come to me with a circuit s/he 
claimed would be metastable-free.  I would patiently explain why
it wouldn't work, but there are always a few who won't believe.

I'm sure they're the same students who are designing perpetual-motion
machines for their thermodynamics lecturers, too! ;-)

Mark
Article: 16274
Subject: Re: Help me: What is FPGA?
From: me@here.com
Date: 13 May 1999 03:36:30 GMT
Links: << >>  << T >>  << A >>
hhk <hhk@wxs.nl> wrote:
> On Fri, 30 Apr 1999 19:18:40 -0700, "Iwan Santoso Oei"
> <iwanoei@mindspring.com> wrote:

>>Hi, i am new guys in this room. Because i will make a thesis in FPGA topic,
>>if you don't mind, tell me about FPGA is.

If I were you I'd chose a thesis in an area with a little 
more knowledge, to speak of.... ;-)

>>1. What is FPGA? Is the function of FPGA can do the same like
>>Microcontrolller?

Well, you can program an FPGA to emulate a microcontroller,
or its functiuonality, but they are two different things. 

>>2. I confuse if FPGA programmable from the beginning(using VHDL or Verilog),
>>how can we change the design when we already made it?


>>3. If the FPGA can do the same function like Microcontroller(such as
>>Motorola 68HC11), is that any possibilities that FPGA will replace
>>Microcontroller in the future?

In general -- NO.  They're like apples and oranges.   

If you have a microcontroller that does something relatively 
simple you can replace that with a state machine implemented 
in an FPGA, but for most uses that's not economical.
 
>>
>>Thanks for your attention and help
>>
>>
>>

> Hi, I am a student in electronics so i don't know too much about it.
> But FPGA stands for Field Programmable Gate Array. And is not
> something like a microcontroler. So it won't replace it.

> A microcontoler is continuisly driven by software.

It's driven by the clock signal and it's executing instructions.

> An FPGA is some
> kind of board filled with and/or/xor etc. ports.

Not exactly.  

> Using these ports a
> complete PCB can be programmed into the device. Depending on the used
> technology the FPGA can be reprogramed or not.
> To change the design you have to change your VHDL design and implement
> the desing again.

> As i don't know evry thing I just can advise you to visit the internet
> site of Xilinx (great site) Actel and altera. These are all
> manufacturers of FPGA's and PLD's.


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