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Messages from 17275

Article: 17275
Subject: SOLUTION: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
From: "Asher C. Martin" <martin2@acm.uiuc.edu>
Date: Thu, 15 Jul 1999 16:40:21 -0500
Links: << >>  << T >>  << A >>

Thanks for all the advice...

Here is an easy solution that I figured out...

After you have compiled your VHDL code take a look at your .RPT file. 
In side the .RPT file will be a listing of all the names of all the
pins.  You can then redefine all the pin outs...

SEE ATTACHED IMAGE IF YOU HAVE ANY FURTHER QUESTIONS

Best regards,

>Asher<

<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
 Asher C. Martin
 805 West Oregon Street
 Urbana, IL 61801-3825
 (217) 367-3877
 E-MAIL: martin2@acm.uiuc.edu
 http://fermi.isdn.uiuc.edu
 telnet://fermi.isdn.uiuc.edu
 ftp://feynman.isdn.uiuc.edu


Article: 17276
Subject: Re: PCI interface
From: Jim McManus <jim.mcmanus@xilinx.com>
Date: Thu, 15 Jul 1999 18:18:24 -0700
Links: << >>  << T >>  << A >>
Rickman wrote:
> Perhaps I am missing something, but I don't see where you explain how
> you meet the spec in a 3.3v signalling environment. From your
> description, it would appear that you are required to clamp inputs to
> 3.3v with diodes. Do you in fact do that? You indicate that a separate
> bitstream is required for 5v vs. 3.3v operation, but you don't indicate
> what is different about the bitstream or how compliance is maintained in
> the 3.3v environment.
> 
> Can you explain this in more detail?

Rick, I'd be glad to. Xilinx provides upper clamp diodes on all 3.3 V
devices. On the earlier XL series, these clamps only tied to pads on the
die. To use them we had to bond out this pad. The result of this was our
XLT family. As we improved our PCI offerings on later families (i.e.
SpartanXL, XLA, and Virtex), me made this clamp diode capable of being
tied to the 3.3 V rail, or left floating, via bitstream control. All
devices, including older 5 V devices have the lower clamp diode. There
are two device checklists, one for 5 V and one for 3.3 V, in the PCI
checklist. The PCI checklist items that cover this are:

5 V signaling:
CE15. Clamps on all signals source at least 25mA at -1V, and 91mA at
-2V?
proven by: __ SPICE simulation, __ device characterization,
other:___________       
na ___ yes___ no___

3.3 V Signaling:
CE31. Clamps on all signals source at least 25mA at -1V, and 91mA at
-2V?
proven by: ___ SPICE simulation, __ device characterization,
other:___________       
yes___ no___

CE32. Clamps on all signals sink at least 25mA at Vcc+1V, and 91mA at
Vcc+2V?
proven by: ___ SPICE simulation, __ device characterization,
other:__________
na ___ yes___ no___

To test the first item, we load a 5 V bitstream, which has the upper
clamp disabled and see if it meets the requirements. 

To test the second two items, we load a 3.3 V bitstream, which has the
upper clamps enabled, and test it. These items are listed in our data
book for each device family we support. 

So to answer your question, we do in fact tie the upper clamp diodes to
3.3 V under bitstream control. For Virtex parts, each individual I/O can
have the clamp enabled or disabled. This is done by selecting the
appropriate I/O cell in your design. For SpartanXL and XLA, this is set
when you are compiling the bitstream. You must set an option to in
bitgen to enable these clamps. In both cases, a series of pips inside
the FPGA are set to tie the clamps to the rail, or not set to leave them
floating. 

The 3.3 V or 5 V drive strength is set in a similar manner for the
Virtex or SpartanXL and XLA families.

As I mentioned in my previous posts, the user is responsible for the
system level design. If he intends to do a fully compliant universal PCI
card, he must insure that the correct bitstream is loaded depending on
Vio. 


Jim McManus
Xilinx PCI Applications Engineer
Article: 17277
Subject: Re: PCI interface
From: Jim McManus <jim.mcmanus@xilinx.com>
Date: Thu, 15 Jul 1999 19:09:14 -0700
Links: << >>  << T >>  << A >>
Bob Bauman wrote:
> 
> Jim,
> 
> The informaton about universal PCI cards is helpful.

Thanks!
 
> Is there an easy way to switch between 3.3V and 5V configuration bit streams
> when a serial EEPROM is used to hold configuration data?

Bob, this will require some discrete logic on the board. The serial
proms have a CE pin; an inverter combined with the output of your
comparator could select between the two serial proms. On the current
universal PCI board I'm developing, I use a parallel flash prom to hold
the two bitstreams; since I have a CPLD on board, I take advantage of
this to select one bitstream or another.  
 
> Would this scenario work and be PCI compliant for a Spartan XL universal
> card: Always load the 3.3V configuration from an on-board serial EEPROM. If
> the environment is determined to be 5V (via query over the bus), reconfigure
> the device over the PCI bus with the 5V configuration bit stream.

You would not want to do this. If you load a 3.3 V bitstream and are in
a 5 V bus, the 5 V from the other devices would result in a short across
the upper clamp diode. Xilinx does not do reliability testing for this
condition, so never use a 3.3 V PCI bitstream in a 5 V PCI bus.
Likewise, you would not want to load a 5 V PCI bitstream while plugged
into a 3.3 V PCI bus.

Your query should be of the Vio pin, which is available immediately as
the system powers up, so there is no need to wait in doing your
determination. 


Jim McManus
Xilinx PCI Applications Engineer
Article: 17278
Subject: Re: PCI interface
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 15 Jul 1999 23:00:32 -0400
Links: << >>  << T >>  << A >>
Jim McManus wrote:
> Rick, I'd be glad to. Xilinx provides upper clamp diodes on all 3.3 V
> devices. On the earlier XL series, these clamps only tied to pads on the
> die. To use them we had to bond out this pad. The result of this was our
> XLT family. As we improved our PCI offerings on later families (i.e.
> SpartanXL, XLA, and Virtex), me made this clamp diode capable of being
> tied to the 3.3 V rail, or left floating, via bitstream control. All
> devices, including older 5 V devices have the lower clamp diode. There
> are two device checklists, one for 5 V and one for 3.3 V, in the PCI
> checklist. The PCI checklist items that cover this are:
> 
> 5 V signaling:
> CE15. Clamps on all signals source at least 25mA at -1V, and 91mA at
> -2V?
> proven by: __ SPICE simulation, __ device characterization,
> other:___________
> na ___ yes___ no___
> 
> 3.3 V Signaling:
> CE31. Clamps on all signals source at least 25mA at -1V, and 91mA at
> -2V?
> proven by: ___ SPICE simulation, __ device characterization,
> other:___________
> yes___ no___
> 
> CE32. Clamps on all signals sink at least 25mA at Vcc+1V, and 91mA at
> Vcc+2V?
> proven by: ___ SPICE simulation, __ device characterization,
> other:__________
> na ___ yes___ no___
> 
> To test the first item, we load a 5 V bitstream, which has the upper
> clamp disabled and see if it meets the requirements.
> 
> To test the second two items, we load a 3.3 V bitstream, which has the
> upper clamps enabled, and test it. These items are listed in our data
> book for each device family we support.
> 
> So to answer your question, we do in fact tie the upper clamp diodes to
> 3.3 V under bitstream control. For Virtex parts, each individual I/O can
> have the clamp enabled or disabled. This is done by selecting the
> appropriate I/O cell in your design. For SpartanXL and XLA, this is set
> when you are compiling the bitstream. You must set an option to in
> bitgen to enable these clamps. In both cases, a series of pips inside
> the FPGA are set to tie the clamps to the rail, or not set to leave them
> floating.
> 
> The 3.3 V or 5 V drive strength is set in a similar manner for the
> Virtex or SpartanXL and XLA families.
> 
> As I mentioned in my previous posts, the user is responsible for the
> system level design. If he intends to do a fully compliant universal PCI
> card, he must insure that the correct bitstream is loaded depending on
> Vio.
> 
> Jim McManus
> Xilinx PCI Applications Engineer


Very good explaination. Thanks.


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 17279
Subject: Re: Dongle problems.
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 15 Jul 1999 23:34:39 -0400
Links: << >>  << T >>  << A >>
bob elkind wrote:
> 
> Orcad 9+ can be locked to a NIC or a hard drive or a dongle, or can float (FlexLM).
> 
> -- Bob Elkind

Are you sure about the locking to a hard drive SN? I had a lenghtly
discussion with Orcad about the node locking and they never once
voluntered that they could lock to the hard drive SN! That would be
entirely acceptable to me. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 17280
Subject: Re: Dongle problems.
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 15 Jul 1999 23:37:38 -0400
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> Nothing more than, yup it's a problem and an offer for a temporary license locked to the
> c: drive serial number.
> 
> Stuart Clubb wrote:
> 
> > On Wed, 14 Jul 1999 17:07:58 -0400, Ray Andraka <randraka@ids.net>
> > wrote:
> >
> > >Some software won't work with the latest sentinel driver...notably viewlogic WVO 7.5
> >
> > eek!

This is why I hate most forms of node locking. It always ends up being a
problem somewhere down the road. And being overly optimistic, I never
think to add a day or two to my schedules to deal with this sort of
thing. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 17281
Subject: Re: Mixed Design Problem (FPGA Express/ACTEL)
From: "Michael Ayton" <mayton@gnt.com>
Date: Thu, 15 Jul 1999 22:17:00 -0700
Links: << >>  << T >>  << A >>
We currently are doing a project in OrCAD that is in schematic form and it
contains a few blocks with VHDL.  What we end up doing is creating a VHDL
netlist from the schematic.  Take that netlist plus the VHDL code for the
few blocks along with the library of components for the Actel FPGA (this is
included with OrCAD) and run them all through Leonardo Spectrum to get your
EDIF.  Then just run that with your pin file through the Actel designer.  I
don't know what schematic package you are using but look to see if you can
make the VHDL netlist and obtain the VHDL  component library.

Hope this helps.


Ingo Purnhagen <purnhagen@ohb-system.de> wrote in message
news:7mi6c4$b85$1@black.news.nacamar.net...
> Hi everybody,
>
> I am trying to implement with Viewlogics FPGA Express a mixed design
> (schematic/VHDL)  in an ACTEL FPGA without success.
>
> What is the right way to implement:
> a)
> - generate an EDIF netlist from VHDL design with FPGA Express
> - invoke EDIF netlist reader to build *.wir file
> - build schematic and symbol from *.wir file with ViewGen
> - implement symbol (with hidden VHDL design) in topdesign (schematic)
> - export EDIF netlist
> - invoke ACTEL Designer
>
> b) (do it the XILINX way)
> - generate symbol from VHDL design (e.g. VHDL2SYM.exe)
> - implement symbol (with hidden VHDL design) in topdesign (schematic)
> - invoke fepreproc to build *.edn
> - start FPGA Express (New Project with schematic (*.edn) and vhdl (*.vhd)
> files)
> - export EDIF netlist from optimized chip
> -> this works (fine?) for Xilinx designs but for ACTEL designs this EDIF
> netlist is empty accept some general things
>
> c) forget mixed design
>
>
> Way a) seems untypical for me!
> What is wrong in b)
>
> Waiting for answers, Ingo.
>
>
>


Article: 17282
Subject: Components for sale (London, UK)
From: "Frank A. Vorstenbosch" <frank@falstaff.demon.co.uk>
Date: Fri, 16 Jul 1999 09:17:46 +0100
Links: << >>  << T >>  << A >>
Hallo!

I have a number of FPGAs for sale.  All of these are surplus to my
company, and I am selling these privately.  I prefer not to break the
dry-sealed packs; I have no way of re-sealing them.  
Any reasonable offer accepted.  Buyer pays for shipping.

Lot 5
-----
Altera EPF6016TC144-3 - FLEX FPGA, 1320 Logic Elements, 117 I/Os
TQFP-144, 60 pieces, in tray

Lot 6
-----
Altera EPF8820ATC144-4 - FLEX FPGA, 672 Logic Elements, 112 I/Os
TQFP-144, 60 pieces, in tray

Frank Vorstenbosch
------------------------------------------------------------------------
Frank A. Vorstenbosch    <SPAM_ACCEPT="NONE">    Phone:  +44-976-430 569
Wimbledon, London SW19                        frank@falstaff.demon.co.uk
Article: 17283
Subject: Re: Beginner in need of help
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Fri, 16 Jul 1999 06:44:50 -0700
Links: << >>  << T >>  << A >>
The Programmable Logic Jump Station at http://www.optimagic.com may be a
good place to start.  It has links to most information on FPGAs, CPLDs, and
associated software.  You can also find links to books and tutorials.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Yonatan Mittlefehldt wrote in message ...
>Hi, I just recently became interested in FPGAs, and was wondering if
>anyone knew of a good website or book that would help out a beginner?
>Most of the info I have found has been to high-level for me just yet.
>Thanks in advance.
>
>yono
>


Article: 17284
Subject: Re: Digital modulator? Synthesisable Sin(x) funct.
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 16 Jul 1999 22:22:01 -0400
Links: << >>  << T >>  << A >>
Luis Yanes wrote:
> 
> Hello.
> 
> I'll like to syntesize a digital modulator within a Xilinx XC5202
> fpga, since I purchased a few ago the Foundation package to
> learn and homebrewing.
> 
> The diagram of what I intend to do, could be something like:
> 
> phase_offset==============           ______    __________
>         _______________   |         |      |  |          |
>        |    _________  |  |    ====>|Sin(x)|=>|          |=>Real
>        V   |         | |  V   |     |______|  |Complex   |
> freq=>(+)=>|Phase_acc|='>(+)=>|      ______   |          |
>            |_________|        |     |      |  |Multiplier|
>                                ====>|Cos(x)|=>|          |=>Img
>                                     |______|  |__________|
>                                                  ^    ^
>                                             mod. a    b
> 
> I've working the phase accumulator yet.(It's the easier, I know)
> 
> My question is about how to syntesize the Sin and Cos functions
> without a lookup table to save the external ram I will need.
> 
> Also I will need a complex multiplier to mix both vectors,
> and don't know how to make it. So I'm requesting help, or
> any pointer to where could I find it.

Luis,

You didn't say how wide your data path is, but for anything practical,
the XC5202 is way too small. For the purposes of education, you might be
able to do something useful with just a very few bits. Perhaps 4 would
fit. The phase accumulator is easy in a Xilinx part, but the multipliers
are not so easy and I believe there are some good design methods for the
sin and cos based on cordic. But I can't help you with that. But there
are many others here who are very capable that I am sure you will be
hearing from. 

But first you need to decide if a very narrow data path will suffice for
your needs or if you need to go to a larger part. 




-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 17285
Subject: Re: Digital modulator? Synthesisable Sin(x) funct.
From: Ray Andraka <randraka@ids.net>
Date: Sat, 17 Jul 1999 10:47:52 -0400
Links: << >>  << T >>  << A >>
The way you show is the expensive way of doing it, since you need both a
quadrature sinusoid generator and a complex multiplier.  Considering that
the more efficient way of doing multiplication in an FPGA involves lookups,
and ostensibly the sin and cosine require look=ups too, one simplification
is to combine the LUTs.  If the required phase resolution is low, then you
can use a "limited set constant multiplier" with partial product expansion.
In other words, you'd have a partial products table driven by the outputs of
the phase accumulator and subsets of the bits in the signal to be
modulated.  You then need to add the partials together in an adder tree or
scaling accumulator.  The approach depends on the data rate too.  This
approach loses viability as the phase resolution, the input width and/or the
data rate is increased.  Note also, the hardware needs to be duplicated for
complex modulation.  Check the multiplier page under the DSP section of my
website for a tutorial on multiplication in FPGAs.

The look up table modulator can be combined with a 2's complement and a
controllable inversion on the phase input to take advantage of the symmetry
in the sinusoid without making the table bigger.  Still, for most
applications the look up table does not map well to an FPGA because of the
small LUT size available.

If you can lock your sample rate to 4x the modulation frequency, then the
modulator becomes a mux and a controllable 2's complement because you can
chose the phase angles of the sampled sinusoid  to be 0,90,180 and 270.
This means that you are multiplying the input signal by the sequence
1,0,-1,0,... for the I output and by 0,1,0,-1 for the Q output.

If you need more phase resolution, or can't lock the local oscillator to the
sample clock and since you need a complex sinusoid, and you are modulating
it, the best approach is a CORDIC rotator.  CORDIC is an iterative shift-add
algorithm for rotating vectors in a plane.  This is essentially all that
modulation by a complex sinusoid does.  Look on my website under the
publications page for the "Survey of Cordic algorithms for FPGA based
computers" paper for a tutorial on CORDIC with a slant toward FPGA
implementation.  The number of CORDIC iterations will determine the phase
resolution of your modulator.

The XC5000 series is not the best choice for DSP applications as its carry
chain structure is quite weak (requires two CLBs for each bit in an adder).
The 5202 only has an 8x8 array of CLBs, so you've got a maximum of 32bits of
adds in it.  That ain't much; for higher data rates you'll find you need
considerably more than that for any of the above approaches except the 4x
modulation frequency one.  If your data rate requirement is really low, you
might be able to fit a bit serial iterative CORDIC in there, but it will be
really tight.  If you move to a spartan series device, you can get much
higher data rates and much better utilization of the FPGA.  A 10 iteration
pipelined CORDIC modulator with 12 bits of precision will easily fit in an
XCS20 and can support sample rates better than 100MS/S with floorplanning.

Luis Yanes wrote:

> Hello.
>
> I'll like to syntesize a digital modulator within a Xilinx XC5202
> fpga, since I purchased a few ago the Foundation package to
> learn and homebrewing.
>
> The diagram of what I intend to do, could be something like:
>
> phase_offset==============           ______    __________
>         _______________   |         |      |  |          |
>        |    _________  |  |    ====>|Sin(x)|=>|          |=>Real
>        V   |         | |  V   |     |______|  |Complex   |
> freq=>(+)=>|Phase_acc|='>(+)=>|      ______   |          |
>            |_________|        |     |      |  |Multiplier|
>                                ====>|Cos(x)|=>|          |=>Img
>                                     |______|  |__________|
>                                                  ^    ^
>                                             mod. a    b
>
> I've working the phase accumulator yet.(It's the easier, I know)
>
> My question is about how to syntesize the Sin and Cos functions
> without a lookup table to save the external ram I will need.
>
> Also I will need a complex multiplier to mix both vectors,
> and don't know how to make it. So I'm requesting help, or
> any pointer to where could I find it.
>
> Thanks.
> 73's de Luis
>
> mail: melus@esi.us.es
> Ampr: eb7gwl.ampr.org
> http://www.esi.us.es/~melus/   <- Homebrewed Hardware Projects with PCBs



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17286
Subject: Re: fpga 10k50 and up prototype with a/d d/a
From: "Mark Grindell" <petejackson7@hotmail.com>
Date: Sat, 17 Jul 1999 15:48:10 +0100
Links: << >>  << T >>  << A >>
You might be best advised to make one up youself. You might select some
chips which you know a fair bit about, choose a configuration using general
I/O pins and then send a coupld of hours or so with Protel, and hey-presto -
you've done it yourself!

There is a catch. Depending on your application complexity, commiting your
pinouts like this can make the project a bit more difficult to fit -
commiting the pins often does this. Given this, and guessing that your
eventual target is a 10K50, I would (in your situation) go for a much bigger
device, which would give me loads of room, and make routing a bit easier and
swifter. I would try a 10K100 myself - and then you *know* you won't run out
of room.

Goodness me, for a protype they're cheap enough. I might even jump to a
10K130 if I was feeling really reckless...



Abraham Roth <s3279466@techst02.technion.ac.il> wrote in message
news:37850f9b.0@news.barak.net.il...
> Hi
> I am looking for a prototype board with altera 10k50 and up,
> some memory, and  4 analog in (12b a/d 150 khz each) 2 analog out(12 b
> d/a),
> some interfacing vhdl/ahdl drivers.
> download with at least byteblaster.
>
>
>
>


Article: 17287
Subject: Re: fpga 10k50 and up prototype with a/d d/a
From: Ray Andraka <randraka@ids.net>
Date: Sat, 17 Jul 1999 11:05:45 -0400
Links: << >>  << T >>  << A >>
You gotta be careful going with the bigger device in Altera.  They get slower as
they get bigger.  Altera is pretty sensitive to pin locking if you fill the
device past around 50%, so you do have to be careful.

Mark Grindell wrote:

> You might be best advised to make one up youself. You might select some
> chips which you know a fair bit about, choose a configuration using general
> I/O pins and then send a coupld of hours or so with Protel, and hey-presto -
> you've done it yourself!
>
> There is a catch. Depending on your application complexity, commiting your
> pinouts like this can make the project a bit more difficult to fit -
> commiting the pins often does this. Given this, and guessing that your
> eventual target is a 10K50, I would (in your situation) go for a much bigger
> device, which would give me loads of room, and make routing a bit easier and
> swifter. I would try a 10K100 myself - and then you *know* you won't run out
> of room.
>
> Goodness me, for a protype they're cheap enough. I might even jump to a
> 10K130 if I was feeling really reckless...
>
> Abraham Roth <s3279466@techst02.technion.ac.il> wrote in message
>



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17288
Subject: Chemical FPGAs
From: Brad Taylor <blt@cmln.com>
Date: 17 Jul 1999 12:30:39 PDT
Links: << >>  << T >>  << A >>
Hi - 

The article below was the front page headline of the San Francisco Chronicle on
Thursday. I thought it might also be of interest to the readers of this group.
It describes work by Philip Kuekes, a computer architect at          
Hewlett-Packard, and others who have constructed a configurable switch based on
carbon nanotubes coated with rotaxane molecules. In effect, the rotaxane
molecules act as "anti-fuse" links between the bucky tubes. It's still a way off
from being a real device however. Philip Kuekes is a long time FPGA researcher
and developer of the reconfigurable Teramac system at HP. 

"Tiny Switch Could Shrink Computers Microscopic machines with the power of a
billion PCs"

http://www.sfgate.com/cgi-bin/article.cgi?file=/chronicle/archive/1999/07/16/MN36688.DTL

-
Brad

I also have a small web page which has some random links in this area at:
http://members.tripod.com/~blt_/nano_electronics.html
Article: 17289
Subject: Frequency Multiplier in XC4000
From: "bill morris" <bill_morris99@hotmail.com>
Date: Mon, 19 Jul 1999 02:00:54 +0100
Links: << >>  << T >>  << A >>

Has anybody implemented a frequency multiplier in XC4k? I need to implement
a frequency multiplier by 2^n
(n=1,2,3,4). I know that VIRTEX contain built-in DLL which can implement
that but unfortunately I have to do it on XC4kE series.

Please help!


Article: 17290
Subject: Frequency multiplier in XC4000
From: "bill morris" <bill_morris99@hotmail.com>
Date: Mon, 19 Jul 1999 11:22:08 +0100
Links: << >>  << T >>  << A >>
Has anybody tried to implement a frequency multiplier on XC4k? I need to
implement a frequency multiplier by 2^n (n=1,2,3,4). I know that VIRTEX
contain DLL's which can implement that but unfortunately I have to use
XC4kE.

Please help!


Article: 17291
Subject: Frequency multiplier in XC4000
From: "bill morris" <bill_morris99@hotmail.com>
Date: Mon, 19 Jul 1999 11:36:06 +0100
Links: << >>  << T >>  << A >>
Has anybody tried to implement a frequency multiplier in XC4k? I need to
implement a frequency multiplier by 2^n (n=1,2,3,4). I know VIRTEX contain
DLL's which can implement that but unfortunately I have to use XC4kE.

Please help!


Article: 17292
Subject: License sharing for synopsys/cadence/modeltech
From: chipfactory@hotmail.com
Date: Mon, 19 Jul 1999 16:15:15 GMT
Links: << >>  << T >>  << A >>
Hi Folks:
When we read the documentation for Synopsys we found out that 
a license server can also be somewhere in the internet. Now we 
came up with the idea to connect our Synopsys/Cadence/Modeltech 
license server to the internet and share our licenses with others. 
During the night here in Europe our licenses are not used.
Would there someone be interested and is this legal?

Best regards
Jack

email: chipfactory@hotmail.com

Article: 17293
Subject: Re: Frequency multiplier in XC4000
From: "Earthlink News" <evansamuel@earthlink.net>
Date: Mon, 19 Jul 1999 12:13:05 -0500
Links: << >>  << T >>  << A >>
I have created a simple multiplier in the 4k device.  Simply connect a
number of gates together and loop the output of the last buffer to the first
invertor (use a nand gate for enable/disable for the first gate).  The
frequency is determine by the CLB delay of the device you are using (# of
invertors X CLB delay X 2 = Period).  Use the output of the last gate in the
chain for your output.  Use the output to also clock a counter.  When the
counter reaches 4, disable the first stage NAND gate and keep it in its
current state.  Use the master clock to enable the next sequence of clock
pulses. The last pulse out of the will have a long or short half cycle until
the next master clock.

It also important to RLOC the invertors to prevent excessive path delay
between invertors and limit the jitter.

Beware,  frequency will vary between devices.  If your frequency is not to
high, you should be able to find a compromise in the number of invertors
required

email: evansamuel@earthlink.net


bill morris wrote in message <7muv2r$5jg$2@news.qub.ac.uk>...
>Has anybody tried to implement a frequency multiplier on XC4k? I need to
>implement a frequency multiplier by 2^n (n=1,2,3,4). I know that VIRTEX
>contain DLL's which can implement that but unfortunately I have to use
>XC4kE.
>
>Please help!
>
>




Article: 17294
Subject: Re: Frequency multiplier in XC4000
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 19 Jul 1999 10:20:21 -0700
Links: << >>  << T >>  << A >>
It depends on the quality of the frequency you want to generate.
If you need to generate a continuous stable frequency, your only choice is an
external voltage-controlled oscillator, an internal phase comparator, and a
counter.
If your frequency has no need to be constant, but can be a series of unevenly
distributed pulses, then you can differentiate the incoming clock and generate a
controlled series of glitches. It works fine for clock doubling ( as shown in
previous editions of the Xilinx data book), but becomes a doubtful proposition
for larger numbers. Unless your frequencies are very low...

You can, for example, build an internal gated oscillator that runs at 10 to 100
MHz ( and varies with temperature and voltage ). This can generate bursts of
pulses with the right average number of pulses, but it will not be an even,
continuous frequency.

Peter Alfke, Xilinx Applications

bill morris wrote:

> Has anybody tried to implement a frequency multiplier on XC4k? I need to
> implement a frequency multiplier by 2^n (n=1,2,3,4). I know that VIRTEX
> contain DLL's which can implement that but unfortunately I have to use
> XC4kE.
>
> Please help!

Article: 17295
Subject: Verilog FAQ
From: rajesh52@hotmail.com
Date: Mon, 19 Jul 1999 18:38:57 GMT
Links: << >>  << T >>  << A >>
Greetings
This is semimonthly announcement of Verilog FAQ.

Verilog FAQ is located at
http://www.angelfire.com/in/verilogfaq/

Alternate Verilog FAQ is an attempt to gather the answers
to most Frequently Asked Questions about Verilog HDL in
one place. It also  contains list of publications, services,
and products.

Alternate Verilog FAQ is divided into three logical parts.

Part 1 : Introduction and misc. questions
Part 2 : Technical Topics
Part 3 : Tools and Services

What's New section outlines the changes in different versions
and announcements. Links connects you to related informative
links in internet.

Your suggestions to make this FAQ more informative are welcome.

Rajesh Bawankule
(Also Visit Verilog & EDA Page :
http://www.angelfire.com/in/rajesh52/verilog.html )


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17296
Subject: Re: Frequency multiplier in XC4000
From: Ray Andraka <randraka@ids.net>
Date: Mon, 19 Jul 1999 14:43:31 -0400
Links: << >>  << T >>  << A >>
I suppose you could construct a delay lock loop in CLBs, or for finer delay
steps with the carry chain to generate your clock.  It would definitely need to
be RLOC'd and depending on jitter tolerance may need some hand routing.  I
haven't tried this, but have thought about it.  It could work.

Earthlink News wrote:

> I have created a simple multiplier in the 4k device.  Simply connect a
> number of gates together and loop the output of the last buffer to the first
> invertor (use a nand gate for enable/disable for the first gate).  The
> frequency is determine by the CLB delay of the device you are using (# of
> invertors X CLB delay X 2 = Period).  Use the output of the last gate in the
> chain for your output.  Use the output to also clock a counter.  When the
> counter reaches 4, disable the first stage NAND gate and keep it in its
> current state.  Use the master clock to enable the next sequence of clock
> pulses. The last pulse out of the will have a long or short half cycle until
> the next master clock.
>
> It also important to RLOC the invertors to prevent excessive path delay
> between invertors and limit the jitter.
>
> Beware,  frequency will vary between devices.  If your frequency is not to
> high, you should be able to find a compromise in the number of invertors
> required
>
> email: evansamuel@earthlink.net
>
> bill morris wrote in message <7muv2r$5jg$2@news.qub.ac.uk>...
> >Has anybody tried to implement a frequency multiplier on XC4k? I need to
> >implement a frequency multiplier by 2^n (n=1,2,3,4). I know that VIRTEX
> >contain DLL's which can implement that but unfortunately I have to use
> >XC4kE.
> >
> >Please help!
> >
> >
>
>  [Image]



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17297
Subject: Re: License sharing for synopsys/cadence/modeltech
From: jdl@user2.teleport.com (Jay Lessert)
Date: 19 Jul 1999 12:16:21 -0700
Links: << >>  << T >>  << A >>
In article <37964ef8.605363216@news.maltanet.net>,
 <chipfactory@hotmail.com> wrote:
>Hi Folks:
>When we read the documentation for Synopsys we found out that 
>a license server can also be somewhere in the internet. Now we 
>came up with the idea to connect our Synopsys/Cadence/Modeltech 
>license server to the internet and share our licenses with others. 
>During the night here in Europe our licenses are not used.
>Would there someone be interested and is this legal?
>
>Best regards
>Jack
>
>email: chipfactory@hotmail.com
>

For what it's worth, you'll find that Synopsys, Cadence and Mentor
will take a dim view of this proposal, for all the obvious reasons.

If formally asked, their corporate counsel will almost certainly claim
it is not legal.

The matter of whether it actually *is* legal or not would be for the
courts to decide; since this sort of thing is nearly always settled out
of court, I'm not aware of any definitive precedents.

-- 
Jay Lessert              Portland, Oregon USA             jdl@teleport.com
Article: 17298
Subject: Re: License sharing for synopsys/cadence/modeltech
From: drogoff@home.com (David Rogoff)
Date: Mon, 19 Jul 1999 19:41:43 GMT
Links: << >>  << T >>  << A >>
Cadence and Synopsys (and probably others) have terms in their license
agreements and prohibit license servers from being more than a specified
distance from the machine requesting the license.  This makes it against the
rules to share licenses between offices of the same company if they are in
different cities!  I don't think that there is anything that can technically
stop you from doing it, but you are breaking a legal contract.

 David

jdl@user2.teleport.com (Jay Lessert) wrote:

>In article <37964ef8.605363216@news.maltanet.net>,
> <chipfactory@hotmail.com> wrote:
>>Hi Folks:
>>When we read the documentation for Synopsys we found out that 
>>a license server can also be somewhere in the internet. Now we 
>>came up with the idea to connect our Synopsys/Cadence/Modeltech 
>>license server to the internet and share our licenses with others. 
>>During the night here in Europe our licenses are not used.
>>Would there someone be interested and is this legal?
>>
>>Best regards
>>Jack
>>
>>email: chipfactory@hotmail.com
>>
>
>For what it's worth, you'll find that Synopsys, Cadence and Mentor
>will take a dim view of this proposal, for all the obvious reasons.
>
>If formally asked, their corporate counsel will almost certainly claim
>it is not legal.
>
>The matter of whether it actually *is* legal or not would be for the
>courts to decide; since this sort of thing is nearly always settled out
>of court, I'm not aware of any definitive precedents.

Article: 17299
Subject: Re: License sharing for synopsys/cadence/modeltech
From: gogo@netcom.com (R. Mark Gogolewski)
Date: 19 Jul 1999 20:06:17 GMT
Links: << >>  << T >>  << A >>
I may regret writing this, but this discussion and
previous ones similar to it have made me curious:

Let's say that the license agreements didn't specifically
have wording to make sure that this usage is restricted.
IMO, I would think that everyone in this industry - designers
and vendors - would agree that software licenses were
never priced with this type of usage in mind.

Does it _have_ to strictly be in violation of a license
agreement before it feels like stealing?  Let's be
realistic, if everyone did this, vendors would have to
either technically do something to stop it, or drastically
change the price model.

Thoughts?

Mark


In article <379f7c9e.221323198@news.rdc2.occa.home.com>,
David Rogoff <drogoff@home.com> wrote:
>Cadence and Synopsys (and probably others) have terms in their license
>agreements and prohibit license servers from being more than a specified
>distance from the machine requesting the license.  This makes it against the
>rules to share licenses between offices of the same company if they are in
>different cities!  I don't think that there is anything that can technically
>stop you from doing it, but you are breaking a legal contract.
>
> David
>
>jdl@user2.teleport.com (Jay Lessert) wrote:
>
>>In article <37964ef8.605363216@news.maltanet.net>,
>> <chipfactory@hotmail.com> wrote:
>>>Hi Folks:
>>>When we read the documentation for Synopsys we found out that 
>>>a license server can also be somewhere in the internet. Now we 
>>>came up with the idea to connect our Synopsys/Cadence/Modeltech 
>>>license server to the internet and share our licenses with others. 
>>>During the night here in Europe our licenses are not used.
>>>Would there someone be interested and is this legal?
>>>
>>>Best regards
>>>Jack
>>>
>>>email: chipfactory@hotmail.com
>>>
>>
>>For what it's worth, you'll find that Synopsys, Cadence and Mentor
>>will take a dim view of this proposal, for all the obvious reasons.
>>
>>If formally asked, their corporate counsel will almost certainly claim
>>it is not legal.
>>
>>The matter of whether it actually *is* legal or not would be for the
>>courts to decide; since this sort of thing is nearly always settled out
>>of court, I'm not aware of any definitive precedents.
>




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