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Messages from 17325

Article: 17325
Subject: Re: Frequency multiplier in XC4000
From: mushh@jps.net (David Decker)
Date: Wed, 21 Jul 1999 07:11:59 GMT
Links: << >>  << T >>  << A >>
It is possible to make a VCO, as Peter suggests, out of a varactor
diode with the amplification supplied by a Xilinx inverter. 
The Xilinx also can be used for the digital divider, and for the phase
comparator. Only a few external passive parts to integrate the phase
comparator's output and a varactor diode are needed to complete a PLL.

No active external passive parts are needed. 

I have recently used a Xilinx Spartan chip in this manor to multiply a
32kHz watch Xtal by 64, but the internal divide ratio could well have
been variable.
The only problems encountered were:
1) The Spartan's 300mV input hysteresis prevented also making the
32kHz reference xtal oscillator out of only passive components.

2) About 500uA of ICC was wasted, presumably by the input amps
attached to the outputs from the phase comparator, driving the
external integrating PLL filter. 
Explanation: To save power, I used the type of phase comparator that
emits positive and negative glitches. These glitches must be
integrated before application to the veractor. Most of the time these
two outputs are in a TriState condition. When in TriState, these
outputs see the DC voltage controlling the VCO. Unavoidably, within
the Xilinx, there are CMOS inputs attached to these output pins, and I
believe it was these unused CMOS inputs that were wasting the extra
ICC. 
To fix the problem I changed the phase comparator outputs to be Low Z
full height digital signals then isolated them from the 'middle'
voltage of the integrator with Schottky diodes. 

If you are not worried about saving every last uA, you could just
drive the integrator directly with one combined up/down/tristate pin,


Peter Alfke <peter@xilinx.com> wrote:

>It depends on the quality of the frequency you want to generate.
>If you need to generate a continuous stable frequency, your only choice is an
>external voltage-controlled oscillator, an internal phase comparator, and a
>counter.

Dave Decker

Please use only one 'h' in mush. I'm trying to reduce the spam.



"Animals .  .  . are not brethren they are not 
underlings;  they are other nations, 
caught with ourselves in the net of life and time, 
fellow prisoners of the splendor and travail of 
the earth."
Henry Beston -  The Outermost House
Article: 17326
Subject: Synplify - Optimizing Out A Bus
From: david_hinds@my-deja.com
Date: Wed, 21 Jul 1999 08:05:52 GMT
Links: << >>  << T >>  << A >>
Hi,

Has any one seen the following;

I have an 8 bit data bus which has two explicitly
tied bits (one high and one low). As these are
assigned in a registered process, and set to zero
under reset conditions, one is optimized out which
is reasonable. However, this in turn seems to be
removing the entire data bus - which is not
reasonable!

Has anyone experienced Synplify behaving in this
way before?

David Hinds.


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17327
Subject: Re: Solaris vs. NT
From: Thomas Reinemann <thomas.reinemann@mb.uni-magdeburg.de>
Date: Wed, 21 Jul 1999 10:11:36 +0200
Links: << >>  << T >>  << A >>
Mark Kinsley wrote:

> I would hate to overlook any important issues which should be
> considdered in making this decision, so if you have any input please
> mail it to me / post it to the group.

I'm using or more exact I've to use NT :-( on a PII (333MHz 128 MB RAM) and I
suffer from it. 

If I simulate bigger things the system seems to be stoned, after the end of
simulation time HD activity will go on some minutes. Not mentioned simulator
crashs, but this could depend on Aldec's Active VHDL simulator.

You will get big problems, if one program needs Service Pack x and another needs
SPy. If you want to administrate a computer, you must go to it, close all
application and then you can do your work, carefully.

How about eMail or Web, then you will need an NT-Server.

There is no useful clustering available, only 2 or 4 computers can work
together.

You should know, some only NT-companies (e.g. VeriBest) will port their
applications to Unix. They will be their reasons.


Here are some links to Unix vs. NT

http://www.unix-vs-nt.org/kirch/
http://www.ugraf.com/unix-nt/

and to NT security or its lack

http://www.ntshop.net/
http://www.technotronic.com/microsoft.html


Bye Tom!
Article: 17328
Subject: Synplify - Optimizing out a Bus.
From: david_hinds@my-deja.com
Date: Wed, 21 Jul 1999 08:18:05 GMT
Links: << >>  << T >>  << A >>
Hi,

Has any one seen the following;

I have an 8 bit data bus which has two explicitly
tied bits (one high and one low). As these are
assigned in a registered process, and set to zero
under reset conditions, one is optimized out which
is reasonable. However, this in turn seems to be
removing the entire data bus - which is not
reasonable!

Has anyone experienced Synplify behaving in this
way before?

David Hinds.


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17329
Subject: Re: Xilinx/Synopsys License Problem
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 21 Jul 1999 09:00:10 -0400
Links: << >>  << T >>  << A >>
Mark Condit wrote:
> 
> I think I may know what your problem is.  The Foundation series software
> wants to be node locked, using either your hard disk serial number or your
> ethernet address.  The problem is that the software doesn't recognize hard
> disk serial numbers that start with a zero "0".  I have 1.5i and have been
> on temp licenses for the last 8 months.  I'm told Xilinx is working the
> problem, but no date for a fix yet. Good luck.

This is easy enough to work around. Just change your serial number so
that it does not begin with a '0' and ask for a new license file. I have
set my SN to a known value in every machine I have used. This lets me
not have to deal with new license files every time I need to jack up my
software and put a new machine under it. I have done this about three
times before and I am looking at getting a laptop now. So this will be
machine number four to have been run on the same license file. 

Most vendors won't use this license method because they know that you
can also use this method to run multiple machines on the same license
concurrently. But it is sure a lot easier for me to maintain. 

The NIC license is a problem for laptops I have been told, because they
power down the hardware when it has not been used in a while. So when
the NIC number is checked they get a time out and never go back to check
it again when the hardware is back up. 

So the only portable solution left (as far as I know) is a dongle, and I
dislike putting thousands of dollars (more than the cost of the laptop)
into an object smaller than a deck of cards. It is just too easy to lose
or have ripped off. 

With the Pentium III incorporating an internal SN, look for PIII
processors being required for licensing soon!


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 17330
Subject: Free Filter Synthesis Software
From: "Gareth Jones" <gareth@systolix.co.uk>
Date: Wed, 21 Jul 1999 14:10:40 +0100
Links: << >>  << T >>  << A >>
Systolix have just released a free version of their windows based filter
sysnthesis tool FilterExpress.

FilterExpress supports the design and analysis of IIR, FIR and multirate FIR
filters.

The free version of FilterExpress is fully functional and saves coefficient
vaules to a simple text file suitable for export to other tools. It is now
available for download from Systolix home site http://www.systolix.co.uk




Article: 17331
Subject: Re: Solaris vs. NT
From: wen-king@myri.com (Wen-King Su)
Date: 21 Jul 1999 06:17:21 -0700
Links: << >>  << T >>  << A >>
In a previous article Jerry Zdenek <zdenekjs@interaccess.com> writes:
:
:I really believe in automating as much of the process as possible;  That
;way, some user (usually me) can't screw it up or forget a step.  We do
:post-layout simulation with an EDIF netlist, and to jump back and forth
;between the unix ws (for everything but the Maxplus2 fitter) and the PC
:just to fit the FPGA is very annoying. 
;
:What I like to be able to do is make some change to the VHDL, and kick
;off the entire process again *without* having to be there.  It's so much
:more efficient, esp. if the design is large.  What I define is the
;easiest is to make a change to the source and then walk away until I
:have simulation results available.

That is exactly the way I feel.  I have an NT box on the side in my office
just so I can, after doing everything on Unix, turn to the side to click
buttons to run the FPGA fitter.   And that NT box, is the only reason why
I have to be physically in my office to get work done.  I could have done
everything else remotely from home or beach otherwise.  That is very
annoying, and I have given up using that particular FPGA for a while.
Nowaday I keep that NT box turned on in my office just to keep my office
warm and to generate some white noise to suppress my tinnitis.

Windows turn people into part of the machine, it expects you to be there
just as it expects the hard drive to be there all the time, and that is
wrong. 
Article: 17332
Subject: Re: Solaris vs. NT
From: husby@fnal.gov (Don Husby)
Date: Wed, 21 Jul 1999 13:48:34 GMT
Links: << >>  << T >>  << A >>
Mark Kinsley <mkinsley@xs4all.nl> wrote:
> 7. Anything else i should be looking at..

Availability of other NT-based tools like word processors,
graphics packages, software development tools, and, especially
for you, newsreaders with spell checkers. :)

Yes, some of these tools are available for Unix, but generally
they are better, cheaper, and sooner for Windows.



--
Don Husby <husby@fnal.gov>                        Phone: 630-840-3668
Fermi National Accelerator Lab                      Fax: 630-840-5406
Batavia, IL 60510
Article: 17333
Subject: Special Issue on Reconfigurable Systems
From: gordon@dcs.ed.ac.uk (Gordon Brebner)
Date: 21 Jul 1999 15:46:26 GMT
Links: << >>  << T >>  << A >>

IEE Proceedings - Computers and Digital Techniques

Special Issue on Reconfigurable Systems

Editors: Gordon Brebner (Edinburgh, U.K),
         Brad Hutchings (Brigham Young, U.S.A.)

 

CALL FOR PAPERS

Deadline: 31 August 1999

 
The special issue is scheduled for publication in May 2000.  Papers
must present original work, from either academic or industrial
laboratories, and may focus on theory, design, simulation or
modelling, including applications of existing techniques in new or
novel situations.

Particular topics of interest include:

      Computational models of reconfigurability 
      Custom computing machines 
      Evolvable and adaptable systems 
      Incorporating reconfigurability in algorithms 
      Novel design methodologies and tools 
      Novel FPGA and system architectures 
      Practical benefits of reconfigurability 
      Run-time reconfigurable circuitry

All papers will be rigorously refereed, with the expectation that
reviewing will be completed by mid-December 1999, and with final
versions of accepted papers due by 29 February 2000.  The approximate
length of papers should be 12-16 double-spaced pages (or 3000 words)
plus 10-14 illustrations as appropriate.

For further information about the special issue, or to express
interest in submitting a paper for the special issue, please contact
editor Gordon Brebner (e-mail gordon@dcs.ed.ac.uk).

For information about the journal, see the Web page at
http://www.iee.org.uk/publish/journals/profjrnl/ieeproc.html.

This Web page also includes submission instructions for papers
(click on "Authors" at the top of the page).
Article: 17334
Subject: C language to programmable logic
From: David Norton <davidnorton@my-deja.com>
Date: Wed, 21 Jul 1999 15:58:13 GMT
Links: << >>  << T >>  << A >>
Hi all,

I have a routine in C language that does masive amounts of data
crunching.  I am looking for a way to take that routine and implement
it with programmable logic to speed things up.

Anyone done this sort of thing before?  Suggestions for tools or
approach to take?

Thanks

David


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17335
Subject: Re: Synplify - Optimizing Out A Bus
From: "Lewis, Mike" <wilma@americasm01.nt.com>
Date: Wed, 21 Jul 1999 13:11:55 -0400
Links: << >>  << T >>  << A >>
I've encountered several instances where synplify is very "aggresive"
in optimizing stuff out .... resulting in functional errors. The one way
to counter this is to add the syn_preserve (registers) or syn_keep (combinatorial)
against the signals that are being optimized out.

reg  R_pulsea  /* synthesis syn_preserve=1 */;

Mike



david_hinds@my-deja.com wrote:

> Hi,
>
> Has any one seen the following;
>
> I have an 8 bit data bus which has two explicitly
> tied bits (one high and one low). As these are
> assigned in a registered process, and set to zero
> under reset conditions, one is optimized out which
> is reasonable. However, this in turn seems to be
> removing the entire data bus - which is not
> reasonable!
>
> Has anyone experienced Synplify behaving in this
> way before?
>
> David Hinds.
>
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.

Article: 17336
Subject: Re: C language to programmable logic
From: timothyc@ribbit.CS.Berkeley.EDU (Tim Callahan )
Date: 21 Jul 1999 20:21:33 GMT
Links: << >>  << T >>  << A >>
In article <7n4qmc$vu3$1@nnrp1.deja.com>,
David Norton  <davidnorton@my-deja.com> wrote:
>
>I have a routine in C language that does masive amounts of data
>crunching.  I am looking for a way to take that routine and implement
>it with programmable logic to speed things up.
>
>Anyone done this sort of thing before?  Suggestions for tools or
>approach to take?


For the fun of it, I'd like to run it through my C - to - Garp
(microprocessor + FPGA-based accelerator on a chip) compiler.
If your code fragment is small enough you can even run it
through yourself using the on-line demo at 
http://www.cs.berkeley.edu/projects/brass/garpcc_demo/

However, this won't actually help you get numbers quickly,
since there's no actual silicon for Garp yet, and a 
simluated Garp is a lot slower than a real workstation!
(note - the demo doesn't include simulation anyway, for security
reasons).  Also, the Garp array architecture is unique, so you 
won't be able to use the generated configuration files 
with any existing Xilinx-based platform.

But, if it's possible for you to send me the source and a
data set, I can tell you how much speedup you COULD get
using Garp, IF it existed.

	Tim


------------------------------------------------------------------------
Tim Callahan                      415 Soda Hall, (510) 643-4203
timothyc@cs.Berkeley.EDU          http://www.cs.berkeley.edu/~timothyc/
------------------------------------------------------------------------
-- 

------------------------------------------------------------------------
Tim Callahan  ティム カラハン	  timothyc@cs.Berkeley.EDU
441 Soda Hall, (510) 643-8229	  http://http.cs.berkeley.edu/~timothyc/
Article: 17337
Subject: Re: C language to programmable logic
From: Ray Andraka <randraka@ids.net>
Date: Wed, 21 Jul 1999 16:44:17 -0400
Links: << >>  << T >>  << A >>
It depends on how your C code is written.  There are people who have done
a considerable amount of work looking at C to FPGA compilers, but AFAIK,
these require a very specific syntax.  Personally, I've had better
results using the C code as an executable specification for a design,
then creating hardware using either schematics or VHDL to match that
design.

David Norton wrote:

> Hi all,
>
> I have a routine in C language that does masive amounts of data
> crunching.  I am looking for a way to take that routine and implement
> it with programmable logic to speed things up.
>
> Anyone done this sort of thing before?  Suggestions for tools or
> approach to take?
>
> Thanks
>
> David
>
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17338
Subject: Re: Xilinx/Synopsys License Problem
From: Dave Vanden Bout <devb@xess.com>
Date: Wed, 21 Jul 1999 19:48:37 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------3112CFD19539F98515F0C042
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

Nicholas:

Did you get your Foundation to work?  I don't think you can key off of the D: drive.  You must use the C: drive or your ethernet id #.  You can't change your license file manually.  You will have to go to the xilinx web site and generate a new license with the appropriate C: or ethernet id key.  You can generate up to three licenses at the xilinx site before you get locked out.  Let me know if you run into this problem and I will try to get you another xilinx serial number.

Email us at xess.com or send questions to the xsboard-users mailing list if you have problems like this in the future.  We don't have xilinx's godly power to generate license files but sometimes we can point you in the right direction.

Nicholas Brown wrote:

> Hello,
>     I have just purchased the Xilinx Foundation Series 1.5 Student
> Edition, a XS40 and a XS95 board  from Xess Corp. Unfortunately, the
> license software dosnt seem to work and Xilinx now claims that they
> dont support the student edition. I was hoping that someone here knows
> a solution to the problem.
>     Everything seems to work except the VHDL synthesis. When attempting
> to synthesize a VHDL entry I get:
>
> Pcm :Synopsys server initialization
> Dpm :Invalid Host(-9,57)
> Pcm :Cannot find a valid license for Synopsys synthesis
>
>     I have spent several hours attempting to get this to work. Initially
> I
> used Drive number 0B87-7DBF with the Xilinx license generator which is
> the id for the D drive where the Foundation Series software resides (as
> reported by Vol C: in DOS.)
> This did not work, so I manually changed the license.dat file so the id
> was 1878-08CD which is the id the master drive, C:. This did not work.
> Then I downloaded Hostid.exe from Synopsys which gave the host id as
> f8d709c10000. This also did not work. The Autoexec.bat dose contain:
> C:\flexlm\license.dat. Any insight to the problem would be appreciated.
> Thanks in advance
> -Nick

--------------3112CFD19539F98515F0C042
Content-Type: text/x-vcard; charset=us-ascii;
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Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
 filename="devb.vcf"

begin:vcard 
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com/FPGA
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;-1
fn:Dave Vanden Bout
end:vcard

--------------3112CFD19539F98515F0C042--

Article: 17339
Subject: Xilinx Foundation Beginner Question
From: Nicholas Brown <nbrownNOT@gulfaccess.com>
Date: Wed, 21 Jul 1999 20:27:52 -0400
Links: << >>  << T >>  << A >>
Hello,
Im just starting out with Xilinx Foundation 1.5 and having a problem
with implementing schematic flow.
When I "Create Netlist" from the schematic editor, I get the warning
"Netlist creation warning: terminals for top level schematic", but the
netlist dose get generated correctly. There are no warnings for the
Integrity test or Export netlist. At the implementation window I get the

message "Starting Constructive Placer.  REAL time: 12 secs" (during the
place and route portion) and nothing seems to happen after that.
Everything was entered as the text book describes. Any suggestions as to

whats wrong ?
Any insight would be appreciated. Thanks in advance.
-Nick

Article: 17340
Subject: Re: Solaris vs. NT
From: Zoltan Kocsi <root@127.0.0.1>
Date: 22 Jul 1999 10:51:29 +1000
Links: << >>  << T >>  << A >>
husby@fnal.gov (Don Husby) writes:

> Availability of other NT-based tools like word processors,
> graphics packages, software development tools, and, especially
> for you, newsreaders with spell checkers. :)
> 
> Yes, some of these tools are available for Unix, but generally
> they are better, cheaper, and sooner for Windows.

While I would not dare to enter the "which wordprocessor is better"
arena, (even though I used some on unix when NT wasn't even dreamt of)
I'd be rather interested in the SW development tools which are better, 
cheaper and sooner on Windows than on unix.

One would think that using GNU tools would make the 'cheaper' issue
rather moot. In addition, a few thoughts might arise:
Unix was designed by SW developers who wanted to make a very creative
development environment - IMHO they achieved their goal. Much much
before Bill Gates dropped out from school. Unix has been developing since
and this process was mostly controlled by people who wanted to create an 
even more creative and productive development environment.

Mind you, what I see on the net is that SW developers on Windows quite
often use unix tools ported to Windows. Would that be an indication
about that better/sooner/cheaper thingy ?

By the way, what do you exactly do with graphics packages when you 
design FPGAs ? 

Regards,

Zoltan

-- 
+------------------------------------------------------------------+
| ** To reach me write to zoltan in the domain of bendor com au ** |
+--------------------------------+---------------------------------+
| Zoltan Kocsi                   |   I don't believe in miracles   |  
| Bendor Research Pty. Ltd.      |   but I rely on them.           |
+--------------------------------+---------------------------------+
Article: 17341
Subject: Re: fpga 10k50 and up prototype with a/d d/a
From: Ray Andraka <randraka@ids.net>
Date: Wed, 21 Jul 1999 21:32:03 -0400
Links: << >>  << T >>  << A >>
Wholesale copying is easy to do, and with an SRAM device, there just isn't much
you can do to prevent it short of loading the configuration during production
and keeping it powered from then on (I've done that for a high security military
system).  As far as reverse engineering the bitstream goes, the person has to be
very motivated, but it can be done.  It is probably a little harder from a
multi-device design in that respect.  However, a multi-device design provides
more nodes that can be observed to help in determining the circuit function.



Mark Grindell wrote:

> Incidently, what is your feeling about Altera design security - given a
> particular design, is it more dificult to reverse engineer a three device
> chip set, or one huge single chip design - or is reverse engineering in any
> case mostly impractical, and a somewhat mute point?
>
>



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17342
Subject: Re: Dongle problems.
From: "EKC" <NOSPAMalpha3.1@ix.netcom.com>
Date: Wed, 21 Jul 1999 20:36:51 -0500
Links: << >>  << T >>  << A >>
What exactly is a dongle?


Article: 17343
Subject: Re: Dongle problems.
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Wed, 21 Jul 1999 19:21:28 -0700
Links: << >>  << T >>  << A >>
DONGLE: n.

The "polite" term for those pesky hardware blocks that hang off a parallel
or serial port and allow you to run a vendor's protected software package.
Many are rumored to contain advanced technology that can detect an
approaching project deadline and cause the dongle to stop working at a
critical juncture.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



EKC wrote in message <7n5p0t$c18$1@nntp1.atl.mindspring.net>...
>What exactly is a dongle?
>
>


Article: 17344
Subject: Re: Xilinx Foundation Beginner Question
From: fliptron@netcom.com (Philip Freidin)
Date: 22 Jul 1999 02:31:51 GMT
Links: << >>  << T >>  << A >>

I assume that you are trying the first example in the book.
There is a problem with the sw when faced with a design that
fits in 1 CLB. This is fixed with some updates you can get
from the web.

Assuming that what you have is F1.5 (not F1.5i)

I believe you need the following two updates:

	ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_service_pack1_nt.zip

and

	ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_sp1_ftp2_nt.zip

You can read about these at ftp://ftp.xilinx.com/pub/ftpfiles.htm

at also look up the solution records.


Philip Freidin



In article <37966588.6F2A05F5@gulfaccess.com>,
Nicholas Brown  <nbrownNOT@gulfaccess.com> wrote:
>Hello,
>Im just starting out with Xilinx Foundation 1.5 and having a problem
>with implementing schematic flow.
>When I "Create Netlist" from the schematic editor, I get the warning
>"Netlist creation warning: terminals for top level schematic", but the
>netlist dose get generated correctly. There are no warnings for the
>Integrity test or Export netlist. At the implementation window I get the
>
>message "Starting Constructive Placer.  REAL time: 12 secs" (during the
>place and route portion) and nothing seems to happen after that.
>Everything was entered as the text book describes. Any suggestions as to
>
>whats wrong ?
>Any insight would be appreciated. Thanks in advance.
>-Nick
>


Article: 17345
Subject: Re: Xilinx Foundation Beginner Question
From: Dave Vanden Bout <devb@xess.com>
Date: Wed, 21 Jul 1999 23:30:10 -0400
Links: << >>  << T >>  << A >>
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Nick:

The place&route stalls for simple 1-CLB designs unless you install a software patch.  Here is the relevant entry from the FAQ at www.xess.com/FPGA:

Q:
When I run the flow engine at PLACE & ROUTE state computer stalls. The
last 7 lines of the status display is as shown below.

     Overall effort level (-ol):   2 (set by user)
     Placer effort level (-pl):    2 (default)
     Placer cost table entry (-t): 1
     Router effort level (-rl):    2 (default)

     Starting initial Placement phase.  REAL time: 10 secs
     Finished initial Placement phase.  REAL time: 10 secs

     Starting Constructive Placer.  REAL time: 10 secs

I am running a very simple design from the book "the practical designer
lab book "TRIPGEN1.SCH". This happens when I assigned the output node to
a pin( using constrain file LOC=p25). The inputs can be assigned to pins
without any problem. When I remove the LOC=p25 from the OBUF runs
without any problems. Any help would be appreciated.

A:
I saw this problem on early versions of Foundation 1.5, but I thought they
fixed it before they mastered the CDROM for the XSE.  I did recreate your
problem by reinstalling from the XSE CDROM.  You need to install a patch from
the Xilinx web site to fix the problem.  The patch is found at
http://www.xilinx.com/support/techsup/sw_updates/sw_f15_pc.htm and is called
15_service_pack1_nt.zip.  The file is said to be for windows NT, but it also
works for Win95.  The file is 11.4 MBytes.

Nicholas Brown wrote:

> Hello,
> Im just starting out with Xilinx Foundation 1.5 and having a problem
> with implementing schematic flow.
> When I "Create Netlist" from the schematic editor, I get the warning
> "Netlist creation warning: terminals for top level schematic", but the
> netlist dose get generated correctly. There are no warnings for the
> Integrity test or Export netlist. At the implementation window I get the
>
> message "Starting Constructive Placer.  REAL time: 12 secs" (during the
> place and route portion) and nothing seems to happen after that.
> Everything was entered as the text book describes. Any suggestions as to
>
> whats wrong ?
> Any insight would be appreciated. Thanks in advance.
> -Nick

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Article: 17346
Subject: Re: Solaris vs. NT
From: rk <stellare@NOSPAM.erols.com>
Date: Thu, 22 Jul 1999 01:38:03 -0400
Links: << >>  << T >>  << A >>
hi wen-king,

i don't know your fpga tools, but can't they be run from a simple batch file
and a command language?  the tools that i run all have a command line
interface and can be run either from a batch file or under the control of
another program.  one of my goals is to automate as much as possible and part
of that is to not have to be there to press a button every few minutes in a
long string of buttons to be pushed.  it was a bit disappointing that one
vendor charges double for the priveledge of running from the command line,
with a floating license required for that feature; it will not work on
node-locked licenses.

have a nice evening,

rk

_______________________________________________________

Wen-King Su wrote:

> In a previous article Jerry Zdenek <zdenekjs@interaccess.com> writes:
> :
> :I really believe in automating as much of the process as possible;  That
> ;way, some user (usually me) can't screw it up or forget a step.  We do
> :post-layout simulation with an EDIF netlist, and to jump back and forth
> ;between the unix ws (for everything but the Maxplus2 fitter) and the PC
> :just to fit the FPGA is very annoying.
> ;
> :What I like to be able to do is make some change to the VHDL, and kick
> ;off the entire process again *without* having to be there.  It's so much
> :more efficient, esp. if the design is large.  What I define is the
> ;easiest is to make a change to the source and then walk away until I
> :have simulation results available.
>
> That is exactly the way I feel.  I have an NT box on the side in my office
> just so I can, after doing everything on Unix, turn to the side to click
> buttons to run the FPGA fitter.   And that NT box, is the only reason why
> I have to be physically in my office to get work done.  I could have done
> everything else remotely from home or beach otherwise.  That is very
> annoying, and I have given up using that particular FPGA for a while.
> Nowaday I keep that NT box turned on in my office just to keep my office
> warm and to generate some white noise to suppress my tinnitis.
>
> Windows turn people into part of the machine, it expects you to be there
> just as it expects the hard drive to be there all the time, and that is
> wrong.



Article: 17347
Subject: Re: fpga 10k50 and up prototype with a/d d/a
From: "Mark Grindell" <mg@markgrindell.free-online.co.uk>
Date: Thu, 22 Jul 1999 08:46:39 +0100
Links: << >>  << T >>  << A >>
Dear Ray and Abraham,

To Ray, certainly, well said, sir. I have noticed this phenomenon with pin
locking to be sure... and I have a design which, rather than placing in a
single 10K100 or a 10K130, I have decided to parition (loosely) in three
10K50's. For a start the ratio of memory blocks to logic cells is rather
more advantageous, and secondly, as you say, its easier to have a design
which works faster.

Incidently, what is your feeling about Altera design security - given a
particular design, is it more dificult to reverse engineer a three device
chip set, or one huge single chip design - or is reverse engineering in any
case mostly impractical, and a somewhat mute point?

Mark Grindell

Ray Andraka wrote in message <37909BC9.A65FB02D@ids.net>...
>You gotta be careful going with the bigger device in Altera.  They get
slower as
>they get bigger.  Altera is pretty sensitive to pin locking if you fill the
>device past around 50%, so you do have to be careful.
>
>Mark Grindell wrote:
>
>> You might be best advised to make one up youself. You might select some
>> chips which you know a fair bit about, choose a configuration using
general
>> I/O pins and then send a coupld of hours or so with Protel, and
hey-presto -
>> you've done it yourself!
>>
>> There is a catch. Depending on your application complexity, commiting
your
>> pinouts like this can make the project a bit more difficult to fit -
>> commiting the pins often does this. Given this, and guessing that your
>> eventual target is a 10K50, I would (in your situation) go for a much
bigger
>> device, which would give me loads of room, and make routing a bit easier
and
>> swifter. I would try a 10K100 myself - and then you *know* you won't run
out
>> of room.
>>
>> Goodness me, for a protype they're cheap enough. I might even jump to a
>> 10K130 if I was feeling really reckless...
>>
>> Abraham Roth <s3279466@techst02.technion.ac.il> wrote in message
>>
>
>
>
>--
>-Ray Andraka, P.E.
>President, the Andraka Consulting Group, Inc.
>401/884-7930     Fax 401/884-7950
>email randraka@ids.net
>http://users.ids.net/~randraka
>
>


Article: 17348
Subject: Re: Chemical FPGAs
From: "Mark Grindell" <mg@markgrindell.free-online.co.uk>
Date: Thu, 22 Jul 1999 08:49:25 +0100
Links: << >>  << T >>  << A >>
All this is OK, but I would simply hate to have to wait for my VHDL
compiler, running on a Pentium II at 350 Mhz  to get through a design for a
billion logic gates....

Interesting, though...

Mark
Brad Taylor wrote in message <3790D9DE.328F3FB9@cmln.com>...
>Hi -
>
>The article below was the front page headline of the San Francisco
Chronicle on
>Thursday. I thought it might also be of interest to the readers of this
group.
>It describes work by Philip Kuekes, a computer architect at
>Hewlett-Packard, and others who have constructed a configurable switch
based on
>carbon nanotubes coated with rotaxane molecules. In effect, the rotaxane
>molecules act as "anti-fuse" links between the bucky tubes. It's still a
way off
>from being a real device however. Philip Kuekes is a long time FPGA
researcher
>and developer of the reconfigurable Teramac system at HP.
>
>"Tiny Switch Could Shrink Computers Microscopic machines with the power of
a
>billion PCs"
>
>http://www.sfgate.com/cgi-bin/article.cgi?file=/chronicle/archive/1999/07/1
6/MN36688.DTL
>
>-
>Brad
>
>I also have a small web page which has some random links in this area at:
>http://members.tripod.com/~blt_/nano_electronics.html


Article: 17349
Subject: Re: Solaris vs. NT
From: Jamie Lokier <spamfilter.jul1999@tantalophile.demon.co.uk>
Date: 22 Jul 1999 12:26:21 +0200
Links: << >>  << T >>  << A >>
Zoltan Kocsi writes:
> By the way, what do you exactly do with graphics packages when you 
> design FPGAs ? 

Click on "compile".  Wait 10 minutes.  Click on "timing analyser".
Click on "registered performance".  Or maybe click on "simulate".
Go back to Linux, edit files, and repeat.

To be fair I've been doing some schematic entry lately using
the graphical tools.

I have to use three computers in the toolchain for a simple build.
Never mind.

-- Jamie


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