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Messages from 17600

Article: 17600
Subject: port name reg_input won't sim.
From: Mike Treseler <tres@tc.fluke.com>
Date: Thu, 12 Aug 1999 21:46:12 +0000
Links: << >>  << T >>  << A >>
port name reg_input won't sim. See below.

Note that you can connect components without a declaration
if the code is in the work directory. 
Here's how I hooked up to your component for example:

bq:entity work.bq_translate 
    port map (dq,clk_8192,hreset,transmit,command,readback,gas_done,gas_error);

----------------------------------------
228 wauna: /usr0/moonunit/public/pendulum/pca/p2kcpu/fpga> vcom test.vhd
Model Technology ModelSim EE/VHDL 5.1f
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package numeric_std
-- Loading package bq_share
-- Compiling entity test
-- Compiling architecture flow of test
-- Loading entity bq_translate
-- Loading entity bq2014
###### test.vhd(65):   );
ERROR: test.vhd(65): Port "reg_input" is on entity "bq2014" but not on the
component declaration.
ERROR: test.vhd(65): Port "reg_addrs" is on entity "bq2014" but not on the
component declaration.
ERROR: test.vhd(65): Port "change" is on entity "bq2014" but not on the
component declaration.
###### test.vhd(334): end architecture flow;
ERROR: test.vhd(334): VHDL Compiler exiting
Article: 17601
Subject: Re: port name reg_input won't sim.
From: Mike Treseler <tres@tc.fluke.com>
Date: Thu, 12 Aug 1999 21:49:35 +0000
Links: << >>  << T >>  << A >>
Sorry. Inside mail sent out by mistake.
          -Mike Treseler
Article: 17602
Subject: Re: port name reg_input won't sim.
From: Steven Casselman <sc@vcc.com>
Date: Thu, 12 Aug 1999 15:46:21 -0700
Links: << >>  << T >>  << A >>
Must have been a fluke.

Mike Treseler wrote:

> Sorry. Inside mail sent out by mistake.
>           -Mike Treseler

--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 17603
Subject: Hollywood Blonde and Reconfigurable Computing
From: Steven Casselman <sc@vcc.com>
Date: Thu, 12 Aug 1999 16:10:46 -0700
Links: << >>  << T >>  << A >>
Today (Thursday 8-12 right now 4:00pm) The Great Beer Company
is giving out free beer at the Beverages and More on
Camden and Union right next to Xilinx. Hollywood Blonde
is on sale there.

For those who don't go to the FCCM. VCC has been bringing
beer for many years. Then My wife got involved in a beer
company (we formulated the beer together but she does
all the brewing (PhD biochemistry)). Anyway the last two years
we have been bringing Hollywood Blonde the website is
http://www.greatbeerco.com  You will notice we just
won the California State Fair "Best of Show" beating
out every other brewing company in the state.

Don't send or post flames. This is the best way for
me to reach my friends.

Thanks

--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 17604
Subject: Re: PCI core
From: "MPU" <CPU@MC.COM>
Date: Fri, 13 Aug 1999 02:54:17 GMT
Links: << >>  << T >>  << A >>
Please, visit the Cypress semiconductors. (www.cypress.com)
       and, Search by "PCI".

p.s : I'm NOT Cypress man.


ȫ  () <37B1348B.A8AC94BA@future.co.kr> ޽
ۼϿϴ...
>hello,
>
>i'm looking for a PCI core in the form of VHDL or Verilog source code
>that is surely synthesizable and provides all kinds of stuffs neeeded to
>develop an ASIC with PCI interface.
>
>Please, somebody tell me who sells this kind of reliable PCI core, or
>where I should find information on it.
>


Article: 17605
Subject: FIREFLY Embeddable MicroController Cores
From: wardrg@my-deja.com
Date: Fri, 13 Aug 1999 10:22:28 GMT
Links: << >>  << T >>  << A >>
FIREFLY Embeddable MicroController Cores

At Mitel Semiconductor, we have combined our advanced CMOS ASIC
technology with our MicroController design expertise to produce a unique
Embedded MicroController ASIC capability. We have given the name Firefly
to a set of embeddable MicroController cores developed for use in these
ASICs.

Firefly cores use the ARM7TDMI ('Thumb') processor core - a RISC
processor core, especially suitable for ASIC applications in the wired,
wireless communications and networking.

Thumb is licensed by Mitel from ARM Ltd, and is offered as part of the
Mitel SystemBuilder library of fully-supported embeddable
macrofunctions.

Mitel has enhanced the ARM core by adding a number of the sort of
peripherals everyone always needs, like a memory interface, an interrupt
controller, UART and timers, and turned it all into a single complex
microcontroller macrocell, the Firefly core. This first in the series of
Firefly cores is available in silicon and is accompanied by extensive
support.

Firefly ASICs bring all this practical design experience to customers
needing special-purpose microcontrollers. Mitel's Embedded
MicroController ASIC architecture has been specially developed to make
it easy to integrate customer's own logic with a Firefly core including
memory and other standard functions. A comprehensive design flow,
assists customers achieve right first time silicon of complex SLI
designs along with many other benefits.

For more information regarding FIREFLY please visit -

http://www.mitelse


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Share what you know. Learn what you don't.
Article: 17606
Subject: Re: Philips Semiconductors (NL) seeks digital designers
From: Brian Boorman <XZY.bboorman@harris.com>
Date: Fri, 13 Aug 1999 07:23:25 -0400
Links: << >>  << T >>  << A >>
Now why would any of us apply for this job when we all know about the
atrocities Philips does to its researchers?

(TIC)

-- 
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>
Article: 17607
Subject: Virtx' Configuration with the Xchecker cable
From: "cuong" <cuong@cnam.fr>
Date: Fri, 13 Aug 1999 17:08:01 +0200
Links: << >>  << T >>  << A >>
Hello,

I tried to download my design to the xcv100_pq240. It runs correctly
sometimes. But after an new implementation, the configuration failed and
DONE signal doesn't go high. It happened in many times.

My hardware configuration is:

"M2 M1 M0" = "101"

I selected the startup clock = Jtagclk. .

the version of Design Manager is 1.5.25.

With the new version of Design Manager 2.1i, there is no change.

Can you show me exactly what to do ?

Thanks.

Best Regards



Article: 17608
Subject: Re: Philips Semiconductors (NL) seeks digital designers
From: "srikanth.b" <Srikanth.B@analog.com>
Date: Fri, 13 Aug 1999 10:16:28 -0500
Links: << >>  << T >>  << A >>
Not me... Never again.

Srikant

Article: 17609
Subject: Computers & Causes
From: donna (Donna Simms)
Date: 13 Aug 1999 17:59:17 GMT
Links: << >>  << T >>  << A >>
I found a great site where you can shop popular computer e-commerce sites 
and support causes like Hospice Foundation, Meals On Wheels, Earth Share, 
Gilda's Club, Arbor Day, Greenpeace, and more. You get great deals on 
computer equipment and 100% of the referral fees go to the cause you choose 
-www.worthycauses.com  . The cause shopping pages have links to great 
places like:

Dell Computers, Outpost.com, Beyond.com Chipshot golf, Golf Warehouse, 
Esprit, J. Crew, Sharper Image, Amazon, eToys, Office Max, Staples, 
Hotel Discounts, priceline.com and more

Also check out more great deals on golf equipment, travel reservations, 
gifts, flowers, and books.

Now I can support a cause and it doesn't even cost me anything.
What a great idea! Check it out!
Article: 17610
Subject: Xilinx FPGA FIR filter number format?
From: Tom McDermott <Tom.Mcdermott@usa.alcatel.com>
Date: Fri, 13 Aug 1999 13:16:28 -0500
Links: << >>  << T >>  << A >>
Does anyone know which 'signed' and 'unsigned' formats are used
by the FIR filters that are generated by the Xilinx COREgen automatic
DSP core generator?  One might guess that the unsigned format is
just binary, but can't tell if the signed format is 1-compement,
2-complement,
offset binary, or what

I've looked through the spec sheets for the serial FIR filter, and
searched
the Xilinx doc's I've got without any success.

--

Tom McDermott
Tom.Mcdermott@usa.alcatel.com


Article: 17611
Subject: Re: Philips Semiconductors (NL) seeks digital designers
From: madhurk@my-deja.com
Date: Fri, 13 Aug 1999 22:12:48 GMT
Links: << >>  << T >>  << A >>
Had enough of your autocratic & lethargic environment.

Has Philips stooped to such levels as to post on news groups
as freelance headhunters do. Go to India. You have lot of
managers in Philips India to do it.

I wish the hr at philips apply their mind as to which newsgroup
they need to post.


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Share what you know. Learn what you don't.
Article: 17612
Subject: Re: Philips Semiconductors (NL) seeks digital designers
From: pboonen@my-deja.com
Date: Fri, 13 Aug 1999 22:56:33 GMT
Links: << >>  << T >>  << A >>
It is true. Heard that Philips semiconductors Bengulure India
does only recruting and sendign nijmegen.Contact managers in philips
semiconductors bengulure, who does nothing but only that.

this is not the forum to do it.

adieu,
paul b.


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Article: 17613
Subject: Re: Virtx' Configuration with the Xchecker cable
From: "Johan Frdin" <frodin@tripnet.se>
Date: Sat, 14 Aug 1999 17:31:16 +0200
Links: << >>  << T >>  << A >>
Just a thought.
Do you have the 3V adapter for the X-checker cable?

/Johan




Article: 17614
Subject: Free UART
From: "Jonathan Cutting" <jcutting@mail.com>
Date: Sat, 14 Aug 1999 08:35:54 -0700
Links: << >>  << T >>  << A >>
Hi,

I am considering using one of the free UARTs listed in the FAQ.  Does anyone
have any preference or tips related to these models?

TIA,

Jon


Article: 17615
Subject: Xilinx purchase of Philips CoolRunner PLDs - good or bad, any views?
From: z80@ds2.com (Peter)
Date: Sat, 14 Aug 1999 18:31:23 GMT
Links: << >>  << T >>  << A >>

I would like to hear of any experiences, good or bad, about this.

I have the P3Z22V10, the basic device in the range, designed into
several products.

What will happen to the programmers and the software support for them?
Will the programmer software still be free like it is at present?


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.
Article: 17616
Subject: Re: Xilinx purchase of Philips CoolRunner PLDs - good or bad, any views?
From: "Roger Hulsmans" <rogerFILTER@OUTchello.nl>
Date: Sun, 15 Aug 1999 12:14:12 +0200
Links: << >>  << T >>  << A >>
A letter to coolrunner customers:

http://www.coolpld.com/company/coolrunner/custltr.htm


Peter <z80@ds2.com> wrote in message
news:37b7b1bf.90579696@news.netcomuk.co.uk...
>
> I would like to hear of any experiences, good or bad, about this.
>
> I have the P3Z22V10, the basic device in the range, designed into
> several products.
>
> What will happen to the programmers and the software support for them?
> Will the programmer software still be free like it is at present?
>
>
> Peter.
> --
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but remove the X and the Y.
> Please do NOT copy usenet posts to email - it is NOT necessary.


Article: 17617
Subject: VHDL/Verilog? - Can of Worms
From: mx3000@my-deja.com
Date: Sun, 15 Aug 1999 10:43:13 GMT
Links: << >>  << T >>  << A >>
Hey,

I'm going to be starting on some hefty Virtex
FPGA designs, and I was trying to settle on
a HDL to use.  I've briefly used VHDL and been
OK with it. (I don't see anything wrong with
the strong typing.)  Other people around me are
saying that Verilog is a better choice for now
(more device models available for simulation,
easier) and the future (gaining market share over
VHDL).

Are there any recent surveys indicating what
current trends are?

Does it really matter?

Thanks,

Peter


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Article: 17618
Subject: Re: VHDL/Verilog? - Can of Worms
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Sun, 15 Aug 1999 14:07:26 GMT
Links: << >>  << T >>  << A >>
On Sun, 15 Aug 1999 10:43:13 GMT, mx3000@my-deja.com wrote:

>Hey,
>
>I'm going to be starting on some hefty Virtex
>FPGA designs, and I was trying to settle on
>a HDL to use.  I've briefly used VHDL and been
>OK with it. (I don't see anything wrong with
>the strong typing.)  Other people around me are
>saying that Verilog is a better choice for now
>(more device models available for simulation,

IMHO that's irrelevant in the grand scheme of things. With a decent
simulator like ModelSim from Model Technology that can co-simulate
Verilog & VHDL easily, the model issue goes away, as does (to some
extent) the recruitment and development issue. A decent FPGA synthesis
tool such as Leonardo Spectrum from Exemplar will enable you to mix
VHDL and Verilog together at the same time, (and quite frankly, for
Virtex will obliterate the others out there) so there are, to all
intents and purposes, no issues over which language to use. IMHO, as
projects and teams get bigger dual-language will perhaps become the
norm.

>easier) and the future (gaining market share over
>VHDL).

Define the market first please. In Europe, Verilog is a very small
part of the overall picture for FPGA and probably always will be. For
the UK that certainly has held true. In the USA, there seems to be a
much more established Verilog user base but there are pockets of VHDL
militia-men holding out against the new-world-order and black
helicopters ;-)

>Are there any recent surveys indicating what
>current trends are?

I don't know of any reliable quantitive data pertaining to the FPGA
market. My experience is that both languages are equally welcomed and
supported by the FPGA vendors, but in Europe you may find it easier to
get support from your local FAE in VHDL rather than Verilog. The
reverse may be true in the USA.

>Does it really matter?

IMHO, not really, no. Local conditions pertaining to recruitment and
support are probably more important. That said, I am still an ardent
VHDL fan as I have yet to find anything that can be done in Verilog
that cannot be done in VHDL. The same cannot be said of Verilog.

A case in point is a simple 31 tap folded filter for video. The VHDL
is given below, and using Spectrum it bangs over 100MHz in Virtex no
problem. Now, I'm sure that a "hand-crafted-and-placed" solution might
go a bit faster, and if super-pipelined might significantly outstrip
this, but changing coefficients in the hand-crafted design..... I'll
leave the estimates to those better in the know than I. Ray???

Any other Verilog (or VHDL) users want to come back on this example?

Cheers
Stuart
-- A very simple symmetrical signed FIR filter with 11 bit signed
coeffs 31 taps
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_signed.all ;

entity fir is
    port (
        clk		: in std_logic ;
        global_reset	: in std_logic ;
        data_in		: in std_logic_vector(9 downto 0) ;
        result		: out std_logic_vector(9 downto 0)
     ) ;
end fir ;

architecture rtl of fir is

type coeff_list is array (0 to 15) of integer ;
constant taps : coeff_list := ( -6, -10, -8, 6, 30, 48, 38, -14, -93,
-154, -132, 21, 298, 628, 896, 1000 ) ;
type data_array is array (30 downto 0) of std_logic_vector(9 downto 0)
;
signal shift : data_array ;
type folded_array is array (15 downto 0) of std_logic_vector(10 downto
0) ;
signal sum : folded_array ;
type mpy_array is array (15 downto 0) of std_logic_vector(21 downto 0)
;
signal mpy : mpy_array ;

begin
shifter : process (clk, global_reset)
begin
    if (global_reset = '0') then
        shift <= (others => (others => '0')) ;
    elsif (clk'event and clk = '1') then
        shift <= shift(29 downto 0) & data_in ;
    end if;
end process shifter;
folder : process (clk, global_reset)
begin
    if (global_reset = '0') then
        sum <= (others => (others => '0')) ;
    elsif (clk'event and clk = '1') then
        for i in 0 to 14 loop
            sum(i) <= sxt(shift(i),11) + sxt(shift(30-i),11) ;
        end loop ;
        sum(15) <= sxt(shift(15),11) ;
        -- middle is only one but extend anyway
    end if;
end process folder;	
multiplier : process (clk, global_reset)
begin
    if (global_reset = '0') then
        mpy <= (others => (others => '0')) ;
    elsif (clk'event and clk = '1') then
        for i in 0 to 15 loop
            mpy(i) <= sxt(sum(i),11) *
conv_std_logic_vector(taps(i),11) ;
        end loop ;
    end if;
end process multiplier;	
summation : process (clk, global_reset)
    type summer_type is array (0 to 3) of std_logic_vector(23 downto
0) ;
    variable summer : summer_type ;
    variable result_int : std_logic_vector(25 downto 0) ;
begin
    if (global_reset = '0') then
        summer := (others => (others => '0')) ;
        result <= (others => '0') ;
    elsif (clk'event and clk = '1') then
        result_int := sxt(summer(0),26) + sxt(summer(1),26) +
sxt(summer(2),26) + sxt(summer(3),26) ;
        for i in 0 to 3 loop
            summer(i) := sxt(mpy(4*i),24) + sxt(mpy(4*i+1),24) +
sxt(mpy(4*i+2),24) + sxt(mpy(4*i+3),24) ;
        end loop ;
        result <= result_int(24) & result_int(20 downto 12) ;
    end if;
end process summation;	
end rtl ;
An employee of Saros Technology:
Model Technology, Exemplar Logic, TransEDA, Renoir.
www.saros.co.uk
Article: 17619
Subject: Best synthesis tools for virtex?
From: "Steve McDowell" <srmcd@marrakesh.mv.com>
Date: Sun, 15 Aug 1999 12:10:10 -0400
Links: << >>  << T >>  << A >>
I'm looking at utilizing the virtex 600 and larger devices. Does anyone have
any strong likes / dislikes for the various systhesis tools as applied to
the large Xilinx gate arrays?

I'm also interested in the same input on mixed schematic / VHDL
environments.

Thanks,

 - Steve



Article: 17620
Subject: file format conversion for obsolete 3000-series XILINX parts?
From: edick@hotmail.com (Richard Erlacher)
Date: Sun, 15 Aug 1999 18:53:56 GMT
Links: << >>  << T >>  << A >>
Many years ago, when the XILINX 3000-series parts cost approximately
the part number /10 in $US, I acquired a few of these parts as part of
a job.  Some remain available, and I wonder if there isn't a utility
for translating/reworking Foundation software output for use in these
devices.

This would be a handy way to use up these otherwise useless parts in
fixtures for my lab, etc.

thanx

Dick

Article: 17621
Subject: Re: VHDL/Verilog? - Can of Worms
From: "Simon Ramirez" <s_ramirez@email.msn.com>
Date: Sun, 15 Aug 1999 20:11:08 -0400
Links: << >>  << T >>  << A >>
Peter,
     My experience has been that it doesn't matter which language you use.
At one time I suppose that it did, depending on what you were doing and
whose tools you had.
     It seems to me, though, that VHDL tools are generally more abundant and
cheaper than Verilog tools.  That may change tomorrow, but if it does, mixed
mode will likely prevail.
-Simon



<mx3000@my-deja.com> wrote in message news:7p65k0$4ts$1@nnrp1.deja.com...
> Hey,
>
> I'm going to be starting on some hefty Virtex
> FPGA designs, and I was trying to settle on
> a HDL to use.  I've briefly used VHDL and been
> OK with it. (I don't see anything wrong with
> the strong typing.)  Other people around me are
> saying that Verilog is a better choice for now
> (more device models available for simulation,
> easier) and the future (gaining market share over
> VHDL).
>
> Are there any recent surveys indicating what
> current trends are?
>
> Does it really matter?
>
> Thanks,
>
> Peter
>
>
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.


Reply-To: "Chi Fung" <cffung@sp.edu.sg>
Article: 17622
Subject: Constant port map in component instantiation
From: "Chi Fung" <cffung@sp.edu.sg>
Date: Mon, 16 Aug 1999 09:51:10 +0800
Links: << >>  << T >>  << A >>
I understand that the standard format for component instantiation
using port map is

    U1: comp1
        port map(component_pin=>signal_node);

where signal_node has been declared previously right
below the currrent architecture.

My problem is, let say, if I want to port map component_pin
to a constant, e.g. '1' instead of signal_node, how am I
suppose to code that? I have tried

    port map(component_pin=>'1');

but it doesn't seem to work.

Thanks for any hints.


Article: 17623
Subject: Re: Best synthesis tools for virtex?
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Sun, 15 Aug 1999 22:08:24 -0400
Links: << >>  << T >>  << A >>
Synplicity does a great job on Virtex.

Josh Rosen

Steve McDowell wrote:
> 
> I'm looking at utilizing the virtex 600 and larger devices. Does anyone have
> any strong likes / dislikes for the various systhesis tools as applied to
> the large Xilinx gate arrays?
> 
> I'm also interested in the same input on mixed schematic / VHDL
> environments.
> 
> Thanks,
> 
>  - Steve
Article: 17624
Subject: Re: VHDL/Verilog? - Can of Worms
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Sun, 15 Aug 1999 22:35:23 -0400
Links: << >>  << T >>  << A >>
Verilog is by far the better choice. I've done large designs in both
languages for both FPGAs and ASICs. Verilog is much cleaner, development
time is much shorter, it simulates faster and Synthesis tools seem to
have less trouble with it. I benchmarked ModelSim on the exact same
design and found that when the design was in Verilog it ran 3 times
faster then when the design was in VHDL. I've also used both Synplicity
and Synopsys with both languages. In Synplicity I've never had a problem
with Verilog, whereas I've frequently seen Synplicity do bizarre things
to VHDL. With Synopsys I've also had fewer problems with Verilog. The
reason for Verilog's advantage is that it's a much much simpler language
which makes it easier for tool developers to get things right. 

Tool prices are pretty much the same for both languages on Unix and
Windows, I don't know of any VHDL tools are on Linux but there are
several Verilog simulators on Linux. I use Finsim which is reasonably
low priced and I've found to be quite satisfactory. VCS is also
available in Linux although my understanding is that it's priced the
same as the workstation version.

Models are vendor specific. Xilinx provides libraries for both VHDL and
Verilog. RAM vendors also provide models in both languages. Other
components have an RTL model in one or the other, with a gate level
model available in both languages.

 

Josh


mx3000@my-deja.com wrote:
> 
> Hey,
> 
> I'm going to be starting on some hefty Virtex
> FPGA designs, and I was trying to settle on
> a HDL to use.  I've briefly used VHDL and been
> OK with it. (I don't see anything wrong with
> the strong typing.)  Other people around me are
> saying that Verilog is a better choice for now
> (more device models available for simulation,
> easier) and the future (gaining market share over
> VHDL).
> 
> Are there any recent surveys indicating what
> current trends are?
> 
> Does it really matter?
> 
> Thanks,
> 
> Peter
> 
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.


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Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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