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Look at the Xilinx part app note. The connections are pretty much the same. The one gotcha I can think of is to watch the reset polarity, which is programmed separately from the bit file, and is opposite the Xilinx. Paul Mondello wrote: > Hello, > > I am trying to find out how to program a Xilinx Spartan XCS40XL with an > Atmel serial EEPROM rather than using the Xilinx serial PROMs. The goal is > to be able to easily reprogram the FPGA. > > Can anyone give me some direction on which Atmel part to use and how to hook > it up to the FPGA? I am using the Master programming mode. > > Any help would be greatly appreciated. Thanks. > > Paul M. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18101
Hi All, What is the criteria on which FPGAs are said to be Coarse grained or Fine grained. Is it the size of the basic logic block?. Xilinx 4000 are sometimes referred to be coarse grained, sometimes medium grained and even fine grained sometimes! I guess it depends on a certain criteria and on a relative comparative ground as well. Please, I want one, precise definition! Cheers.Article: 18102
Well, I've never considered the 4K ans anything but a course grained architecture. I don't know of any real definitions, but for comparison sake consider the atmel 6K or even the xilinx 6K. Those are what I'd call fine grain - each cell only handles a 2 or 3 input function, but the cell speeds are considerably higher than the 4K of the same time period. The 4 K cell is a conglomerate of smaller LUTs, flip-flops, carry logic etc. I haven't come across an architecture touted as medium grained. If you find a solid definition, I'd like to hear it too. George wrote: > Hi All, > > What is the criteria on which FPGAs are said to be Coarse grained or Fine > grained. Is it the size of the basic logic block?. Xilinx 4000 are sometimes > referred to be coarse grained, sometimes medium grained and even fine > grained sometimes! I guess it depends on a certain criteria and on a > relative comparative ground as well. > > Please, I want one, precise definition! > > Cheers. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18103
Actel FPGAs are considered to employ a fine-grained architecture. The ACT architecture is comprised of simple c-modules and s-modules. These simple modules greatly simplify place-and-route .... this allows a high level of device utilization (over 90%) whatever the mix of combinational logic to flip-flops.Article: 18104
: - each cell only handles a 2 or 3 input function, but the cell speeds are
: considerably higher than the 4K of the same time period.
A while ago I think I remember a thread discussing the speed grading
of FPGAs, but I cant recall the details. Can someone clarify these
points for me:
- Is the Xilinx XC6k grading as the same as the XC4k? If not, how can I
from a basis for comparison.
- The same question applies for comparing the Virtex grading vs that
of the XC4k devices.
Is there any on-line documentation which answers these questions?
Thanks,
Mathew
Article: 18105In article <37F2A36D.B12E5EC0@ids.net>, Ray Andraka <randraka@ids.net> wrote: > Look at the Xilinx part app note. The connections are pretty much the same. > The one gotcha I can think of is to watch the reset polarity, which is > programmed separately from the bit file, and is opposite the Xilinx. > We use both Xilinx and Atmel serial PROMs with Xilinx FPGA families, and the PROM programmer must be set for low reset polarity, for both Atmel and Xilinx. We usually use Atmel devices for prototyping and early production, since they can be reprogrammed. If you follow Xilinx recommendations for their PROMs, you can drop the Atmel equivalent PROM in the same socket. BTW, it is our experience that if you go cheap on a PROM programmer, you will get exactly what you pay for (poor yields, slow, bad user interface, lousy device support, etc.) Bite the bullet and fork out a few grand to buy a good quality programmer. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@betweenthesplats.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18106
Stephan Diemer schrieb: > = > Someone said to me that FPGA=B4s are poor performers. Is this right? Co= uld > someone give me a speed comparison, for example between a modern PC-CPU= > and an fast Xilinx FPGA? > thanx You cannot compair a cpu with Logic; a CPU cannot have 250 Input and 250 Output and make cross-switching with 100 Mbit / Input = A cpu cannot make Jitter compensation, = A cpu cannot make Signal Encoding or decoding for Transmission of Data = at 100 MSymbols / sec = A Cpu cannot have 4 Clocks, each at another frequencyArticle: 18107
Klaus - I have not heard of the problems you mentioned. As you are aware, WebPack is a CPLD specific derivative of Foundation. A new version of WebPack was released yesterday. 2.1 W.P. 2.1 is to bring WebPack in line with service pack 2 of Foundation. One major change was the install from the web capability. This should provide a more robust installation process. I would encourage you to download the HDL-ABEL, the Device Fitter and the Device Programming Modules. If you do not find that this resolves the JEDEC problem I would encourage you to let me know. Hopefully we can identify where the issue lies and if it is in fact a potential problem. Larry McKeogh CPLD S/W Marketing Xilinx, Inc. Klaus Falser wrote: > Hello, > > Does anyone use Xilinx WebPack too? > I'm using Foundation 1.4 with XVHDL, and I downloaded Webpack, > seeing it as a possibility to have always the latest fitter. > > The first WebPack, based on Fitter M1.5 works fine, but the newer > versions (C.16 and C.17) do produce jedec files, which do not work. > When I fit the same EDIF file with the old fitter, they work. > > From the reports it seems, that the two fitter runs produces the same > equations, but .. > > Did anyone have similar problems? > > Best regards > Klaus > > -- > Klaus Falser > Durst Phototechnik AG > I-39042 Brixen > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 18108
There is an AT17 programmers kit from Atmel (ATDH2200E) which will program AT17 configurator proms and also normal serial EEPROMs. -- This is a personal view which may or may not be shared by my employer Atmel Sweden Ulf Samuelsson ulf 'a't atmel 'd'o't com Paul Mondello skrev i meddelandet <37f223f1.0@newsfeed.vitts.com>... >Hello, > >I am trying to find out how to program a Xilinx Spartan XCS40XL with an >Atmel serial EEPROM rather than using the Xilinx serial PROMs. The goal is >to be able to easily reprogram the FPGA. > >Can anyone give me some direction on which Atmel part to use and how to hook >it up to the FPGA? I am using the Master programming mode. > >Any help would be greatly appreciated. Thanks. > >Paul M. > >Article: 18109
>Ray Andraka <randraka@ids.net> wrote in message news:37F2B043.532A6FB8@ids.net... > Well, I've never considered the 4K ans anything but a course grained > architecture. I don't know of any real definitions, but for comparison sake > consider the atmel 6K or even the xilinx 6K. Those are what I'd call fine grain > - each cell only handles a 2 or 3 input function, but the cell speeds are > considerably higher than the 4K of the same time period. The 4 K cell is a > conglomerate of smaller LUTs, flip-flops, carry logic etc. I haven't come > across an architecture touted as medium grained. If you find a solid > definition, I'd like to hear it too. OK, that is how I would define it: I think the granularity of the the basic logic block (the number of I/O) is not the only determing factor. I think the routing architecture is also very important. The fine logic granularity gives better logic utilisation (less wasted logic resources). The coarse logic granularity allows the logic to be compacted in one complex logic block resulting in a very high operating speed. From this side, we can say that XC6000 and Atmel6k for example are fine grained. On the other hand, XC3000, XC4000, Virtex, Altra's Flex8000 etc. are coarse grained. However, if the routing structure is hierarchical (i.e there are Local, Doubles, 4 length, 16 length etc. routings segments), the FPGA can be considered as both fine and coarse grained because it combines both the efficient logic utilisation and the high operating speed no matter what the logic granularity is. That's why Virtex (and may be XC4000XL,XV) are sometimes decribed as fine grained (as well as coarse grained) because of the hierachical routing structure which means that a CLB can communicate with another distant CLB very quickly using long routing segments. Anybody agrees with that?Article: 18110
Hi, has anyone a schematic of the parallel-port-adapter for the ISP-Devices? THNX Masterbot Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18111
I don't need an explicit reset pin since all flip-flops are reset on
initialization anyway, however I still want to define the global reset net
in verilog. Is there a way to indicate that this net is being driven by the
chip's internal reset generator without having to bring the net out to an
external pin?
For example, I can do this ok:
module toplevel(clk,reset,in,out);
input clk, reset, in;
output out;
reg out;
STARTUP u1(.GSR(reset));
always @(posedge clk or posedge reset)
if(reset) out=0;
else out=in;
endmodule
But I really want something like this, with no pin wasted on the reset
signal:
module toplevel(clk,in,out);
input clk, in;
output out;
reg out;
wire reset=BUILT_IN_RESET_GENERATOR;
STARTUP u1(.GSR(reset));
always @(posedge clk or posedge reset)
if(reset) out=0;
else out=in;
endmodule
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 18112This is a multi-part message in MIME format. --------------FED29BFB63C4B6B7B097C4B8 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi, I have a few questions on using FPGAs for Reconfigurable Computing. 1) Are all SRAM based FPGAs capable of supporting reconfigurablity? 2) Xilinx 6000 series and Virtex FPGAs, are these the only devices capable of supporting partial and dynamic reconfigurations in the Xilinx family? 3) Is there any specifications that refer to On the Fly or Run time reconfiguration of these FPGA devices? Thank you very much. Regards Anup Kumar --------------FED29BFB63C4B6B7B097C4B8 Content-Type: text/x-vcard; charset=us-ascii; name="anup.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for anup kumar raghavan Content-Disposition: attachment; filename="anup.vcf" begin:vcard n:Anup Kumar;Raghavan tel;home:0061-7-38761962 tel;work:0061-7-33658849 x-mozilla-html:FALSE adr:;;;;;; version:2.1 email;internet:anup@elec.uq.edu.au fn:Anup Kumar end:vcard --------------FED29BFB63C4B6B7B097C4B8--Article: 18113
anup kumar raghavan wrote: > Hi, I have a few questions on using FPGAs for Reconfigurable Computing. > > 1) Are all SRAM based FPGAs capable of supporting reconfigurablity? Yes, at least at the whole chip level. > > > 2) Xilinx 6000 series and Virtex FPGAs, are these the only devices > capable of supporting partial and dynamic reconfigurations in the Xilinx > family? > No. Atmel6K, Atmel40K, Motorola's now extinct FPGA all do/did. I believe lucent ORCA parts do too. > 3) Is there any specifications that refer to On the Fly or Run time > reconfiguration of these FPGA devices? > Not a whole lot is written about it, at least from the vendors. Check papers by various universities. One of the more prominent is BYU under Brad Hutchings. Partial reconfiguration is loaded with pitfalls, many of which have not been solved completely. I don't think we'll see the silicon vendors actively pitching (with documentation and software to back it up) partial reconfiguration until it is better understood. Atmel currently has the best support for partial reconfig, and to be fair, they've been doing it longer than anyone else. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18114
Hai all
I am searching for evaluation/development board with StrongARM (SA-11XX)
processors. Anybody know where I can find such board and have uni. discount.
Your help is highly appreciated
Thank you
Article: 18115
I have to do an ATM scrambler in a FPGA and I wonder some questions :
Norm says that the polynome is x^43+1, it's enabled only during payload and
that the basic diagram is :
-------------------------------
| __ __ __ |
V | | | | | | |
Ei -->+-----| |-- | |-- ... --| |--|
| |__| |__| |__|
V
Yi
(sorry for this poor draw)
In others words :
d0 = e + q42
d1 = q0
d2 = q1
...
d42 = q41
Is it right ?
Thank you for your help.
Rémi SEGLIE
Hardware Design Engineer
company : CELOGIC
www : http://www.celogic.com/
Article: 18116In article <7t0cnp$fkf$1@nnrp1.deja.com>, Masterbot <masterbot@my-deja.com> wrote: > Hi, > > has anyone a schematic of the parallel-port-adapter > for the ISP-Devices? > It's on the Lattice CD-ROM, if you have a copy. It's a bit difficult to find, though, and I can't remember where it is. You'll probably find it on their web site, also. Leon -- Leon Heller, G1HSM Tel (Mobile): 079 9098 1221 (Work): 01327 357824 Email: leon_heller@hotmail.com Web: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18117
Leon Heller wrote: > It's on the Lattice CD-ROM, if you have a copy. It's a bit difficult to > find, though, and I can't remember where it is. Probably underneath the third coffee mug from your right elbow. Jonathan BromleyArticle: 18118
I am trying to estimate how many CLB's my design is going to need and I have some interesting findings to share. Let me go through the assumptions first. I use verilog, synplify 5.15, Xilinx Virtex v50pq240-4 (for the purpose of the example - in reality I use the 1000), and M2.1i tools. I have done a very simplistic 32-bit adder design as shown below: // Force i/o's into IOB's if (reset) begin at <= 'h0; bt <= 'h0; q <= 'h0; else begin at <= a; bt <= b; q <= qt; end // 32-bit adder if (reset) qt <= 'h0 else if (enable) qt <= at + bt; // Comment out "+ bt" for the register example Comment out everything related to the "b" input and get a simple 32-bit register. After mapping, the results strike me: adder: 16 slices register: 21 slices (exclude I/O's - just want core function) Why an adder (more complex) would need more slices than a simpler design (register)??? I have done a 5 32-bit register design and this scales almost linearly, i.e. 107 slices! Am I missing something? How come both dff slices not be utilized completely in the register implementation cases, i.e. a 32-bit register should map to 16 slices max. The "-c" switch does not seem to do anything. I have opened a case at xilinx, but I thought I'd share this with you. Cheers Martin Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18119
I was wondering if a Linear Feedback Shift Register of 64 plus bits running at 100MHz could be implemented on Xilinx XC9500 series chip. I need to implement this for my senior design project and this solution seems a lot cheaper than an IC based shift register. Any comments or pointers will be greatly appreciated. Thanks Aaron Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18120
>Leon Heller wrote: >> It's on the Lattice CD-ROM, if you have a copy. It's a bit difficult to >> find, though, and I can't remember where it is. > The schematic for the d/l cable is found in the datasheet for the d/l cable, both on the ISP CD and the website - www.latticesemi.com Hope this helps - Michael Thomas LSC SFAE 516-874-4968 fax 516-874-4977 michael.thomas@latticesemi.com for the latest info on Lattice/Vantis - www.latticesemi.comArticle: 18121
Hi, aaronburgess@ieee.org wrote: > I was wondering if a Linear Feedback Shift Register of 64 plus bits > running at 100MHz could be implemented on Xilinx XC9500 series chip. I > need to implement this for my senior design project and this solution > seems a lot cheaper than an IC based shift register. Any comments or > pointers will be greatly appreciated. take a look at the Xilinx application note XAPP052 (http://www.xilinx.com/apps/xapp.htm) entitled "Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators". -- EdwinArticle: 18122
Looking for VHDL source code to make a Motorola 6809E.If anyone has pointers, please holler back.Paul T. Bartonpaultb@wwdb.org (preferred, please) -**** Posted from RemarQ, http://www.remarq.com/?a ****- Search and Read Usenet Discussions in your Browser - FREE -Article: 18123
On Fri, 01 Oct 1999 12:27:09 GMT, martin_at_deja@my-deja.com wrote: >I am trying to estimate how many CLB's my design is going to need >and I have some interesting findings to share. > >Let me go through the assumptions first. >I use verilog, synplify 5.15, Xilinx Virtex v50pq240-4 (for the purpose >of the example - in reality I use the 1000), and M2.1i tools. > <snipped> >After mapping, the results strike me: > >adder: 16 slices >register: 21 slices >(exclude I/O's - just want core function) > >Why an adder (more complex) would need more slices than a simpler >design (register)??? I have done a 5 32-bit register design and >this scales almost linearly, i.e. 107 slices! Am I missing something? possible reason: synplify is presumably generating an RPM'ed module, which is packed into 16 slices, but is leaving PAR to do whatever it wants with the 32-bit register. I guess that PAR is simply spreading out the register to leave more room for routing (2.1i doesn't pack as tightly as 1.5, to simplify routing; there's a note about this somewhere in the installation guide). if you have a look in fpga editor you should find that some slices only have one register used. evanArticle: 18124
Yes, you can do that quite easily. The next-to-smallest device has 72 macrocells = flip-flops. All you need is a long shift register with the input fed from an exclusive-nor gate driven by two inputs, one of them from the end of the shift register. For a 65-bit LFSR, the other XNOR input is driven by bit position 47, for a 68-bit LFSR it's driven by position 59; for a 71-bit LFSR it's driven by position 65. (These feedback give you the maximum-length sequence ) Note that the positions are counted 1 through n ( not 0 through n-1) More information can be found in the Xilinx App Note XAPP 052. Peter Alfke, Xilinx Applications ================================ aaronburgess@ieee.org wrote: > I was wondering if a Linear Feedback Shift Register of 64 plus bits > running at 100MHz could be implemented on Xilinx XC9500 series chip. I > need to implement this for my senior design project and this solution > seems a lot cheaper than an IC based shift register. Any comments or > pointers will be greatly appreciated. > Thanks > Aaron > > Sent via Deja.com http://www.deja.com/ > Before you buy.
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