Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 18300

Article: 18300
Subject: Interconnecting LUTs on a Virtex
From: "Espen Tislevoll" <tislevol@idi.ntnu.no>
Date: Wed, 13 Oct 1999 11:56:06 +0200
Links: << >>  << T >>  << A >>
I want to connect different LUTs together on a Virtex chip.
For example, connecting output of F-LUT Slice 0 Column 1 Row 1 to one of the
inputs of G-LUT Slice 1 Column 2 Row 1.

Is it possible to put such low-level constraints, to a design, by any of the
development tools available for Virtex ?





Article 18558 of comp.arch.fpga:
Article: 18301
Subject: Re: Interconnecting LUTs on a Virtex
From: Ray Andraka <randraka@ids.net>
Date: Wed, 13 Oct 1999 09:47:15 -0400
Links: << >>  << T >>  << A >>
Use RLOC's to constrain the placement.  You'll also need to define the contents
of the LUT to nail the logic to the LUT.  For Virtex you can use the LUT
primitive or you can use an FMAP to specify the partitioning. The LUT primitive
needs an INIT= attribute to specify the contents, while the FMAP shows the
mapping of other logic to the LUT.  If you are using VHDL, you'll have to use
the EQN attribute with the FMAP to specify the logic.  With schematics, the FMAP
can be put in parallel with the logic it is to contain.  You can also put the
luts into specific locations using the graphical floorplanner.

The VHDL snippets below show one way of constraining some combinatorial logic to
a specific location.  In this case, the 3 input comb. function fmap_xnor3 is
defined by a separate entity with the xc_xmap=lut attribute.  That contains the
logic in a lut.  Then when that component is instantiated, an rloc string is
attached to the component label.  Here it is constrained to row 10, column 20,
LUT F in slice 0.

entity fmap_xnor3 is
  port ( a, b, c : in std_logic;
  z : out std_logic);
end fmap_xnor3;
architecture rtl of fmap_xnor3 is
attribute xc_map : STRING;
attribute xc_map of rtl : architecture is "lut";
begin
  z <= not a xor b xor c;
end rtl;

entity test is
 ....
end test

architecture structural of test is
attribute RLOC: string;
attribute RLOC   of U1 : label is "R10C20.F.S0";
 begin
  U1: fmap_xnor3 port map(
   a=> a(i),
   b=> b(i),
   c=> add,
   z=> l);


Espen Tislevoll wrote:

> I want to connect different LUTs together on a Virtex chip.
> For example, connecting output of F-LUT Slice 0 Column 1 Row 1 to one of the
> inputs of G-LUT Slice 1 Column 2 Row 1.
>
> Is it possible to put such low-level constraints, to a design, by any of the
> development tools available for Virtex ?



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka




Article 18559 of comp.arch.fpga:
Article: 18302
Subject: Re: Announcement: VHDL/FPGA Development Boards (up to 400.000 Gates) (Corrected Links, More Boards)
From: mrauf@nova-eng.com
Date: Wed, 13 Oct 1999 14:48:26 GMT
Links: << >>  << T >>  << A >>
Nova Engineering, Inc. is another place to look at for Altera
development boards:

http://www.nova-eng.com/constellation.html

Most of the boards are one week delivery or less.

VHDL Megafunctions are available from the same company:

http://www.nova-eng.com/vhdl.html

In article <ksoL3.18$Eb6.1816@typhoon-sf.snfc21.pbi.net>,
  "Steven K. Knapp" <sknapp@optimagic.com> wrote:
> I believe that the correct links are shown below.
>
> http://www.tzkom.de/service/devboard.htm
>
> http://www.tzkom.de/service/devboard_e.htm
>
> There is another page for these boards on the related Alcatel site at
> http://www.alcatel.de/telecom/asd/test_hw/devboards.htm.  You may
also be
> interested in the fairly comprehensive list of boards available at
> http://www.optimagic.com/boards.html.
>
> --
> -----------------------------------------------------------
> Steven K. Knapp
> OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
> E-mail:  sknapp@optimagic.com
>    Web:  http://www.optimagic.com
> -----------------------------------------------------------
>
> <lothar_brodbeck@my-deja.com> wrote in message
> news:7tks00$il3$1@nnrp1.deja.com...
> > Hello reader,
> >
> > I would announce two development boards. The two boards are useful
for
> > ASIC prototyping and simulation as well as for other purposes.
> > We and some other companies (Alcatel, Rhode&Schwarz, Siemens,
> > Wandel&Goltermann, ...) already used the boards to verify our
> > designs.
> >
> > Examples:
> >
> > - DSP algorithms written in VHDL
> > - behaviour of PLL circuits
> > - building of complex test equipment
> > - call simulator for 480 subscribers
> > - etc.
> >
> >
> > Short description of the boards:
> >
> > Altera FLEX10K development board:
> >
> > - up to 400.000 logical gates
> > - 2 slots for external memory (standard SIMM modules)
> > - PBA size 233mm*210mm
> > - 5V or 3.3V operation voltage (depending on used FPGAs)
> > - breadboard area for user applications
> > - on board reset circuit
> > - ...
> >
> >
> > Altera FLEX8K development board:
> >
> > - up to 20.000 logical gates
> > - PBA size 233mm*160mm
> > - board splittable into 2 times 100mm*160mm
> > - 5V operation voltage
> > - breadboard area for user applications
> > - on board reset circuit
> > - ...
> >
> > For more information about the development boards use one of
> > the possibilities listed below.
> >
> > Web-Site:   1st page:
> > http://www.tzkom.de
> >
> >                      development boards page:
> > http://www.tzkom.de/kompetenz/nt/devboard.htm
> >
> >                      (English: sorry not the final version
> > http://www.tzkom.de/kompetenz/nt/devboard_e.htm)
> >
> > Email:        Lothar.Brodbeck@tzkom.de .
> >
> >
> > Kind Regards
> >
> > Lothar Brodbeck
> >
> >
> > p.s.:
> >
> > An user wrote:    ... we successfully used the Altera FLEX10K board
to
> >                          verify our complex signal processing
algorithm.
> > ... The
> >                          programming and the handling of the
evaluation
> > board
> >                          stands out. ...
> >
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.


Article 18560 of comp.arch.fpga:
Article: 18303
Subject: .cal .rbt file format
From: James Birmingham <shu96jb@reading.ac.uk>
Date: Wed, 13 Oct 1999 17:19:23 +0100
Links: << >>  << T >>  << A >>

hello,

can anybody tell me or point me in the direction of .cal or .rbt file
format specification.  Also is there software which can convert a cal file 
to a .edn or .des file?

My knowledge of VHDL is very limited and I am
interested in working the binary/ascii files that are actually written to
a Xilinx 6216 for a cybernetics project.

Any help or advice is much appreciated.

James Birmingham
shu96jb@reading.ac.uk



Article 18561 of comp.arch.fpga:
Article: 18304
Subject: Re: ISP-Cable again
From: "Fuzesi Arnold" <arno@freemail.hu>
Date: Wed, 13 Oct 1999 21:29:54 +0200
Links: << >>  << T >>  << A >>

Hi!

>Hi,
>
>I've written some time ago that i need the schematic
>for the Lattice ISP-Cable.
>Some of you told me i could find the schematic
>at the Lattice webpage.

Everything about download cable:
http://www.hszk.bme.hu/~fa218/Download/Lattice_download_cable.zip

>I only could find the PIN-configuration for the cable from
>the PARALLEL-ADAPTER to the board that includes the ISP
>and not for the PARALLEL-ADAPTER itself.
>So it would be great if you could give me the exact URL (not
>only www.latticesemi.com )or send me the pdf-file direct via email.




Arnold





Article 18578 of comp.arch.fpga:
Article: 18305
Subject: Part Time, Atmel 6K, Bay Area
From: "Brad Smallridge" <manbike@smallridge.xo.com>
Date: Wed, 13 Oct 1999 13:34:28 -0700
Links: << >>  << T >>  << A >>
Looking for an Atmel 6K designer.
Video experience helpful.
Send resumes or email to bsmaxxllridge@sighxxtech.coxxm and remove the xx






Article 18563 of comp.arch.fpga:
Article: 18306
Subject: Re: Can't detect Flex 10K Altera device through JTAG port
From: "Mike" <mmatusov@ics-ltd.com>
Date: Wed, 13 Oct 1999 20:36:46 GMT
Links: << >>  << T >>  << A >>
Thanks to everybody for your input.

It seems that we had a bad device. We assembled another board and now can
detect the device. Still having some problems with programming it but it is
a different issue.

Mikhail Matusov




Article 18562 of comp.arch.fpga:
Article: 18307
Subject: ANN: The Industry's Largest Independent Information Source of FPGAs and CPLDs (www.optimagic.com)
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Wed, 13 Oct 1999 17:15:49 -0700
Links: << >>  << T >>  << A >>
UPDATE:  New industry market data (http://www.optimagic.com/market.html) and
         board vendor list (http://www.optimagic.com/boards.html)



Visit the industry's largest independent on-line information source for
programmable logic, The Programmable Logic Jump Station.

   * FREE downloadable FPGA and CPLD design software
   * Information on devices, boards, books, consultants, etc.
   * FAQ plus tutorials on VHDL and Verilog


              http://www.optimagic.com/index.shtml



Featuring:
---------


            --- FREE Development Software ---


Free and Low-Cost Software - http://www.optimagic.com/lowcost.shtml
Free, downloadable demos and evaluation versions from all the major
suppliers.


          --- Frequently-Asked Questions (FAQ) ---


Programmable Logic FAQ - http://www.optimagic.com/faq.html
A great resource for designers new to programmable logic.



          --- FPGAs, CPLDs, FPICs, etc. ---


Recent Developments - http://www.optimagic.com/index.shtml
Find out the latest news about programmable logic.


Device Vendors - http://www.optimagic.com/companies.html
FPGA, CPLD, SPLD, and FPIC manufacturers.


Device Summary - http://www.optimagic.com/summary.html
Who makes what and where to find out more.


Market Statistics - http://www.optimagic.com/market.html
Total high-density programmable logic sales and market share.



            --- Development Software ---


Design Software - http://www.optimagic.com/software.html
Find the right tool for building your programmable logic design.


Synthesis Tutorials - http://www.optimagic.com/tutorials.html
How to use VHDL or Verilog.



              --- Related Topics ---


FPGA Boards - http://www.optimagic.com/boards.html
See the latest FPGA boards and reconfigurable computers.


Design Consultants - http://www.optimagic.com/consultants.html
Find a programmable logic expert in your area of the world.


Research Groups - http://www.optimagic.com/research.html
The latest developments from universities, industry, and
government R&D facilities covering FPGA and CPLD devices,
applications, and reconfigurable computing.


News Groups - http://www.optimagic.com/newsgroups.html
Information on useful newsgroups.


Related Conferences - http://www.optimagic.com/conferences.html
Conferences and seminars on programmable logic.


Information Search - http://www.optimagic.com/search.html
Pre-built queries for popular search engines plus other
information resources.


The Programmable Logic Bookstore - http://www.optimagic.com/books.html
Books on programmable logic, VHDL, and Verilog.  Most can be
ordered on-line, in association with Amazon.com



            . . . and much, much more.


Bookmark it today!


Article: 18308
Subject: APEX
From: Leslie Yip (/ Loui) <leslie.yip@asmpt.com>
Date: Thu, 14 Oct 1999 01:26:13 GMT
Links: << >>  << T >>  << A >>
 Hello

I would like to ask if any people used Altera's new device APEX.
It seems unable to tolerate +5.0 Volt.
Any idea?

--
Hong Kong


Sent via Deja.com http://www.deja.com/
Before you buy.


Article 18568 of comp.arch.fpga:
Article: 18309
Subject: Great Lakes Symposium on VLSI: Submission deadline has been extended till October 22, 1999
From: "Amir Farrahi" <ahf@watson.ibm.com>
Date: 13 Oct 1999 18:55:59 -0800
Links: << >>  << T >>  << A >>

Dear Colleagues,

The submission deadline for the 10th Great Lakes Symposium on VLSI has been
extended from:

    October 15, 1999

to:

    October 22, 1999

Attached, you will find the updated call for papers.

Regards,
Amir Farrahi
Publicity Chair for the GLSVLSI-2000

===============================================================================

                             CALL FOR PAPERS
                   Tenth Great Lakes Symposium on VLSI
                              (GLSVLSI-2000)

                             March 2-4, 2000
                         Northwestern University
                            Evanston, Illinois

                   In Cooperation with ACM SIGDA, IEEE

           http://domino.watson.ibm.com/gls2000/glsvlsi_2000.nsf
                          glsvlsi@watson.ibm.com

===============================================================================

The 10th Great Lakes Symposium on VLSI will be sponsored by the IEEE Computer
Society and hosted by Northwestern University, Department of Electrical
and Computer Engineering. Original, unpublished papers, describing
research in the general area of VLSI are solicited. Authors should clearly
state their contribution to the state-of-the-art. Both theoretical and
experimental research results are welcome. Proceedings will be available at
the Symposium. Topics of interest will include, but are not limited to:


1. VLSI System Design. Design of low power systems, microprocessors and
   micro-architectures, embedded processors, ASIC systems, mixed analog and
   digital VLSI systems, multi-chip modules,

2. Computer-Aided Design. Hardware/software co-design, logic and
   behavioral synthesis, simulation and formal verification, layout tools
   partitioning, placement, routing, floorplanning, compaction, etc.), digital
   testing and testable design, analog testing and mixed mode testing, VLSI
   algorithms and complexity analysis,

3. VLSI Circuits. RF and communication circuits, low power circuit techniques,
   analog and digital circuits, chaos, neural and fuzzy logic circuits, high-
   speed circuit design techniques,

4. Nanotechnology. Emerging technologies (resonant tunneling devices, single
   electron transistors, quantum devices, molecular electronics), circuit design
   using quantum electronic devices, modeling and simulation tools for
   nanoelectronic devices and circuits,

5. Micro-Electro-Mechanical Systems (MEMS). MEMS technology and system design,
   CAD tools for MEMS, MEMS applications for wireless communications.


IMPORTANT DATES:

        Submission Deadline:            October 22, 1999
        Acceptance Notification:        November 19, 1999
        Camera-Ready Paper Due:         December 10, 1999


SUBMISSION OF PAPERS:

Authors should submit full-length, original, unpublished papers (maximum 15
pages double spaced) along with an abstract of at most 200 words and contact
information (name, street/mailing address, telephone,/fax, e-mail).
Previously published papers or papers submitted for publication to other
conferences/journals will not be considered.  Electronic submission via
uuencoded e-mail is required.  Please email a single postscript file, formatted
for 8 1/2" x 11" paper, compressed with Unix "compress" or "gzip" to:

        kaushik@ecn.purdue.edu


CONTACT INFORMATION:

        Email:  glsvlsi@watson.ibm.com
        Web:    http://domino.watson.ibm.com/gls2000/glsvlsi_2000.nsf


SYMPOSIUM ORGANIZATION:

    General Chairs:             M. Sarrafzadeh (Northwestern)
                                P. Banerjee (Northwestern)
    Steering Committee Chair:   N. Sherwani (Intel)
    Program Chair:              K. Roy (Purdue)
    Program Committee:          J. Abraham (UT-Austin)
                                V. Agrawal (Lucent)
                                D. Bouldin (U. Tennessee)
                                S. Blanton (CMU)
                                A. Chandrakasan (MIT)
                                J. Cong (UCLA)
                                A. Farrahi (IBM)
                                J. Figueras (U. Catalunya, Spain)
                                E. Friedman (U. Rochester)
                                I. Hajj (UIUC)
                                S. Kang (UIUC)
                                C.-K. Koh (Purdue)
                                E. Macii (Torino, Italy)
                                P. Mazumder (U. Michigan)
                                K. Muhammad (TI)
                                S. Nag (Xilinx)
                                K. Parhi (U. Minnesota)
                                S. Raje (Monterey Design)
                                D. Somasekhar (Intel)
                                K. Usami (Toshiba, Japan)
    Publication Chair:          C.-K. Koh (Purdue)
    Publicity Chair:            A. Farrahi (IBM)
    Local Chair:                J. Crenshaw (Motorola)
    Finance Chair:              J. Lavelle (Northwestern)

===============================================================================



Article 18569 of comp.arch.fpga:
Article: 18310
Subject: Re: Altera's MaxplusII: incremental compilation
From: mikeharwood@yahoo.com
Date: Thu, 14 Oct 1999 03:27:23 GMT
Links: << >>  << T >>  << A >>
Hi,

I had a similar problem. You may be able to solve your problem
by doing the following.

1) Fix your original design by back-annotating the project

2) re-run the synthesis with everything fixed but output an AHDL
    results file. This should output multiple design files representing
     each module of your design

3) If you know where the Flop is to be added you should be able to
   manually insert it in the AHDL file.

4) re-synthesize with the AHDL as source - you should get the same
result with the new flop added it - hopefully in a reasonal place. If
not you can manually add alocation property to the new device.

Regards

Mike Harwood


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 18311
Subject: Re: Xilinx FPGA Programmer
From: Ray Andraka <randraka@ids.net>
Date: Wed, 13 Oct 1999 23:38:48 -0400
Links: << >>  << T >>  << A >>
The XNF files are the old netlist format for input to the place and route tools.  You can't put an xnf
file directly into the device.  The Xilinx devices do not get programmed by a 'programmer', as they are
SRAM based devices.  SRAM based devices hold their program only as long as power is applied to the part.
Turn off power and poof, no program.  The bitstream generated by the xilinx tools is normally programmed
either in a PROM (serial or byte wide) or written to a file that is used by a microprocessor in the
system with the FPGA to load the FPGA.

In any case, you will need to obtain the xilinx place and route tools which will translate the xnf or
edif netlist generated by your design capture or synthesis tool to a bitstream.  Check the xilinx website
http://www.xilinx.com for more information.

Sharad Kumar wrote:

> Hi,
>
> I am interested in downloading my design in the xilinx netlist file format (.xnf) onto a Xilinx FPGA.
> I wated to to know what kind of device programmers are available, what would be a good option and
>  where I can get more information  about it. I am keen to use either the Xilinx -4000 series or the
>  Xilinx Virtex series of FPGA's.
>
> thanks, sharad



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka




Article 18573 of comp.arch.fpga:
Article: 18312
Subject: Xilinx FPGA Programmer
From: "Sharad Kumar" <sharad17@hotmail.com>
Date: 13 Oct 1999 20:29:14 -0800
Links: << >>  << T >>  << A >>

Hi,

I am interested in downloading my design in the xilinx netlist file format (.xnf) onto a Xilinx FPGA. 
I wated to to know what kind of device programmers are available, what would be a good option and
 where I can get more information  about it. I am keen to use either the Xilinx -4000 series or the
 Xilinx Virtex series of FPGA's.

thanks, sharad


Article 18571 of comp.arch.fpga:
Article: 18313
Subject: Reading a Lattice ispLSI 1016
From: bureauc@hotmail.com (X)
Date: Thu, 14 Oct 1999 04:30:01 GMT
Links: << >>  << T >>  << A >>
This may be a stupid question, but I'm pretty new to the PLD world, so
here goes:

Basically, I have a Lattice in-circuit programmable ispLSI 1016 that
is not read-protected. I need to read it out and re-write it to
another identical part in an updated board in order to test my circuit
changes (to the board, not the PLD programming). The writing part is
easy, as it's an in-circuit programmable part, and there is a program
to do that through the PC parallel port on their website, however it
doesn't seem to have any provisions for reading the chip. 

Thanks in advance.

jds


Article 18574 of comp.arch.fpga:
Article: 18314
Subject: Need info about a FAST adders. How built it? (0)
From: Victor Levandovsky <vic@alpha.podol.khmelnitskiy.ua>
Date: Thu, 14 Oct 1999 08:10:25 +0300
Links: << >>  << T >>  << A >>
:))


Article 18575 of comp.arch.fpga:
Article: 18315
Subject: Virtex Board
From: "abdulqadir alaqeeli" <alaqeeli@bobcat.ent.ohiou.edu>
Date: Thu, 14 Oct 1999 01:31:17 -0400
Links: << >>  << T >>  << A >>
Hi,
Does anyone know where I find a PCI Board with a Virtex Chip?
I found the following two companies:
Avnet:  http://www.em.avnet.com/semi/marketing/xlx-19990526semw.html
Embedded Solutions Ltd  ( RC1000-PP)

I need any helpful information so I can choose a good board.

Abdul





Article 18576 of comp.arch.fpga:
Article: 18316
Subject: Re: Virtex Board
From: Harald Simmler <simmler@ti.uni-mannheim.de>
Date: Thu, 14 Oct 1999 08:26:24 +0200
Links: << >>  << T >>  << A >>
Have a look at the optimagic web side. You will find all available 
FPGA boards there.

http://www.optimagic.com/index.shtml

abdulqadir alaqeeli schrieb:
> 
> Hi,
> Does anyone know where I find a PCI Board with a Virtex Chip?
> I found the following two companies:
> Avnet:  http://www.em.avnet.com/semi/marketing/xlx-19990526semw.html
> Embedded Solutions Ltd  ( RC1000-PP)
> 
> I need any helpful information so I can choose a good board.
> 
> Abdul

-- 

---------------------------------------------------------------------------
Harald Simmler                               Lehrstuhl fuer Informatik V
                                             Universitaet Mannheim
Tel:    +49-621-181-2632   ! NEW !           B6, 26
Fax:    +49-621-181-2634   ! NEW !           D-68131 Mannheim 
eMail:   simmler@ti.uni-mannheim.de          Germany


Article 18577 of comp.arch.fpga:
Article: 18317
Subject: compiling vhdl code(help please)
From: Ben <ejhong@future.co.kr>
Date: Thu, 14 Oct 1999 08:24:48 GMT
Links: << >>  << T >>  << A >>
When I try to compile a vhdl code for simulation with Synopsys tools and
the following command,
---
    vhdlan -nc -check -w mylib ./mydesign.vhd
---

the vhdl code is analyzed, but there come warning messages like
---
    Warning: vhdlan, 1500 ./mydesign.vhd(321):

        Error compiling file : ./mylib/mydesign__RTL.c, Reverting to
Interpreted code for design unit : RTL.

    Warning: vhdlan, 1504 ./mydesign.vhd(321):

        The C compiler, specified as /opt/SUNWspro/bin/cc, doesn't work
properly.
        Change CS_CCPATH in the setup file or specify a path by the
-ccpath option.
        Reverting to Interpreted Code.
---

I don't think there's really a problem with the specified C compiler
since it exists and works well with C code.
I also tried changing the -ccpath option to /usr/ucb/cc, but the result
is same.

Could anybody please help me with this?

TIA,

Ben

--
Ben Hong
Future Systems, Inc.
Phone : +82-2-578-0581 (ext. 533)
Fax   : +82-2-578-0584
Email : ejhong@future.co.kr




Article 18579 of comp.arch.fpga:
Article: 18318
Subject: test
From: Also-Antal Csaba <antalcs@mail.matav.hu>
Date: Thu, 14 Oct 1999 10:50:14 +0200
Links: << >>  << T >>  << A >>
sorry


Article 18587 of comp.arch.fpga:
Article: 18319
Subject: Virtex FPGA PCI select I/O Characteristics.
From: Mahboob Ahmed <m.ahmed@ieee.org>
Date: Thu, 14 Oct 1999 09:26:23 GMT
Links: << >>  << T >>  << A >>
Hi,
   I need detailed virtex FPGA PCI select I/O (PCI33_5,PCI33_3,
PCI66_3) characteristics, especially their timing and delay
specifications. Please specify where to find it, if anybody knows.

Mahboob Ahmed
And-Or Logic Inc.


Sent via Deja.com http://www.deja.com/
Before you buy.


Article 18580 of comp.arch.fpga:
Article: 18320
Subject: Re: Virtex Board
From: Ray Andraka <randraka@ids.net>
Date: Thu, 14 Oct 1999 08:39:59 -0400
Links: << >>  << T >>  << A >>
go to http://www.optimagic.com  there is a fairly comprehensive list of
boards on that site.

abdulqadir alaqeeli wrote:

> Hi,
> Does anyone know where I find a PCI Board with a Virtex Chip?
> I found the following two companies:
> Avnet:  http://www.em.avnet.com/semi/marketing/xlx-19990526semw.html
> Embedded Solutions Ltd  ( RC1000-PP)
>
> I need any helpful information so I can choose a good board.
>
> Abdul



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka




Article 18581 of comp.arch.fpga:
Article: 18321
Subject: Re: Need info about a FAST adders. How built it? (0)
From: Ray Andraka <randraka@ids.net>
Date: Thu, 14 Oct 1999 08:42:51 -0400
Links: << >>  << T >>  << A >>
Need more info.  Presumably for an FPGA, but which one?  How many bits?
If it is an FPGA with a carry chain (xilinx, altera or lucent) then it
is hard to beat the ripple carry adder using the carry chain for widths
up to about 32 bits.  If that is the case, look at the vendor literature
and if you can, the insides of their macros for an idea of how they are
put togehter.

Victor Levandovsky wrote:

> :))



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka




Article 18582 of comp.arch.fpga:
Article: 18322
Subject: Estimating Gates in FPGA
From: thomas.hedler@fen.baynet.de
Date: Thu, 14 Oct 1999 14:52:05 +0200
Links: << >>  << T >>  << A >>
Hello!

I want to know how I can estimate the necessary gates used
by my design in a Xilinx Virtex.
In another message I read that a LUT is about 4.5 Gates. OK.
But my Synthesis-Tool (Leonardo Spectrum) outputs IOBUF, MUX
etc., too.
Are there any numbers for this blocks, too?

Thomas


Article 18583 of comp.arch.fpga:
Article: 18323
Subject: Re: Virtex Board
From: "smart" <smart@smart.netlineuk.net>
Date: Thu, 14 Oct 1999 19:56:39 +0100
Links: << >>  << T >>  << A >>
Hi Abdul,

You could try Alpha Data http://www.alphadata.co.uk they have PCI and PMC
based Virtex boards.


abdulqadir alaqeeli wrote in message ...
>Hi,
>Does anyone know where I find a PCI Board with a Virtex Chip?
>I found the following two companies:
>Avnet:  http://www.em.avnet.com/semi/marketing/xlx-19990526semw.html
>Embedded Solutions Ltd  ( RC1000-PP)
>
>I need any helpful information so I can choose a good board.







Article 18584 of comp.arch.fpga:
Article: 18324
Subject: Need a Lucent chip in T100 package.
From: husby@fnal.gov (Don Husby)
Date: Thu, 14 Oct 1999 21:38:55 GMT
Links: << >>  << T >>  << A >>
Hi,
I need any one of the following Lucent FPGAs in a 100-pin TQFP
as soon as possible:

OR2C04A4-T100
OR2C04A3-T100
OR2C06A4-T100
OR2C06A3-T100

Anyone have one of these laying around?



--
Don Husby <husby@fnal.gov>             http://www-ese.fnal.gov/people/husby
Fermi National Accelerator Lab                          Phone: 630-840-3668
Batavia, IL 60510                                         Fax: 630-840-5406


Article 18585 of comp.arch.fpga:


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search