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Messages from 19050

Article: 19050
Subject: Re: Non-dedicated clock
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Thu, 25 Nov 1999 17:46:29 +0200
Links: << >>  << T >>  << A >>
> Dear friend,
> Yesterday  I have got following message from Xilinx Alliance design
> manager
> 
> WARNING:Timing:33 - Clock nets using non dedicated resources were found
> in this
>    design. Clock skew on these resources will not be automatically
> addressed
>    during path analysis. To create a timing report that analyzes clock
> skew for
>    these paths, run trce with the '-skew' option.
> 
> But I'm sure to use only dedicated clock resources. And place all my
> clock nets on bufg or bufgp.
> 1. How can I find out which net exactly or in which component Xilinx
> means.
> 2. I have never started trce manualy. Is it any say to Design manager
> to run trce with -skew option.

  I think you are using Xilinx Design Manager M2.1i.

  The warning is related to a clock net that is used in a logic or directly
  in a pad. For example, you can sample this clock with another clock, which
  normally runs in higher rate. The other application is, you have gated clock.
  For example and internal signal is ANDed with this clock and the output
  of the AND gate is connected as an output to the pad of the FPGA.

  In both cases, clock is connected to a logic, other than FF. In this case
  clock must travel in some routing resources. This warning describes this
  fact. This is not an error, this is the nature of your design. Clock is
  not only used for clocking, but also for logic functions, although they
  say "avoid gating clock in FPGA".

  Utku
Article: 19051
Subject: Re: async latch implementation in Leonardo
From: Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid>
Date: Thu, 25 Nov 1999 07:46:30 -0800
Links: << >>  << T >>  << A >>
Sorry for smal typing error in programm,
it must be so:
 library ieee; use ieee.std_logic_1164.all;
 entity  LT  is
 port (o : out std_logic ;
        r : in std_logic ;
       s : in std_logic );
 end;
 architecture  LT  of  LT  is
 begin
 process (R,S)
 begin
   if  R='0' then o <='0';
       else if S='0' then o <='1';
             end if;
    end if;
 end process;
 end;





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Article: 19052
Subject: Xilinx Virtex design (xcv-800) into production
From: arafeeq@my-deja.com
Date: Thu, 25 Nov 1999 17:51:55 GMT
Links: << >>  << T >>  << A >>
Hello all!

Has anyone put the xilinx's virtex (xcv-800-bga432) device into
Production. If yes, what was the EDA tools flow used. like..

Verilog/vhdl/synplify/or fpga-express or fpga compiler II or leonardo
/alliance tools etc...


I appreciate the answers,

Best Regards,


Abdul Rafeeq.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19053
Subject: Re: implementing TCP/IP on PLD
From: "Dirk Bruere" <artemis@kbnet.co.uk>
Date: Fri, 26 Nov 1999 01:15:12 -0000
Links: << >>  << T >>  << A >>

Mark Summerfield <m.summerfield@ieee.org> wrote in message
news:383CE6DF.A07AFB46@ieee.org...
> > Depends what you mean by 'hardware implementation'. Do you mean single
chip
> > micro using a gate array? State machine that is not quite single chip
micro,
> > or 'random logic' with TCP/IP hardwired - no microcode?

> Well, I haven't seen iReady's code, but if it's written entirely in
> Verilog RTL, requires 67k gates, and is technology and library independent
> (all their claims), then I think it qualifies as a hardware
implementation.
> It includes TCP, UDP, IP and PPP implementations, and a serial interface.
> It also appears to require 20k of external memory as a buffer for packets.
> And an external microprocessor (or equivalent) to actually control it.

> I would assume that it contains many state machines, and a lot of "random
> logic".  And maybe some simple microcode for some of the state machines,
> I guess.  I don't actually understand the distinction you're trying to
> draw -- all these are valid digital design techniques which result in
> "hardware".

The point I am trying to make is that calling something a 'hardware
implementation' or a 'software implementation' is getting meaningless these
days. Eventually it comes to where you draw an arbitrary % line.

What I wanted when I did my stack port earlier this year was UART one side
and an Ethernet interface the other, with TCP/IP in the middle and me having
to know nothing of its insides.

Dirk



Article: 19054
Subject: XTP
From: #YEO WEE KWONG# <P7102672H@ntu.edu.sg>
Date: Fri, 26 Nov 1999 09:58:21 +0800
Links: << >>  << T >>  << A >>
Your remark: If you are looking for a network protocol for hardware
implementation,
why not look at XTP (express transfer protocol, designed by Greg
Chesson in the late 1980's).  This protocol would be much easier to
implement in hardware.  Also, you would have to add a lot of structure
to the problem ( such as decomposing the problem into correct sub
problems before giving it to the undergraduates ).

My comment:

However XTP may not be well endorsed by the current networking world
hence, that would not answer the objective of providing connectivity to
the current devices.

-----Original Message-----
From: gillies@cs.ubc.ca (Donald Gillies) [ mailto:gillies@cs.ubc.ca
<mailto:gillies@cs.ubc.ca> ]
Posted At: 24 November 1999 07:23
Posted To: comp.arch.fpga
Conversation: implementing TCP/IP on PLD
Subject: Re: implementing TCP/IP on PLD


"Dirk Bruere" <artemis@kbnet.co.uk> writes:

>Joseph C. Su <sujosep@sympatico.ca> wrote in message
> news:cEo_3.62916$up3.99009@news21.bellglobal.com
<news:cEo_3.62916$up3.99009@news21.bellglobal.com> ...
>> Do you think it is realistic for an undergraduate design project to
>> undertake the task of implementing TCP/IP on FPGA ( i dare not to use
the
>> term "pld" anymore), given a team of three not very smart students?

TCP is an unrealistic thing to implement on an FPGA - no matter what
the time frame, no matter who is doing it.  A good TCP has some very
complex sub-algorithms.

Moreover, another problem is that a protocol such as TCP is extremely
hard to understand and define fully, and it is unlikely for some
undergraduates to even understand the problem fully in a 1-semester
time frame.

These two issues are a recipe for disaster.

Once upon a time, I wrote a software TCP on my own in 1 semester as
part of my MIT undergraduate thesis.  Because of the difficulty, the
TCP became the *entire* thesis - and in those days I used to win
programming contests for my speed at programming.  I had a working
single-process TCP already (PC/IP) and the "TCP Implementer's Guide"
which is part of RFC793.  I barely got it working and then I "de-tuned
it" so that it would work with slightly flakey other types of TCP's.
This was a very full one semester project, about 4 hours a day (the
whole afternoon) From Jan 1st through May 10th.

If you are looking for a network protocol for hardware implementation,
why not look at XTP (express transfer protocol, designed by Greg
Chesson in the late 1980's).  This protocol would be much easier to
implement in hardware.  Also, you would have to add a lot of structure
to the problem ( such as decomposing the problem into correct sub
problems before giving it to the undergraduates ).


Don Gillies - t_dgilli.x@qualcomm.x.com - Planetwide Software, Inc.
(consultant) / Globalstar Satellite CDMA Project, Qualcomm Inc.,
6455 Lusk Blvd San Diego, California 92121 - phone: 619-651-2326.
Adjunct Professor of EE, UBC, Vancouver BC Canada V6T 1Z4
http://www.ee.ubc.ca/home/staff/faculty/gillies/etc/www/index.html
<http://www.ee.ubc.ca/home/staff/faculty/gillies/etc/www/index.html> 
(remove x's to reply by email)



Article: 19055
Subject: implementing TCP/IP on PLD
From: #YEO WEE KWONG# <P7102672H@ntu.edu.sg>
Date: Fri, 26 Nov 1999 10:03:34 +0800
Links: << >>  << T >>  << A >>

correct me if i am wrong, Iready chipset does not need a microprocessor
to control it, rather it serves as a mean to send and receive data. That
mimics a typical system.


-----Original Message-----
From: Mark Summerfield [ mailto:m.summerfield@ieee.org
<mailto:m.summerfield@ieee.org> ]
Posted At: 25 November 1999 15:36
Posted To: comp.arch.fpga
Conversation: implementing TCP/IP on PLD
Subject: Re: implementing TCP/IP on PLD


Dirk Bruere wrote:
> Depends what you mean by 'hardware implementation'. Do you mean single
chip
> micro using a gate array? State machine that is not quite single chip
micro,
> or 'random logic' with TCP/IP hardwired - no microcode?

Well, I haven't seen iReady's code, but if it's written entirely in
Verilog RTL, requires 67k gates, and is technology and library
independent
(all their claims), then I think it qualifies as a hardware
implementation.
It includes TCP, UDP, IP and PPP implementations, and a serial
interface.
It also appears to require 20k of external memory as a buffer for
packets.
And an external microprocessor (or equivalent) to actually control it.

I would assume that it contains many state machines, and a lot of
"random
logic".  And maybe some simple microcode for some of the state machines,
I guess.  I don't actually understand the distinction you're trying to
draw -- all these are valid digital design techniques which result in
"hardware".

You can decide for yourself if you think it qualifies as a hardware
implementation.  There's more information on their web site:
    http://www.iready.com/products/internet_tuner.html
<http://www.iready.com/products/internet_tuner.html> 

Mark



Article: 19056
Subject: Analog
From: Luigi <andyf@telerama.com>
Date: Thu, 25 Nov 1999 21:38:56 -0500
Links: << >>  << T >>  << A >>
I read this board all the time and pick up alot of valuable info.  I am
mainly a Xilinx user, but also spent the last year doing Altera
designs.  However, there are times when I have to put the digital stuff
aside for a while and put on my analog cap.  Problem is...I can do
pretty well in the analog world also, but I'm no analog guru.  Does
someone out there know a good analog person I can get in touch with to
ask questions about certain amplifier configurations using Current
Feedback Amplifiers.  I've always used Voltage Feedback Amps.  The sad
thing is, it doesn't seem like the App Engineers from Analog Devices,
Burr-Brown, etc...have a real grasp on basic configurations with these
devices so I am going to the sources that I feel are most knowledgable
on many subjects.....you guys.  Any names or contacts for the above
would be of great help.  Thanks alot and I will probably never post an
analog request on this page for another couple of years, I promise.
I'll be back on my Xilinx designs again soon I hope!

Luigi

Article: 19057
Subject: Re: Analog
From: Mark Summerfield <m.summerfield@ieee.org>
Date: Fri, 26 Nov 1999 16:09:14 +1100
Links: << >>  << T >>  << A >>
Luigi wrote:
> 
> pretty well in the analog world also, but I'm no analog guru.  Does
> someone out there know a good analog person I can get in touch with to
> ask questions about certain amplifier configurations using Current
> Feedback Amplifiers.  I've always used Voltage Feedback Amps. 

My "real-world" experience with analog design is limited, but for what 
it's worth, the textbook we are currently using here in one of our 
undergraduate electronics courses is pretty good.  It's called 
"Electronics: A Top-Down Approach to Computer-Aided Circuit Design"
by Allan R. Hambley.  Chapter 8 is on feedback; Sections 8.4 to 8.10
in particular cover the four basic types of feedback, their effects 
on gain, input impedance and output impedance, and practical feedback
networks with ideal and non-ideal amplifiers.

The approach in Gray and Meyer's "Analog Integrated Circuits" (Chapters
8 and 9) is more fundamental and rigorous, but it's harder to digest as
well (which is not to say it isn't worth the effort).

Hope this is of some help.

Mark
Article: 19058
Subject: Re: Programming Virtex device via JTAG
From: Michael Schmid <mlschmid@iis.fhg.de>
Date: Fri, 26 Nov 1999 08:44:18 +0000
Links: << >>  << T >>  << A >>
Bill Blyth wrote:
> 
> In article <383AE573.C80AF8FE@arl.wustl.edu>,
> 
> As far as I know, the state of the mode pins does not matter. On my own
> board the mode can be either 111 or 110 (slave serial or selectmap) and
> in either state can be programmed over JTAG.
> 
> I do notice that if the device is already configured, DONE does not
> change. I suspect that the configuration over JTAG is a partial one.
> 
> I always have INIT pulled up because the device will indicate an error
> by pulling it low. PROG does not have to be toggled to get JTAG to work.
>   Tom McLaughlin <tomm@arl.wustl.edu> wrote:
> > Michael,
> > Thanks for the advice.  I'm still having problems.  We didn't design
> the board
> > which is one of the problems.  One thing I noticed is that you guys
> put the
> > config pins on "000" for configuration.  We put them on 101 for "JTAG
> mode"  I
> > thought that is what it had to be on to config through the JTAG
> port.  Again,
> > the JTAG programmer software says that the device is programmed, but
> it is like
> > the device never goes through it's startup sequence.  DONE never goes
> high.
> > When I have access to the board again, I'll try configuring with the
> pins on
> > "000".
> >
> > The other thing I noticed is that you mention the program pin.  We
> don't
> > manipulate this pin.  Should we???  You mention that it is for PROM
> > configuration.  Again, we are trying to program via JTAG.  Should we
> have to
> > pull the PROGRAM pin low and then let it go high to program via
> JTAG???
> > Tom
> >
> > >
> > >
> > > Hi Tom,
> > >
> > > We'v done JTAG configuration of virtex
> > > XCV300 with  XChecker and also with a
> > > selfmade interface for parallelport
> > > (Application Note Xilinx). There were no
> > > problems. I think the pullup on init is
> > > ok (we have the same).
> > > I will tell you the other configuration
> > > pins for orientation:
> > >
> > >
> >
> >
> 
> --
> -----------------------------
> Alpha Data
> -----------------------------
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

Hi Bill,


I think the same way like you with the
configuration pins (and also the Xilinx
Datasheet). JTAG works in every
configuration mode. The init pin must be
high (Tom has this and we too). For JTAG
configuration toggling of the program
signal shouldn't be necessary, you're
right. But do you know what happens if
Tom has the program pin low or floating?
This could explain why I can program my
virtex via JTAG (program is stable high
after several time) and Tom isn't able
to (maybe pulldown on program). What do
you think? 



Bye,


Michael


mlschmid@iis.fhg.de
Article: 19059
Subject: Re: Programming Virtex device via JTAG
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 26 Nov 1999 10:30:11 +0000
Links: << >>  << T >>  << A >>


Michael Schmid wrote:

>
> Hi Bill,
>
> I think the same way like you with the
> configuration pins (and also the Xilinx
> Datasheet). JTAG works in every
> configuration mode. The init pin must be
> high (Tom has this and we too). For JTAG
> configuration toggling of the program
> signal shouldn't be necessary, you're
> right. But do you know what happens if
> Tom has the program pin low or floating?
> This could explain why I can program my
> virtex via JTAG (program is stable high
> after several time) and Tom isn't able
> to (maybe pulldown on program). What do
> you think?
>
> Bye,
>
> Michael
>
> mlschmid@iis.fhg.de

If JTAG works in all modes then any idea why there are special mode pin
settings for JTAG ?

rick@algor.co.uk

Article: 19060
Subject: How one can use level sensitive latches
From: Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid>
Date: Fri, 26 Nov 1999 02:41:52 -0800
Links: << >>  << T >>  << A >>
Hi experts,
I ' using Leonardo for synthesys, alliance 2.1i. for implementation to
Virtex.

The storage elements in the Virtex slice can be configured as level
sensitive latches.

Is it any way to say Leonardo to do so?

(See also discussion "Re: async latch implementation in Leonardo"
in comp.lang.VHDL group)


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Article: 19061
Subject: HDL editor?
From: "Ahmad A." <aa939788@oak.cats.ohiou.edu>
Date: Fri, 26 Nov 1999 13:12:49 +0100
Links: << >>  << T >>  << A >>
Hi..
Can any one tell me where can I find Free, Student edition, or Shareware HDL
editor?

Thank you in advanced.
Ahmad.


Article: 19062
Subject: Programming Virtex device via JTAG
From: Malachy Devlin <m.devlin@nallatech.com>
Date: Fri, 26 Nov 1999 12:31:10 -0000
Links: << >>  << T >>  << A >>
Tom,


I believe your problem may that you do not configure the bitstream so
that the configuration is completed with the JTAG clock. In the
configuration options when you go to the implementation stage, change
the start-up clock from CCLK to JTAG. Otherwise you configure but the
Virtex doesn't finish it configuration process.

BTW. The setting of the mode pins doesn't matter for JTAG configuration
on the Virtex

regards

Malachy

--------------------------------------------------
Dr. Malachy Devlin    Tel: +44 (0)7020 98 65 32
Nallatech Ltd         Fax: +44 (0)7020 98 65 34
10-14 Market Street   mailto:m.devlin@nallatech.com
Kilsyth               http://www.nallatech.com
Glasgow, UK, G65 0BD
--------------------------------------------------  


> -----Original Message-----
> From: Michael Schmid [mailto:mlschmid@iis.fhg.de]
> Posted At: 25 November 1999 09:20
> Posted To: fpga
> Conversation: Programming Virtex device via JTAG
> Subject: Re: Programming Virtex device via JTAG
> 
> 
> Tom McLaughlin wrote:
> > 
> > Michael,
> > Thanks for the advice.  I'm still having problems.  We 
> didn't design the board
> > which is one of the problems.  One thing I noticed is that 
> you guys put the
> > config pins on "000" for configuration.  We put them on 101 
> for "JTAG mode"  I
> > thought that is what it had to be on to config through the 
> JTAG port.  Again,
> > the JTAG programmer software says that the device is 
> programmed, but it is like
> > the device never goes through it's startup sequence.  DONE 
> never goes high.
> > When I have access to the board again, I'll try configuring 
> with the pins on
> > "000".
> > 
> > The other thing I noticed is that you mention the program 
> pin.  We don't
> > manipulate this pin.  Should we???  You mention that it is for PROM
> > configuration.  Again, we are trying to program via JTAG.  
> Should we have to
> > pull the PROGRAM pin low and then let it go high to program 
> via JTAG???
> > Tom
> > 
> > >
> > >
> > > Hi Tom,
> > >
> > > We'v done JTAG configuration of virtex
> > > XCV300 with  XChecker and also with a
> > > selfmade interface for parallelport
> > > (Application Note Xilinx). There were no
> > > problems. I think the pullup on init is
> > > ok (we have the same).
> > > I will tell you the other configuration
> > > pins for orientation:
> > >
> > >
> 
> 
> 
> Hi Tom,
> 
> I don't know exactly if the program pin
> is necessary in your BSCAN-Mode (101).
> I'v read in the Virtex Manual and found
> on side 21 a description of
> configuration sequence. I think if you
> hold program low the FPGA will do
> nothing exept resetting its memory. If
> then program goes high the FPGA is ready
> for configuration. 
> 
> Our program Signal is everytime
> available (low, high after 100ms) in
> PROM or JTAG Configuration. Maybe this
> is the case it works?
> 
> 
> 
> 
> 
> I hope this will help You, 
> 
> 
> Michael
> 

Article: 19063
Subject: Re: Programming Virtex device via JTAG
From: "Bill Blyth" <bb@alphadata.co.uk>
Date: Fri, 26 Nov 1999 12:31:37 -0000
Links: << >>  << T >>  << A >>
Perhaps the benefit is that the device behaves properly when JTAG mode is
selected - I don't know because I can't select it on my boards.

Certainly when SelectMap is the mode, JTAG will work but DONE never changes
during configuration which kind of implies it is reconfiguration without
clearing first. This can lead to odd problems like DLL malfunction for
example.

Bill

Rick Filipkiewicz <rick@algor.co.uk> wrote in message
news:383E6133.D708DC31@algor.co.uk...
>
>
> Michael Schmid wrote:
>
> >
> > Hi Bill,
> >
> > I think the same way like you with the
> > configuration pins (and also the Xilinx
> > Datasheet). JTAG works in every
> > configuration mode. The init pin must be
> > high (Tom has this and we too). For JTAG
> > configuration toggling of the program
> > signal shouldn't be necessary, you're
> > right. But do you know what happens if
> > Tom has the program pin low or floating?
> > This could explain why I can program my
> > virtex via JTAG (program is stable high
> > after several time) and Tom isn't able
> > to (maybe pulldown on program). What do
> > you think?
> >
> > Bye,
> >
> > Michael
> >
> > mlschmid@iis.fhg.de
>
> If JTAG works in all modes then any idea why there are special mode pin
> settings for JTAG ?
>
> rick@algor.co.uk
>


Article: 19064
Subject: slightly OT ...
From: rk <stellare@NOSPAM.erols.com>
Date: Fri, 26 Nov 1999 08:53:08 -0500
Links: << >>  << T >>  << A >>
... but perhaps close enough for government work.

hi,

i'm looking to get some pals in low quantity ... just need a handful for
evaluation, the coooool runners.  the 22v10 works well in my test set
and i believe the part numbers are: P3Z22V10 and XCR22LV10.  anyways,
i'm pretty flexible.  also, how many different foundries make these
devices?  how do i tell them apart?

i did find some from a distributor but they had like a $200 minimum
order per part type and that sort of seems a lot for a quick
evaluation.  does any know where i could find some in low quantities for
eval?

thanks a bunch,

------------------------------------------------------------------------

rk                                 The world of space holds vast promise

stellar engineering, ltd.          for the service of man, and it is a
stellare@erols.com.NOSPAM          world we have only begun to explore.
Hi-Rel Digital Systems Design      -- James E. Webb, 1968




Article: 19065
Subject: Re: Analog
From: me@here.com (myself)
Date: Fri, 26 Nov 1999 14:08:46 GMT
Links: << >>  << T >>  << A >>
try the application engineers at "analog devices" their analog parts,
tech help and web site are all quite good.


On Thu, 25 Nov 1999 21:38:56 -0500, Luigi <andyf@telerama.com> wrote:

>I read this board all the time and pick up alot of valuable info.  I am
>mainly a Xilinx user, but also spent the last year doing Altera
>designs.  However, there are times when I have to put the digital stuff
>aside for a while and put on my analog cap.  Problem is...I can do
>pretty well in the analog world also, but I'm no analog guru.  Does
>someone out there know a good analog person I can get in touch with to
>ask questions about certain amplifier configurations using Current
>Feedback Amplifiers.  I've always used Voltage Feedback Amps.  The sad
>thing is, it doesn't seem like the App Engineers from Analog Devices,
>Burr-Brown, etc...have a real grasp on basic configurations with these
>devices so I am going to the sources that I feel are most knowledgable
>on many subjects.....you guys.  Any names or contacts for the above
>would be of great help.  Thanks alot and I will probably never post an
>analog request on this page for another couple of years, I promise.
>I'll be back on my Xilinx designs again soon I hope!
>
>Luigi
>

Article: 19066
Subject: Re: HDL Editor
From: Marco Sanvido <sanvido@aut.ee.ethz.ch>
Date: Fri, 26 Nov 1999 16:38:24 +0100
Links: << >>  << T >>  << A >>
Have a look at the
Programmable Jump Station -> http://www.optimagic.com/index.shtml

You will find more information on available HDL (also free and
shareware)
______________________________________________________________
Marco Sanvido
Article: 19067
Subject: Re: HDL editor?
From: bob@nospam.thanks (Bob Perlman)
Date: Fri, 26 Nov 1999 17:37:10 GMT
Links: << >>  << T >>  << A >>
Hi - 

On Fri, 26 Nov 1999 13:12:49 +0100, "Ahmad A."
<aa939788@oak.cats.ohiou.edu> wrote:

>Hi..
>Can any one tell me where can I find Free, Student edition, or Shareware HDL
>editor?
>
>Thank you in advanced.
>Ahmad.
>

One editor I've been very happy with is UltraEdit.  It's easy to use,
loaded with features and, while not an HDL editor as such, has
configurable syntax coloring.  There are syntax coloring files
available for Verilog, VHDL, and just about any other programming
language you can think of.  And the price is right: use it free for a
month or so, then pay $30 if you like it.
 
The software can be downloaded from:

http://www.idmcomp.com/

I now use UltraEdit for all my text editing.  It's easily the biggest
software bargain on my computer.

I have no connection, business or otherwise, with the folks who did
UltraEdit.  I'm just a happy customer.

Take care,
Bob Perlman

-----------------------------------------------------
Bob Perlman
Cambrian Design Works
Digital Design, Signal Integrity
http://www.best.com/~bobperl/cdw.htm
Send e-mail replies to best<dot>com, username bobperl
-----------------------------------------------------
Article: 19068
Subject: Re: Analog
From: Jonathan Bromley <jonathan@oxfordbromley.u-net.com>
Date: Fri, 26 Nov 1999 18:17:00 +0000
Links: << >>  << T >>  << A >>
Luigi wrote:
> 
> ask questions about certain amplifier configurations using Current
> Feedback Amplifiers.  I've always used Voltage Feedback Amps.  The sad
> thing is, it doesn't seem like the App Engineers from Analog Devices,
> Burr-Brown, etc...have a real grasp on basic configurations with these
> devices

App engineers are a species showing much variation among individuals,
but I can assure you that the data books and appnotes of AD and BB are
full of good stuff.

Even better, though, are appnotes from Elantec.  Look at their notes on
early CFOAs like the EL2020, written in the days when hardly any
customers
knew what a CFOA was, and the databook had a mission to educate.

What are "certain amplifier configurations" ?  Anything unlikely,
or are you just trying to get to grips with the standard stuff?

Jonathan Bromley
Article: 19069
Subject: Re: UTOPIA Interface on FPGA
From: "Amal Khailtash" <akhailtash@spacebridge.com>
Date: Fri, 26 Nov 1999 19:04:51 GMT
Links: << >>  << T >>  << A >>
You can find the UTOPIA level 1 and level 2 specs from the following links:
    ftp://ftp.atmforum.com/pub/approved-specs/af-phy-0017.000.pdf
    ftp://ftp.atmforum.com/pub/approved-specs/af-phy-0039.000.pdf

+-----------------------------------+----------------------------------+
| Name:  Amal Khailtash             | Co.: SpaceBridge Networks Corp.  |
| Title: Hardware Developer         |    (A Com Dev/NewBridge Company) |
| Email: akhailtash@spacebridge.com | Tel: +1 (819) 776-2848 x.6183    |
| URL:   http://www.spacebridge.com | Fax: +1 (819) 776-4179           |
| Addr.: 115 Champlain Street       +----------------------------------+
|        Hull, PQ J8X 3R1, Canada   |                                  |
+-----------------------------------+----------------------------------+

Franck Thierry <fthierry@videotron.ca> wrote in message
news:383CA878.87366B@videotron.ca...
> I have to interface a regular micro to an UTOPIA 1.0 Interface using a
> FPGA. I've tried to find out an application note describing this kind of
> interface on different FPGA Web Site, but it seems that today, everybody
> has IP stuff, and you have to buy it (it's quite expensive...)
>
> Is someone there has any reference or good URL about that,
>
> Thanks,
>
> -- Franck


Article: 19070
Subject: Re: HDL editor?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 26 Nov 1999 20:03:29 +0000
Links: << >>  << T >>  << A >>


Bob Perlman wrote:

> Hi -
>
> On Fri, 26 Nov 1999 13:12:49 +0100, "Ahmad A."
> <aa939788@oak.cats.ohiou.edu> wrote:
>
> >Hi..
> >Can any one tell me where can I find Free, Student edition, or Shareware HDL
> >editor?
> >
> >Thank you in advanced.
> >Ahmad.
> >

You could try [x]emacs + verilog-mode and/or vhdl-mode. There's a pretty good NT
emacs at
www.cs.washington.edu/homes/voelker and you can download a verilog-mode from
www.surefirev.com. I don't know who maintains vhdl-mode.


Article: 19071
Subject: Xilinx FPGA Editor guessing games solved!
From: "Austin Franklin" <austin@darkroom098.com>
Date: 26 Nov 1999 23:38:08 GMT
Links: << >>  << T >>  << A >>
I finally 'guessed' right on how to edit an equation in the new Xilinx FPGA
Editor.

In an XCS40, the equation editor refers to the pins as F1, F2 etc.  AND the
documentation refers to them that way.  Well, when using a Virtex, they are
referred to as A1, A2 etc.

Now, in a Virtex, if I use the FMAP designation (A1-4), instead of the CLB
pin designation (F1-4, G1-4) it takes my equations.

Can they make this tool any more user hostile?  Damn.


Article: 19072
Subject: Siemens HSCX development tools.
From: Mahboob Ahmed <m.ahmed@ieee.org>
Date: Sat, 27 Nov 1999 10:59:03 GMT
Links: << >>  << T >>  << A >>
Hello,
	I am working on Siemens' HSCX SAB82526 HDLC controller. I need the
information regarding HSCX development tool, evaluation systems, and
device driver software. If anybody has worked on Siemens HSCX 82526
systems, then please indicate. Nothing except datasheet is available on
the infineon site. They do have an evaluation system for other HDLC
controllers like 82532, but not for 82526. If anyone knows any third
party tools, and/or evaluatin boards having HSCX 82526, then please
specify. Thanks in advance.

Mahboob Ahmed.
m.ahmed@ieee.org


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19073
Subject: Re: Xilinx FPGA Editor guessing games solved!
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 27 Nov 1999 09:25:03 -0500
Links: << >>  << T >>  << A >>
Austin Franklin wrote:
> 
> I finally 'guessed' right on how to edit an equation in the new Xilinx FPGA
> Editor.
> 
> In an XCS40, the equation editor refers to the pins as F1, F2 etc.  AND the
> documentation refers to them that way.  Well, when using a Virtex, they are
> referred to as A1, A2 etc.
> 
> Now, in a Virtex, if I use the FMAP designation (A1-4), instead of the CLB
> pin designation (F1-4, G1-4) it takes my equations.
> 
> Can they make this tool any more user hostile?  Damn.

Is there a reason that you didn't call Xilinx support on this issue? I
don't always find them helpful on subtle or complex issues, but they are
usually pretty good on a basic question like this. I expect you would
have had an answer in a day or less. 

-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 19074
Subject: Re: Xilinx FPGA Editor guessing games solved!
From: "Austin Franklin" <austin@darkroom098.com>
Date: 27 Nov 1999 15:39:26 GMT
Links: << >>  << T >>  << A >>


Rickman <spamgoeshere4@yahoo.com> wrote in article
<383FE9BF.8F07E9B6@yahoo.com>...
> Austin Franklin wrote:
> > 
> > I finally 'guessed' right on how to edit an equation in the new Xilinx
FPGA
> > Editor.
> > 
> > In an XCS40, the equation editor refers to the pins as F1, F2 etc.  AND
the
> > documentation refers to them that way.  Well, when using a Virtex, they
are
> > referred to as A1, A2 etc.
> > 
> > Now, in a Virtex, if I use the FMAP designation (A1-4), instead of the
CLB
> > pin designation (F1-4, G1-4) it takes my equations.
> > 
> > Can they make this tool any more user hostile?  Damn.
> 
> Is there a reason that you didn't call Xilinx support on this issue? I
> don't always find them helpful on subtle or complex issues, but they are
> usually pretty good on a basic question like this. I expect you would
> have had an answer in a day or less. 

I did call/email Xilinx support on this issue.  What they said was 'it
works for me'.

I don't just sit around for days trying to figure things out because I have
nothing better to do, when a simple phone call/email would suffice.  I even
called another Xilinx 'expert', who is prolific in this group, and all FPGA
Editor did for him was crash...so, he was no help.

I was hoping someone here had actually USED the tool, encountered the same
problem, and already figured out a solution to the problem.  I also post my
findings in hope that someone, who does a DejaNews search, and is looking
to solve the same problem, finds the post.  If people post questions here,
and the solutions, they are available 24 hours a day...and with no wait.

I also email support@xilinx.com with the problem/solution in hopes that
they 1) fix the 'problem' in a future release and 2) put the 'solution' in
their 'answer base'.




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