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Messages from 19150

Article: 19150
Subject: Tristate bidirectional pads with Xilinx
From: Davide Falchieri <davide.falchieri@bo.infn.it>
Date: Thu, 02 Dec 1999 16:48:18 +0100
Links: << >>  << T >>  << A >>
Hello,
   I have some problems with two Xilinx FPGA's 4025E-4. 
I am trying to implement tristate bidirectional pads since, on the same
pins, I have to receive commands and to send data out. 
The VHDL description and the output schematic obtained using Synopsys
seem fine, but when I download the bit file on the Xilinxs nothing works
as it should. Do you think something goes wrong during the place and
route with Alliance ?
Now I've even been told that Xilinx doesn't provide tristate
bidirectional pads at all: does anyone know if it is true ?

Thank you very much for your help.

Regards,
    Davide


_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
                                                      
                      Davide Falchieri                
           Physics Department, Bologna University     
        40127,Viale Berti Pichat 6/2, Bologna(ITALY)      
          TEL:+39-051-2095077, FAX:+39-051-2095297          
           URL:http://sunvlsi4.bo.infn.it/~davide     
            mailto:davide.falchieri@bo.infn.it     
                                                      
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Article: 19151
Subject: Question to synplicity users and other not Leonardo users,
From: Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid>
Date: Thu, 02 Dec 1999 08:12:21 -0800
Links: << >>  << T >>  << A >>
Hi,
I still  have the problem that Leonardo Spectrum  transfer my async
latches to sync latches in spite of
the fact, that Virtex have async latches in storage elements.
How is it by synplicity.
As example I send the VHDL you could try to synthesize
> > library ieee; use ieee.std_logic_1164.all;
> >
> > entity  LT  is
> > port (o : out std_logic ;
> >        r : in std_logic ;
> >       s : in std_logic );
> > end;
> >
> > architecture  LT  of  LT  is
> > begin
> > process (R,S)
> >
> > begin
> >   if  R='0' then o <='0';
> >       else if S='0' then o <='1';
> >             end if;
> >    end if;
> >
> > end process;
> > end;


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Article: 19152
Subject: Re: Tristate bidirectional pads with Xilinx
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Thu, 2 Dec 1999 10:25:29 -0700
Links: << >>  << T >>  << A >>
Davide Falchieri wrote in message <384694C2.41C67EA6@bo.infn.it>...
>Hello,
>   I have some problems with two Xilinx FPGA's 4025E-4.
>I am trying to implement tristate bidirectional pads since, on the same
>pins, I have to receive commands and to send data out.
>The VHDL description and the output schematic obtained using Synopsys
>seem fine, but when I download the bit file on the Xilinxs nothing works
>as it should. Do you think something goes wrong during the place and
>route with Alliance ?
>Now I've even been told that Xilinx doesn't provide tristate
>bidirectional pads at all: does anyone know if it is true ?


Please post your VHDL.  The Xilinx 4KE series certainly does provide
bidirectional pads - my last three designs using those parts used them!


-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

The secret of Slurm is on a need-to-know basis.



Article: 19153
Subject: Re: Command line for FPGA Express
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Thu, 2 Dec 1999 10:28:56 -0700
Links: << >>  << T >>  << A >>
Mark van de Belt wrote in message <944124247.568813@big.hacom.nl>...
>Hello,
>
>Is there a possibility to use a command line option for FPGA express for
>checking, synthesis and optimalisation?
>I presume that Xilinx foundation also calls FPGA express with a command
line
>option.

Yep, at least with the M2.1i tools and FE v3.3.  Look in your start menu
under Programs | Synopsys (or programs | Xilinx Foundation Series, which is
where I put it) and you'll see an item for the FPGA Express Shell.  I'm not
sure where it lives on a Unix box.


--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

The secret of Slurm is on a need-to-know basis.



Article: 19154
Subject: Virtex and JTAG configuration
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Thu, 02 Dec 1999 18:59:24 +0100
Links: << >>  << T >>  << A >>
Hi all
I have a problem with my Virtex JTAG... I have several error messages:
- Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan
chain test failed at bit position '3' on instance 'dcmproto(Device1)'.
- ERROR:JTag - Boundary scan chain has been improperly specified
- ERROR:JTag - : The boundary-scan chain has not been declared correctly

The device is an XCV100-PQ240. Among the possible error sources is a bad
.bsd file. Has anyone experienced JTAG configuration of this device and
encountered the same problem ?
(I'll check the PCB too...)

Thanks in advance

Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 19155
Subject: Connection of light diode and FPGA
From: Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid>
Date: Thu, 02 Dec 1999 10:13:20 -0800
Links: << >>  << T >>  << A >>
Hi,
A simple question:
I want to connect one of pins of Virtex to Light diode.
1.It must radiate by "1".
So I have to connect serially GND-300 Ohm resistor - diode -signal pin.
2.It must radiate by "0".
So I have to connect serially Vcc-300 Ohm resistor - diode -signal pin.


(I am not sure with current value)

Am I right?



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Article: 19156
Subject: Re: Connection of light diode and FPGA
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Thu, 2 Dec 1999 14:24:48 -0500
Links: << >>  << T >>  << A >>
I suppose this question is FPGA related...

Before you decide to connect a diode to a signal pin, find out how much
current it requires to be sufficiently illuminated. I believe that by
default, the Virtex pins only sink or source 12 mA. This can be increased to
24 mA (maybe more). However, you may not want to go that route, especially
if you're hooking up many diodes. You may be better off putting a simple
buffer between the FPGA and the diode because it will likely have more
robust I/O.

As for your question, you have the right idea. However, the appropriate
value for the resistor will depend on the specs for the diode. You'll want
to find out the voltage drop across the diode when it's turned on, as well
as the required illumination current I mentioned earlier. You can figure out
the required resistor value from that. It could very well be less than 300
Ohms, especially if VCC is 3.3 volts or less.

Cheers,
Jamie

Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid> wrote in message
news:065f8722.30014cf0@usw-ex0101-004.remarq.com...
> Hi,
> A simple question:
> I want to connect one of pins of Virtex to Light diode.
> 1.It must radiate by "1".
> So I have to connect serially GND-300 Ohm resistor - diode -signal pin.
> 2.It must radiate by "0".
> So I have to connect serially Vcc-300 Ohm resistor - diode -signal pin.
>
>
> (I am not sure with current value)
>
> Am I right?



Article: 19157
Subject: Re: Tristate bidirectional pads with Xilinx
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Thu, 2 Dec 1999 14:29:56 -0500
Links: << >>  << T >>  << A >>
Having a tri-state bi-directional signals implies a control signal or
signals which tell the I/O when to tri-state, when to drive, and when to
read. Usually the latter two are mutually exclusive. The most likely culprit
is that the polarity of a control signal isn't correct. That's easy to do
since everyone has different ideas about whether these signals should be
active high or active low.

Cheers,
Jamie

Davide Falchieri <davide.falchieri@bo.infn.it> wrote in message
news:384694C2.41C67EA6@bo.infn.it...
> Hello,
>    I have some problems with two Xilinx FPGA's 4025E-4.
> I am trying to implement tristate bidirectional pads since, on the same
> pins, I have to receive commands and to send data out.
> The VHDL description and the output schematic obtained using Synopsys
> seem fine, but when I download the bit file on the Xilinxs nothing works
> as it should. Do you think something goes wrong during the place and
> route with Alliance ?
> Now I've even been told that Xilinx doesn't provide tristate
> bidirectional pads at all: does anyone know if it is true ?
>
> Thank you very much for your help.
>
> Regards,
>     Davide



Article: 19158
Subject: CAN testing - Any CANbus cores out there?
From: Jonathan Bromley <jonathan@oxfordbromley.u-net.com>
Date: Thu, 02 Dec 1999 20:53:10 +0000
Links: << >>  << T >>  << A >>
"Raymond E. Rogers" wrote:
> > >   I am organizing a CAN-2.0B testing procedure.
<snip my suggestion>
> This is certainly feasable and has some advantages
<snip>
>  OTOH, it
> is not as general and synchronization with the MAC layer would have to
> be resolved.
 
Yes indeed. - hence my comment about fooling the Rx.
 
It occurs to me to ask whether anyone out there has a 
synthesisable VHDL core for a CAN controller.  It clearly 
wouldn't be cost competitive with commodity CAN parts
for production, but it sure as hell would make this kind
of diagnostic and special-purpose stuff far easier if you
had a working controller core to start from that you could
modify in an arbitrary way.
 
I would be **very** interested in getting involved in
any public-domain effort to realise this goal, as I
have upcoming projects for which it would be rather
useful.
 
I've posted this also to comp.arch.fpga and comp.lang.vhdl
(from sci.electronics.design) in the hope of exciting some 
interest.
 
Jonathan Bromley
Article: 19159
Subject: Re: backup fifo's
From: Eric Crabill <crabill@xilinx.com>
Date: Thu, 02 Dec 1999 12:55:22 -0800
Links: << >>  << T >>  << A >>
Hi Bruce,

No, this problem still exists.  If you are bus mastering a write,
there are several ways the transaction can end.  One of these
is disconnect without data by the target.  In such a case, you
(the bus master) will have popped data out of the FIFO, and
it will be sitting in the I/O output flip flops.  At this point, if the
target disconnects without taking it, your FIFO is out of
sync.

This behavior is described in section 3.3.3.2.1 "Target
Termination Signaling Rules" of the PCI 2.2 specification.

Also keep in mind that this is only an issue if your data source
is not prefetchable.  If the data source is prefetchable and you
are using the FIFO as a rate matching buffer, you can simply
flush the buffer when you are done.

Incidentally, backing up a FIFO built from RAM and address
pointers (counters) is very easy; you just have to use an up/down
counter for the read address pointer.

Thanks,
Eric Crabill

Bruce Nepple wrote:

> Assuming that I am bus mastering a write....Isn't the problem with the fifo
> being out of sync at the end of a transaction eliminated by the fact that
> the transaction can only be terminated by a stop (unless I end it), which
> will take the data just saved in the hidden register?  It's hard for me to
> see how (if I am writing) I can be out of sync after the transaction
> completes.
>
> Bruce

Article: 19160
Subject: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
From: SMiOUxrH <SMiOUxrH@UWlMRxgP.comNOSPAM>
Date: 2 Dec 1999 21:03:21 GMT
Links: << >>  << T >>  << A >>






<!-- Get Specific Variables for cobrand -->
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Article: 19161
Subject: Re: Tristate bidirectional pads with Xilinx
From: Dragon <hyarbr01@NoSpam.harris.com>
Date: Thu, 02 Dec 1999 16:11:21 -0500
Links: << >>  << T >>  << A >>
You don't need to use bidir tristates in a Xilinx 4000 to do what you are
trying to do. You do need to have a tristate for data going out of the
FPGA onto a data bus. But for data or commands coming into the
FPGA, try using clock enables for the registers that receive the
data or commands. Looks like this:


                                                                FPGA    |
Outside World
                                                                              |
     Tri_control _______                                          |
                                     |
|              | data bus
                                     |               DATA_PORT    |
|
     Data_out -------------|>------*-------------------------|-----------*
                                               |
|              |
                                               |
|               |
                             |---------|     |                                |
Command_reg----- | Q     D|----|                               |
Read_cmd---------- | EN     |                                     |
                             |           |                                     |

sys_clk --------------|>         |                                     |
                             |---------|                                     |

Hope that turns out. My ASCII art sucks! Think I'll keep my day job.
The VHDL code for it looks like this:

entity tristuff is
port (sys_clk                :in std_logic;
        DATA_PORT    :inout std_logic_vector(7 downto 0);
        <blah blah>);
end tristuff;

architecture behavioral of tristuff is

signal Tri_control        :std_logic;
signal Data_out            :std_logic_vector(7 downto 0);
signal Command_reg    :std_logic_vector(7 downto 0);
signal Read_cmd            :std_logic;

<other stuff>

begin

DATA_PORT <= Data_out when (Tri_control='1') else (others=>'Z');

tri_this:process(sys_clk,Read_cmd)
begin
if (sys_clk'event and sys_clk='1') then
    if (Read_cmd='1' )then
        Command_reg <= DATA_PORT;
    end if;
end if;
end process;

<rest of code>

That's it! When it's the FPGA's turn to drive the bus, set Tri_control='1'.
Data_out will also appear at the D input of Command_reg, but it doesn't
matter because the register is not enabled. When the FPGA is to receive
a command, set Tri_control='0' and Read_cmd='1'.

Also, make sure the enable (Read_cmd='1') comes after the 'event line.
This will infer the clock enable instead of an asynchronous set/reset.

All of the logic pictured should wind up in an IOB. There are tristates in
the FPGA other than those in the IOBs, but I've never seen them used for
anything other than wired-ORs and wired-ANDs. Has anyone found
them to be valuable?

                - Craig


Davide Falchieri <davide.falchieri@bo.infn.it> wrote in message

> news:384694C2.41C67EA6@bo.infn.it...
> > Hello,
> >    I have some problems with two Xilinx FPGA's 4025E-4.
> > I am trying to implement tristate bidirectional pads since, on the same
> > pins, I have to receive commands and to send data out.
> > The VHDL description and the output schematic obtained using Synopsys
> > seem fine, but when I download the bit file on the Xilinxs nothing works
> > as it should. Do you think something goes wrong during the place and
> > route with Alliance ?
> > Now I've even been told that Xilinx doesn't provide tristate
> > bidirectional pads at all: does anyone know if it is true ?
> >
> > Thank you very much for your help.
> >
> > Regards,
> >     Davide



Article: 19162
Subject: Re: Tristate bidirectional pads with Xilinx
From: Dragon <hyarbr01@NoSpam.harris.com>
Date: Thu, 02 Dec 1999 16:15:29 -0500
Links: << >>  << T >>  << A >>
ACK! It got hosed. If you're really interested in what it looks like,
email me and I'll draw you a picture.

            - Craig

Dragon wrote:

> You don't need to use bidir tristates in a Xilinx 4000 to do what you are
> trying to do. You do need to have a tristate for data going out of the
> FPGA onto a data bus. But for data or commands coming into the
> FPGA, try using clock enables for the registers that receive the
> data or commands. Looks like this:
>
>                                                                 FPGA    |
> Outside World
>                                                                               |
>      Tri_control _______                                          |
>                                      |
> |              | data bus
>                                      |               DATA_PORT    |
> |
>      Data_out -------------|>------*-------------------------|-----------*
>                                                |
> |              |
>                                                |
> |               |
>                              |---------|     |                                |
> Command_reg----- | Q     D|----|                               |
> Read_cmd---------- | EN     |                                     |
>                              |           |                                     |
>
> sys_clk --------------|>         |                                     |
>                              |---------|                                     |
>
> Hope that turns out. My ASCII art sucks! Think I'll keep my day job.































Article: 19163
Subject: Re: data serializer/decoder FPGA solution
From: "Holger Kleinert" <Holger@hollgi.de>
Date: Thu, 2 Dec 1999 22:48:28 +0100
Links: << >>  << T >>  << A >>
Manfred Kraus <mkrausnews@cesys.com> schrieb in im Newsbeitrag: 823gqf$bgk$1@thetenth.astat.de...
> I have to transmit data using an optical link (100 MBd).
> How can I serialize / encode and deserialize / decode
> the data using an FPGA only (no analog solution, no CPU) ?
> Are there any  pure digital solutions ?
> The way RS232 transmission works is not practicable (would need at least
> 400 MHz sampling clock)
Hi Manfred !
What about LVDS serializer/deserializer from National Semiconductor or TI ?
Example:
http://www.national.com/pf/DS/DS92LV1021.html
http://www.national.com/pf/DS/DS92LV1210.html
http://www.national.com/pf/DS/DS92LV1212.html

This are 10 Bit serializer/deserializer from National.

Gruss
Holger


Article: 19164
Subject: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
From: OxbIEcum <OxbIEcum@HudEShpv.comNOSPAM>
Date: 2 Dec 1999 22:12:47 GMT
Links: << >>  << T >>  << A >>






<!-- Get Specific Variables for cobrand -->
<!-- YESs and NOs are CaSe SeNsItIvE... Always use ALL CAPS for them! -->

    

   


<!-- EXTRA_CODE_AFTER_TOP/BOTTOM are typically used for consistent
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Article: 19165
Subject: Re: Tristate bidirectional pads with Xilinx
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 02 Dec 1999 15:54:47 -0800
Links: << >>  << T >>  << A >>
Here comes a slight correction:
In all Xilinx FPGAs, the read function is never turned off. You (can) always
read the signal on the pin.
The outputs generally have two controls: one drives the data High or Low, the
other enables or disables the output driver.
Permanently enabled, this makes it a conventional active output,
permanently diabled it's an input only.
Tying data and output enable together makes it an "open collector" or an "open
source" output ( depending on the OE or 3-state polarity chosen), and
controlling the enable/disable signal independently offers bidirectional I/O.

So, the hardware is very straightforward, but you have to observe the polarity
difference between Output Enable and Tristate.
Just read the nomenclature in English...

Peter Alfke, Xilinx Applications
======================
Jamie Sanderson wrote:

> Having a tri-state bi-directional signals implies a control signal or
> signals which tell the I/O when to tri-state, when to drive, and when to
> read. Usually the latter two are mutually exclusive. The most likely culprit
> is that the polarity of a control signal isn't correct. That's easy to do
> since everyone has different ideas about whether these signals should be
> active high or active low.
>
> Cheers,
> Jamie
>
> Davide Falchieri <davide.falchieri@bo.infn.it> wrote in message
> news:384694C2.41C67EA6@bo.infn.it...
> > Hello,
> >    I have some problems with two Xilinx FPGA's 4025E-4.
> > I am trying to implement tristate bidirectional pads since, on the same
> > pins, I have to receive commands and to send data out.
> > The VHDL description and the output schematic obtained using Synopsys
> > seem fine, but when I download the bit file on the Xilinxs nothing works
> > as it should. Do you think something goes wrong during the place and
> > route with Alliance ?
> > Now I've even been told that Xilinx doesn't provide tristate
> > bidirectional pads at all: does anyone know if it is true ?
> >
> > Thank you very much for your help.
> >
> > Regards,
> >     Davide

Article: 19166
Subject: Re: Tristate bidirectional pads with Xilinx
From: Dragon <hyarbr01@NoSpam.harris.com>
Date: Thu, 02 Dec 1999 20:41:20 -0500
Links: << >>  << T >>  << A >>
I suppose  it depends on whether or not the data bus uses an open-drain
(or source?) circuit. If the bus simply used tristates with external pullups, then

you wouldn't need to configure the output as open-drain. I assumed this when
I wrote the VHDL code. If open-drain is needed, then the VHDL must be
coded differently.

After reading the data book on the 4000E, it appears the I/O pins are not
configured to open-drain by default. You must make
special provisions in the code to configure the output for open-drain,
either by coding the VHDL to infer open-drain, or instantiating the
OBUFT symbol directly.

            - Craig

Peter Alfke wrote:

> Here comes a slight correction:
> In all Xilinx FPGAs, the read function is never turned off. You (can) always
> read the signal on the pin.
> The outputs generally have two controls: one drives the data High or Low, the
> other enables or disables the output driver.
> Permanently enabled, this makes it a conventional active output,
> permanently diabled it's an input only.
> Tying data and output enable together makes it an "open collector" or an "open
> source" output ( depending on the OE or 3-state polarity chosen), and
> controlling the enable/disable signal independently offers bidirectional I/O.
>
> So, the hardware is very straightforward, but you have to observe the polarity
> difference between Output Enable and Tristate.
> Just read the nomenclature in English...
>
> Peter Alfke, Xilinx Applications
> ======================



Article: 19167
Subject: Re: Command line for FPGA Express
From: "Austin Franklin" <austin@darkr88oom.com>
Date: 3 Dec 1999 04:15:52 GMT
Links: << >>  << T >>  << A >>
You can go to the FPGAEXP\bin-win32i directory of where your WorkView
Office is installed to find what executables are available.  It appears
there is an executable called "fe_shell.exe", and if you give it a "/?"
it'll show you the options.  You can apparently give it a script file (with
the -file option), and it will run that script.

It appears the script would contain commands like listed when you type
"fe_shell" and once it comes up, you type "help" and it gives you a very
long list of things you can do in the FPGA Express shell...

Another note is "fe.exe" wants a project name...but I don't know what it
does once you give it one...

If you create a script, I'd be interested in seeing what it looked
like...or if anyone has some example scripts, please share them!  I would
like to put this in a batch file that compiles the Verilog, then runs the
Xilinx tools...and gives me a placed and routed chip...


Andy Peters <apeters.Nospam@nospam.noao.edu.nospam> wrote in article
<826abt$21el$1@noao.edu>...
> Mark van de Belt wrote in message <944124247.568813@big.hacom.nl>...
> >Hello,
> >
> >Is there a possibility to use a command line option for FPGA express for
> >checking, synthesis and optimalisation?
> >I presume that Xilinx foundation also calls FPGA express with a command
> line
> >option.
> 
> Yep, at least with the M2.1i tools and FE v3.3.  Look in your start menu
> under Programs | Synopsys (or programs | Xilinx Foundation Series, which
is
> where I put it) and you'll see an item for the FPGA Express Shell.  I'm
not
> sure where it lives on a Unix box.
> 
> 
> --
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) noao \dot\ edu
> 
> The secret of Slurm is on a need-to-know basis.
> 
> 
> 
> 
Article: 19168
Subject: ghd
From: "ycp" <snaycp@sbell.com.cn>
Date: Fri, 3 Dec 1999 13:08:33 +0800
Links: << >>  << T >>  << A >>



Article: 19169
Subject: Re: Tristate bidirectional pads with Xilinx
From: Ray Andraka <randraka@ids.net>
Date: Fri, 03 Dec 1999 00:18:26 -0500
Links: << >>  << T >>  << A >>
If you want open drain type outputs, you tie the obuft I input to ground and the T
input to your internal signal you want to bring out as an open collector type.  That
way when the T pin is high, the output pin is hi-Z and when the T pin is low, it is
driving a logic low level.  The easiest way to make sure you get what you want in VHDL
is to instantiate the IOBs rather than letting the tool try to figure out what you
want.

architecture ...
component OBUFT
   port(
      O                              : out   STD_ULOGIC;
      I                              : in    STD_ULOGIC;
      T                              : in    STD_ULOGIC);
end component;

begin
    sample:OBUFT port map(
        O=> pad_signal,
        I => '0',
        T => internal_output_signal  --this is the internal signal 1=>'z'  and 0=> '0'

);


Dragon wrote:

> I suppose  it depends on whether or not the data bus uses an open-drain
> (or source?) circuit. If the bus simply used tristates with external pullups, then
>
> you wouldn't need to configure the output as open-drain. I assumed this when
> I wrote the VHDL code. If open-drain is needed, then the VHDL must be
> coded differently.
>
> After reading the data book on the 4000E, it appears the I/O pins are not
> configured to open-drain by default. You must make
> special provisions in the code to configure the output for open-drain,
> either by coding the VHDL to infer open-drain, or instantiating the
> OBUFT symbol directly.
>
>             - Craig
>
> Peter Alfke wrote:
>
> > Here comes a slight correction:
> > In all Xilinx FPGAs, the read function is never turned off. You (can) always
> > read the signal on the pin.
> > The outputs generally have two controls: one drives the data High or Low, the
> > other enables or disables the output driver.
> > Permanently enabled, this makes it a conventional active output,
> > permanently diabled it's an input only.
> > Tying data and output enable together makes it an "open collector" or an "open
> > source" output ( depending on the OE or 3-state polarity chosen), and
> > controlling the enable/disable signal independently offers bidirectional I/O.
> >
> > So, the hardware is very straightforward, but you have to observe the polarity
> > difference between Output Enable and Tristate.
> > Just read the nomenclature in English...
> >
> > Peter Alfke, Xilinx Applications
> > ======================



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 19170
Subject: Re: Connection of light diode and FPGA
From: "Olaf" <Olaf_Birkeland@coldmail.com>
Date: Fri, 3 Dec 1999 10:21:11 +0100
Links: << >>  << T >>  << A >>
Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid> wrote in message
news:065f8722.30014cf0@usw-ex0101-004.remarq.com...
> Hi,
> A simple question:
> I want to connect one of pins of Virtex to Light diode.
> 1.It must radiate by "1".
> So I have to connect serially GND-300 Ohm resistor - diode -signal pin.
> 2.It must radiate by "0".
> So I have to connect serially Vcc-300 Ohm resistor - diode -signal pin.
>
>
> (I am not sure with current value)
>
> Am I right?

Use a low current LED (like HP's HLMP1700), requires approx If=2 mA @
Vf=1.8V to get good visibility. The resistor is calculated as ( Vcc-Vf ) /
If = 750 Ohm. Your connection scheme is OK.

The low current reduces the current stress on the Virtex, and also
guarantees that the pin has a valid logic level when driving the LED (if
used as input to other devices as well).

Regards,
- Olaf




Article: 19171
Subject: Re: Virtex and JTAG configuration
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Fri, 03 Dec 1999 11:12:03 +0100
Links: << >>  << T >>  << A >>
Nicolas Matringe wrote:
> 
> Hi all
> I have a problem with my Virtex JTAG... I have several error messages:
> - Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan
> chain test failed at bit position '3' on instance 'dcmproto(Device1)'.
> - ERROR:JTag - Boundary scan chain has been improperly specified
> - ERROR:JTag - : The boundary-scan chain has not been declared correctly

I feel stupid replying to myself...
The PROGRAM pin was pulled low (I still don't understand why it has been
done so), which keeps the Virtex clearing his memory and prevents it
from doing anything else.

Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 19172
Subject: Re: Command line for FPGA Express
From: "Mark van de Belt" <mark@nospam.bs>
Date: Fri, 3 Dec 1999 12:24:43 +0100
Links: << >>  << T >>  << A >>
Hello,

I looked into this fe shell, and it is possible to create a batch file for
synthesis, but only if there is a FPGA express project. The foundation
software does not make this project.

The intention of this all is to use an other VHDL editor (Codewright) and to
synthesise the project from there (bypassing the foundation GUI and version/
revision philosophy). The design implementation is no problem, this is a
long series of batch commands (check the fe.log and you can see all the
batch commands for the implementation). The only thing is the syntax check
and the synthesis and optimalisation.

I think a lot of people can benefit from this.

Mark van de Belt


Article: 19173
Subject: Problems with routing Virtex device
From: "Johan Ditmar" <qtxjdit@al.etx.ericsson.se>
Date: Fri, 3 Dec 1999 14:14:17 +0100
Links: << >>  << T >>  << A >>
Hi there,

I am implementing a design on a Xilinx Virtex 1000 device and I have some
problems with routing my design:

Routing active routes does not take that long, maybe a few hours, but
routing PWR/GND gives a lot of problems. It happens often, that PAR simply
'hangs' at that point, by getting into some kind of loop. I have been
waiting many hours and it never finishes. I have to change my design then
(by changing the placement constraints in my .ucf file) and sometimes that
works. This is the case for both rather small and large designs.

This has happened many times and the only special thing about my design is
that I have a lot of placement constraints and carry chains. This might make
routing difficult, but why does PAR hang on routing PWR/GND then and not
active routes? Does someone else have this problem as well?

Johan


Article: 19174
Subject: Re: Problems with routing Virtex device
From: Ray Andraka <randraka@ids.net>
Date: Fri, 03 Dec 1999 09:26:27 -0500
Links: << >>  << T >>  << A >>
Power and ground are routed after all the active signals since you don't have
timing constraints on power and ground.  Your chosen placement is congesting the
routes enough that there is no way to route the power or ground signal to a
particular spot in the design.  When doing the floorplanning, you need to watch
out for excessive routing congestion as well as the distances on critical
routes.  Virtex does have a large routing resource, but it is far from infinite.

Johan Ditmar wrote:

> Hi there,
>
> I am implementing a design on a Xilinx Virtex 1000 device and I have some
> problems with routing my design:
>
> Routing active routes does not take that long, maybe a few hours, but
> routing PWR/GND gives a lot of problems. It happens often, that PAR simply
> 'hangs' at that point, by getting into some kind of loop. I have been
> waiting many hours and it never finishes. I have to change my design then
> (by changing the placement constraints in my .ucf file) and sometimes that
> works. This is the case for both rather small and large designs.
>
> This has happened many times and the only special thing about my design is
> that I have a lot of placement constraints and carry chains. This might make
> routing difficult, but why does PAR hang on routing PWR/GND then and not
> active routes? Does someone else have this problem as well?
>
> Johan



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka




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