Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 19225

Article: 19225
Subject: Re: hobbyist friendly pld?
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Tue, 07 Dec 1999 12:57:09 +0000
Links: << >>  << T >>  << A >>
Dan Rymarz wrote:
> 
> Hello all,
> 
> I am looking for a programmable logic technology I can use that
> also has a free+permanant (not 30 day trial) compiler available,
> that uses JTAG or similar few-wire (4 for jtag etc.) programming
> mode.  I don't need a large gate count.  ...

Have a look at Lattice.  They do an isp version of the trusty 22V10. 
The starter pack software to handle this is based on ABEL - again a
trusty "standard".  Software isn't free, but the deal on the starter
pack is normally pretty good, and includes some devices and a download
cable.  Info at
<http://www.latticesemi.com/products/destools/ispstarter.html>.  Lattice
also now incorporate Vantis (was AMD not that long ago), and there's a
similar starter kit for Vantis MACH parts
<http://www.latticesemi.com/products/destools/mstarter.html>.

Best deals of all, in my experience, come when you go along to a
company's introductory "seminar" presentation.  You pay for the day or
half-day, but get a free intro kit, plus manuals, plus several sessions
which are half-way between sales talk and "how-to" instruction.  There's
a fair amount of opportunity for some hands-on evaluation of the
software.  You sometimes get vouchers to use should you decide to buy
more of the stuff or to upgrade from starter kit to a higher level. 
Look up the main distributors of Lattice, and try to find out when the
next "roadshow" comes somewhere near you.

Usual warning I give to anyone getting into isp devices: take great care
with your power supply.  ispICs incorporate an on-chip voltage
multiplier.  If this sees a Vcc spike outside the absolute maximum
rating, it will turn the whole chip into an expensive multi-terminal one
Ohm resistor.  Check the Vcc for spikes BEFORE fitting the isp stuff -
don't rely on the fact that you've used this for years with all manner
of 74 series and stick-it-in-the-programmer PLDs - those devices will
take up to 100% overload spikes and (most of the time) not even go into
a reset or malfunction mode, certainly won't suicide.

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
The University of Southampton, UK

The University is not responsible for my opinions
Article: 19226
Subject: Problems with Leonardo Spectrum
From: "Thorsten Neumann" <thorsten.neumann@ese.de>
Date: Tue, 7 Dec 1999 14:46:40 +0100
Links: << >>  << T >>  << A >>
Hello,
I have problems during the synthesis of a small VHDL design in Leonardo
Spectrum.
Leonardo duplicates some of my packages! In the RTL schematic is all correct
but in the technology schematic
one block is double and not all of its ports are connected. I have tried the
most of the compiler switches, and
only the flatten design helps. But with this option the XPLA Professional
for the CoolRunner series can't
synthesize this edf because of the tristates.
Has someone else such problems? Or can someone help me with tips?

Thanks
Thorsten Neumann



Article: 19227
Subject: AM2901 bit slice processor
From: mikew@hmgcc.gov.uk (Mike)
Date: Tue, 07 Dec 1999 14:31:48 GMT
Links: << >>  << T >>  << A >>
Hello All,
	I am looking for an VHDL model for an AM2901 bit slice
processor. (very old Math co-pro). There are numerous web sites with
reference to this part because it is commonly used to teach the
fundamentals of processor achitecture.
	 However, there apear to be no complete VHDL implementations
available. Any ideas where I can find it ?

Regards

Mike
Article: 19228
Subject: tool command language (TCL)
From: raderrl@my-deja.com
Date: Tue, 07 Dec 1999 15:23:11 GMT
Links: << >>  << T >>  << A >>


Hi,

Where can I find a users manual for the TCL (tool command language)
language?  I would like to write TCL force vectors to use with Mentor
Graphics's ModelSim, and I don't know the language!

Thank you,
Regena


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19229
Subject: Re: Problems with Leonardo Spectrum
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Tue, 07 Dec 1999 21:41:58 GMT
Links: << >>  << T >>  << A >>
Without seeing the code and your script (if any), it's impossible to
understand what the problem is.

Have you tried your local Exemplar or Mentor Graphics tech support?

Cheers
Stuart

On Tue, 7 Dec 1999 14:46:40 +0100, "Thorsten Neumann"
<thorsten.neumann@ese.de> wrote:

>Hello,
>I have problems during the synthesis of a small VHDL design in Leonardo
>Spectrum.
>Leonardo duplicates some of my packages! In the RTL schematic is all correct
>but in the technology schematic
>one block is double and not all of its ports are connected. I have tried the
>most of the compiler switches, and
>only the flatten design helps. But with this option the XPLA Professional
>for the CoolRunner series can't
>synthesize this edf because of the tristates.
>Has someone else such problems? Or can someone help me with tips?
>
>Thanks
>Thorsten Neumann
>
>
>

An employee of Saros Technology:
Model Technology, Exemplar Logic, TransEDA, Renoir.
www.saros.co.uk
Article: 19230
Subject: Re: tool command language (TCL)
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Tue, 07 Dec 1999 21:41:59 GMT
Links: << >>  << T >>  << A >>
From memory the book I have is by Brent Welch. Useful, if a little too
much concentration on Tk, but the nuts and bolts are all there.

I've posted velow some Tcl examples that I touch upon when introducing
Tcl to my ModelSim customers. The first is simple, the other is a more
complex "magic breakpoint" that watches for multiple conditions and
then asserts the reset. If you need more, might I suggest your local
Model Technology representative?

Watch out for line wrap in the news reader.

Cheers
Stuart

Example 1
---------

when -label when1 {/testbench/uut/message_counter = 30 } {
    echo "Message counter is [examine /testbench/uut/message_counter]"
    echo "current output is [examine
/testbench/uut/state_machine/required]"
    stop} 


Complex Example 2
-----------------

set my_counter 1
set timekeeper 0

proc magic_bp {} {
    when -label when1 {/testbench/uut/message_counter = 31 } {
    echo "Message counter is [examine /testbench/uut/message_counter]"
    echo "current output is [examine
/testbench/uut/state_machine/required]"
    if {$my_counter == 20} then {
        echo "20 iterations completed"
        echo "time is $now"
        nowhen
        when -label when2 {clk'event and clk ='0' and
/testbench/uut/message_counter = 15 } {
            echo "Asserting reset"
            echo "time is $now"
            force -freeze /testbench/global_reset 0
            set timekeeper [expr ($now + 300)]
            echo "timekeeper set to $timekeeper"
            nowhen
            when -label reset_trap {clk'event and clk = '0'} {
                if {$timekeeper < $now} then {
                echo "Sim finished at $now"
                    stop }
                }
            }
        } else {
        echo "counter = $my_counter"
        set my_counter [expr ($my_counter +1)]
        }
    }
    }

On Tue, 07 Dec 1999 15:23:11 GMT, raderrl@my-deja.com wrote:

>
>
>Hi,
>
>Where can I find a users manual for the TCL (tool command language)
>language?  I would like to write TCL force vectors to use with Mentor
>Graphics's ModelSim, and I don't know the language!
>
>Thank you,
>Regena
>
>
>Sent via Deja.com http://www.deja.com/
>Before you buy.

For Email remove "NOSPAM" from the address
Article: 19231
Subject: Re: TIme Delay 1us-100ms
From: muzo <muzok@nospam.pacbell.net>
Date: 07 Dec 1999 16:58:05 EST
Links: << >>  << T >>  << A >>
Moussa Ba wrote:
> Good Day,
> What is the best to way to implement a Delay ranging from 1us to 100ms,
> I am synthesizing some verilog code for use with a xilinx xs4005xl.
> Could you please direct me to the best code construct for implementing
> such a delay.  The clock in my design is 8MHz and I am using Xilinx
> Foundation 1.5 software.
>
> Thank you in advance

I will take the trivial interpretation of this question and try to
answer it.
If you need a single programmable delay you can use a single
synchronous counter and reset it to overflow at different numbers to
implement the delay. 8 MHz has a 125 ns period so you need a counter
from 8 to 10e5 which a 17 bit counter can do. You can register the
signal you want to delay everytime the counter overflows. If you want
multiple delays of fixed size, you can do a ripple counter (you don't
want many 17 bit counters because of size) and divide 8 MHz into
smaller speeds. The you can pick the outputs of some of registers in
the ripple counter to drive much smaller synchronous counters the size
of which depends on the precision you need in the delay.

Hope this helps.
muzo

Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)
Article: 19232
Subject: Re: AM2901 bit slice processor
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Tue, 07 Dec 1999 17:21:32 -0500
Links: << >>  << T >>  << A >>
As I remember,it's been 20 years since I used one, the 2901 was trivial,
you should be able to write a model in a few minutes. The 2901 had a
16x4 register file, a 4 bit ALU and maybe a 1 bit left/right shift (I
don't remember exactly). There was no pipelineing to worry about. If you
can find the spec sheet somewhere, you should be able to implement it
with one case statement for the ALU and a couple of lines of code for
the reg file.


Mike wrote:
> 
> Hello All,
>         I am looking for an VHDL model for an AM2901 bit slice
> processor. (very old Math co-pro). There are numerous web sites with
> reference to this part because it is commonly used to teach the
> fundamentals of processor achitecture.
>          However, there apear to be no complete VHDL implementations
> available. Any ideas where I can find it ?
> 
> Regards
> 
> Mike
Article: 19233
Subject: Re: JTAG on PCI slot
From: "Holger Kleinert" <Holger@hollgi.de>
Date: Tue, 7 Dec 1999 23:46:14 +0100
Links: << >>  << T >>  << A >>
Bernard Esteban <esteban@worldnet.fr> schrieb in im Newsbeitrag: 82iq91$kpp$1@wanadoo.fr...
> Hi,
>
> Where can I find information how works JTAG signals on PC mother board ??,
> the goal, is to check if a PCI card with JTAG devices is well connected with
> on PCI slot. The JTAG connector is on PCI card.

JTAG is an optional feature of the PCI System.
The interfacing for this signal on a mainboard is vendor dependent.
Also the boundary scan order is vendor dependent.
I found no information regarding this manner in the PCI Spec V 2.2.

I guess the PCI-JTAG is most used for product verification during factory assembly.
--
mfg
Hollgi
http://www.hollgi.de





Article: 19234
Subject: Re: Actel Programming Information Sought
From: "Erich Wagner" <ewagner@pdq.net>
Date: Tue, 7 Dec 1999 17:46:12 -0600
Links: << >>  << T >>  << A >>
If you can't find a source for your Activator, contact tech support at BP
Microsystems (http://www.bpmicro.com ). They have been known to do small
favors for individuals in the past.


rk <stellare@NOSPAM.erols.com> wrote in message
news:384C772F.AE117798@NOSPAM.erols.com...
> IEC5 wrote:
>
> > Hello,
> >
> > I am looking for anyone with information on the Actel Activator One
> > FPGA programmer. To the best of my knowledge the kit included
> > a programming head, cable and PC ISA interface card plus documentation.
> > Specifically, if anyone can provide a part number for the PC ISA card,
> > it
> > would be greatly appreciated.
> >
> > I have a need to program 2 (two) ancient Actel Parts based on the 1020
> > family.
> >
> > I can be reached at:  iec5@pacbell.net
> >
> > Thanks-in-advance
> >
> > Dan
>
> have you contacted our actelian friends?
>
> here's some info, perhaps it will help.
>
> the activator one is pretty old and i haven't used it in a while.   i
> checked here at home, don't have the info, but i may have at my day job.
i
> did have an activator 1 there but it hasn't been used in many years.  i'll
> see what info i can dig out for you, although there's a good possibility
> that the techs trashed it.  i do (day job and home business) all the
> programming on the activator 2s and recently got their new programmer to
> try and keep somewhat up to date at day job.
>
> but anyways, i'm puzzled as to why you don't use the activator 2 for your
> old 1020 series parts.  all of the programming information is still in the
> software and runs on the activator 2 just fine.  in fact, we still
> routinely program the oldest model of that series, the 2.0 um A1020
> devices.  it works just fine.  i do note that the older devices are not in
> the drop down menus in designer; the info is there, it is just hidden.
> this is constantly a source of confusion and i know of no good reason why
> the parts aren't on the menus.  in any event, if you load the old database
> into the programming software (the file you load depends on what version
it
> was written in, it'll most likely be either a .def or a .afm) it'll call
up
> the correct programming algorithms.  the newest programming software may
> require you to convert your file.  i'm not using that, yet, since r1-1999
> did not support the actionprobe; i believe i'm running r3-1998.  i haven't
> received r2-1999 so i don't know if that'll still accept .def files or if
> the actionprobe "consideration" has been fixed.
>
> hope this helps some,
>
> ------------------------------------------------------------------------
> rk                                 The world of space holds vast promise
> stellar engineering, ltd.          for the service of man, and it is a
> stellare@erols.com.NOSPAM          world we have only begun to explore.
> Hi-Rel Digital Systems Design      -- James E. Webb, 1968
>


Article: 19235
Subject: Re: TIme Delay 1us-100ms
From: Ray Andraka <randraka@ids.net>
Date: Tue, 07 Dec 1999 18:55:24 -0500
Links: << >>  << T >>  << A >>
There are two types of delays.  Inertial and transport.  An inertial delay is somewhat
like a one-shot, in that a trigger event starts some sort of counter so that so many
clocks later there is an output.  Any additional events on the trigger either start
the time over or are ignored.  An inertial delay cannot reproduce a complex input
sequence where input events are spaced closer than the time of the delay.

The other type of delay is a transport delay, which is essentially a pipeline where
each sample of the input sequence is delayed and then reproduced at the output some
fixed time later.  The transport delay can be visualized as a pipeline thta takes a
finite time to traverse.  An input sequence is accurately reproduced at the output,
even when the events in the sequence are spaced closer than the length of the delay.

Muzo describes one way of doing an inertial delay, although in an FPGA, I would avoid
ripple counters unless you have a really good reason to use them.  Stick with
synchronous logic.  Inertial delays are usually implemented as a simple state machine
coupled to a counter.  The counter doesn't have to be binary, and in fact may be more
compact and considerably faster as a non-binary counter.  If your delay is an inertial
delay, a counter and some simple decode/state machine logic should do the trick.

If your delay is a transport delay, you need a memory element for each clock cycle of
the delay.  To help conserve resources, you want to clock that delay with the slowest
clock that still allows you to reproduce your input sequence faithfully.  That said,
it becomes obvious that for long delays, especially if the data is many bits wide that
this gets resource intensive.  In Altera devices, you are more or less forced to use
the LE flip-flops at one LE per bit per clock of delay.  If you only have a few of
these delays, you can use the EAB as RAM and implement a circular buffer for the delay
storage.  In Xilinx, you have the opportunity to use the CLB LUTs as small RAMs, which
means you can build delays up to 2 bits by 17 clocks in one 4000CLB or Virtex slice.
In that regard, the xilinx gives you much more flexibility and capability.  Some
synthesizers, such as synplicity, will infer the Virtex delay queues from a shift
register if you don't take outputs from intermediate taps.  I haven't seen any yet
that will infer a CLB RAM delay queue for xilinx 4K from just a delay spec.  You can
write the code as a RAM and circular buffer however, and it will work right.
Synplicity will infer CLB RAM if it recognizes the code as a RAM.  With FPGA Express,
I think you are still stuck with instantiating RAM16x1s primitives in your code.

muzo wrote:

> Moussa Ba wrote:
> > Good Day,
> > What is the best to way to implement a Delay ranging from 1us to 100ms,
> > I am synthesizing some verilog code for use with a xilinx xs4005xl.
> > Could you please direct me to the best code construct for implementing
> > such a delay.  The clock in my design is 8MHz and I am using Xilinx
> > Foundation 1.5 software.
> >
> > Thank you in advance
>
> I will take the trivial interpretation of this question and try to
> answer it.
> If you need a single programmable delay you can use a single
> synchronous counter and reset it to overflow at different numbers to
> implement the delay. 8 MHz has a 125 ns period so you need a counter
> from 8 to 10e5 which a 17 bit counter can do. You can register the
> signal you want to delay everytime the counter overflows. If you want
> multiple delays of fixed size, you can do a ripple counter (you don't
> want many 17 bit counters because of size) and divide 8 MHz into
> smaller speeds. The you can pick the outputs of some of registers in
> the ripple counter to drive much smaller synchronous counters the size
> of which depends on the precision you need in the delay.
>
> Hope this helps.
> muzo
>
> Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 19236
Subject: Re: AM2901 bit slice processor
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 8 Dec 1999 00:24:31 GMT
Links: << >>  << T >>  << A >>
"B. Joshua Rosen" <bjrosen@polybus.com> writes:

>As I remember,it's been 20 years since I used one, the 2901 was trivial,
>you should be able to write a model in a few minutes. The 2901 had a
>16x4 register file, a 4 bit ALU and maybe a 1 bit left/right shift (I
>don't remember exactly). There was no pipelineing to worry about. If you
>can find the spec sheet somewhere, you should be able to implement it
>with one case statement for the ALU and a couple of lines of code for
>the reg file.

There is a book with authors "Mick and Brick" that descibes these,
and their application in microprogrammed machines.

-- glen


>Mike wrote:
>> 
>>         I am looking for an VHDL model for an AM2901 bit slice
>> processor. (very old Math co-pro). There are numerous web sites with
>> reference to this part because it is commonly used to teach the
>> fundamentals of processor achitecture.
>>          However, there apear to be no complete VHDL implementations
>> available. Any ideas where I can find it ?
>> 
Article: 19237
Subject: Re: AM2901 bit slice processor
From: rk <stellare@NOSPAM.erols.com>
Date: Tue, 07 Dec 1999 19:33:15 -0500
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:

> "B. Joshua Rosen" <bjrosen@polybus.com> writes:
>
> >As I remember,it's been 20 years since I used one, the 2901 was trivial,
> >you should be able to write a model in a few minutes. The 2901 had a
> >16x4 register file, a 4 bit ALU and maybe a 1 bit left/right shift (I
> >don't remember exactly). There was no pipelineing to worry about. If you
> >can find the spec sheet somewhere, you should be able to implement it
> >with one case statement for the ALU and a couple of lines of code for
> >the reg file.
>
> There is a book with authors "Mick and Brick" that descibes these,
> and their application in microprogrammed machines.

it's called _bit-slice microprocessor design_, published by mcgraw-hill.

------------------------------------------------------------------------
rk                                 The world of space holds vast promise
stellar engineering, ltd.          for the service of man, and it is a
stellare@erols.com.NOSPAM          world we have only begun to explore.
Hi-Rel Digital Systems Design      -- James E. Webb, 1968

Article: 19238
Subject: Re: backup fifo's(2)
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Tue, 7 Dec 1999 19:08:00 -0800
Links: << >>  << T >>  << A >>
A backup fifo gets a little messy when you start dealing with full/empty
issues.  Little side effects that make things messy.

Actually, all you really need to do is to start another transaction on that
channel to flush the holding register.
That would be simpler than (in my case) 3 updown counters and messy logic.

Bruce

Eric Crabill <crabill@xilinx.com> wrote in message
news:3846DCBA.E741D25E@xilinx.com...
> Hi Bruce,
>
> No, this problem still exists.  If you are bus mastering a write,
> there are several ways the transaction can end.  One of these
> is disconnect without data by the target.  In such a case, you
> (the bus master) will have popped data out of the FIFO, and
> it will be sitting in the I/O output flip flops.  At this point, if the
> target disconnects without taking it, your FIFO is out of
> sync.
>
> This behavior is described in section 3.3.3.2.1 "Target
> Termination Signaling Rules" of the PCI 2.2 specification.
>
> Also keep in mind that this is only an issue if your data source
> is not prefetchable.  If the data source is prefetchable and you
> are using the FIFO as a rate matching buffer, you can simply
> flush the buffer when you are done.
>
> Incidentally, backing up a FIFO built from RAM and address
> pointers (counters) is very easy; you just have to use an up/down
> counter for the read address pointer.
>
> Thanks,
> Eric Crabill
>
> Bruce Nepple wrote:
>
> > Assuming that I am bus mastering a write....Isn't the problem with the
fifo
> > being out of sync at the end of a transaction eliminated by the fact
that
> > the transaction can only be terminated by a stop (unless I end it),
which
> > will take the data just saved in the hidden register?  It's hard for me
to
> > see how (if I am writing) I can be out of sync after the transaction
> > completes.
> >
> > Bruce
>


Article: 19239
Subject: Re: AM2901 bit slice processor
From: Bob Doyle <doyle@primenet.com>
Date: Wed, 08 Dec 1999 05:05:32 +0000
Links: << >>  << T >>  << A >>
Mike wrote:
> 
> Hello All,
>         I am looking for an VHDL model for an AM2901 bit slice
> processor. (very old Math co-pro). There are numerous web sites with
> reference to this part because it is commonly used to teach the
> fundamentals of processor achitecture.
>          However, there apear to be no complete VHDL implementations
> available. Any ideas where I can find it ?
> 
> Regards
> 
> Mike

Get the book:

VHDL for Programmable Logic
Kevin Skahill
Cypress Semiconductor
Addison Wesley
ISBN 0-201-89573-0

It devotes a chapter to the '2901 as
a case study.

Regards,
Bob
Article: 19240
Subject: Autologic II Xilinx Library
From: Sharif <sharif0326@hotmail.com>
Date: Wed, 08 Dec 1999 00:44:52 -0600
Links: << >>  << T >>  << A >>
Hello,

I am using Autologic II under solaris but I do not have the Xilinx
XC4000 Library. I tried the mentor graphics ftp site
(supportnet.mentorg.com) but couldn't find it. If anyone knows where I
can get the library please let me know.

Thank you for your help,

Sharif

Article: 19241
Subject: Re: hobbyist friendly pld?
From: nospam_ees1ht@ee.surrey.ac.uk (Hans)
Date: 8 Dec 1999 08:34:13 GMT
Links: << >>  << T >>  << A >>
Dan,

Try the Xilinx(Philips) Coolrunner family of PLD, they are reasonable dense, 
low power, EDA software (simulator+VHDL Synthesiser) is free from Xilinx. The 
simulator is basic but useable,

Hans.

>
>In article <384AD812.858079EF@boeing.com>, Dan Rymarz
><m261981@boeing.com> writes
>>Hello all,
>>
>>I am looking for a programmable logic technology I can use that
>>also has a free+permanant (not 30 day trial) compiler available, that
>>uses JTAG or similar few-wire (4 for jtag etc.) programming mode.  I
>>don't need a large gate count.  It seems like the  big devices need big
>>software, and the small ones need special programming hardware.  Does
>>anyone know where this holy grail of digital hobbyist devices exists -
>>free s/w and simple h/w?  
>>
>>                                                      Thanks,
>>                                                             Dan
>
>-- 
>Steve Dewey
>Remove 123 for email.

Article: 19242
Subject: Is there two-read one-write asynchronous SRAM in FPGA?
From: "anonymous" <jianjie@263.net>
Date: Wed, 8 Dec 1999 19:43:52 +0800
Links: << >>  << T >>  << A >>
Hi,
I want to use a three-port(two reads and one write) asynchronous SRAM(or
register file)
in my ASIC design. As the first step, I hope to verify my logic using
FPGA, but I'am not sure if some FPGA can provide this capability. If not,
are there some methods to implement the same function, for example, using
discrete SRAM device. Any information about multi-port SRAM in FPGA or ASIC
would be very appreciated.

jianjie


Article: 19243
Subject: Re: JTAG on PCI slot
From: Pete Dudley <padudle@sandia.gov>
Date: Wed, 08 Dec 1999 07:41:56 -0700
Links: << >>  << T >>  << A >>
Holger Kleinert wrote:
> 
> Bernard Esteban <esteban@worldnet.fr> schrieb in im Newsbeitrag: 82iq91$kpp$1@wanadoo.fr...
> > Hi,
> >
> > Where can I find information how works JTAG signals on PC mother board ??,
> > the goal, is to check if a PCI card with JTAG devices is well connected with
> > on PCI slot. The JTAG connector is on PCI card.
> 
> JTAG is an optional feature of the PCI System.
> The interfacing for this signal on a mainboard is vendor dependent.
> Also the boundary scan order is vendor dependent.
> I found no information regarding this manner in the PCI Spec V 2.2.
> 
> I guess the PCI-JTAG is most used for product verification during factory assembly.
> --
> mfg
> Hollgi
> http://www.hollgi.de


My guess is that the JTAG signals on the PCI connector are never used by
anyone for testing. JTAG is a very complicated and slow way to test.

On the other hand the JTAG signals on a PCI card could be very useful
for programming In System Programmable (ISP) devices.

	Pete Dudley
Article: 19244
Subject: Re: Is there two-read one-write asynchronous SRAM in FPGA?
From: Utku Ozcan <ozcan@mimoza.netas.com.tr>
Date: Wed, 08 Dec 1999 17:22:18 +0200
Links: << >>  << T >>  << A >>
anonymous wrote:
> 
> Hi,
> I want to use a three-port(two reads and one write) asynchronous SRAM(or
> register file)
> in my ASIC design. As the first step, I hope to verify my logic using
> FPGA, but I'am not sure if some FPGA can provide this capability. If not,
> are there some methods to implement the same function, for example, using
> discrete SRAM device. Any information about multi-port SRAM in FPGA or ASIC
> would be very appreciated.
> 
> jianjie

  The CLB's in Xilinx XC4000 FPGAs (E, EX, XL, XV) can be configured
  as exactly the same RAM type you want. These are called synchronous
  Dual Port RAMs. These RAMs have two-read and one-write terminals.

  Restrictions:

  1. RAM Address size must be between 16 and 256 and a multiple of 16
  (because of the CLB limitations).

  2. RAM Data size must be between 1 and 32.

  2. Write Address of Write Port and Read Address of one of the Read Ports
  are the same.

  Write system is fully synchronous, i.e. clock input and write enable,
  the read port which has the common read address input with write port
  is thus also synchronous. The remainder read port is purely asynchronous.

  Consider the features when prototyping your ASIC in FPGA.

  Utku

-- 
I feel better than James Brown.
Article: 19245
Subject: Re: Xilinx FPGA Map report question
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 08 Dec 1999 15:53:38 GMT
Links: << >>  << T >>  << A >>
<cross-posted from comp.lang.vhdl: putting timing constraints on
internal signals for synthesised code> 

On Tue, 7 Dec 1999 09:58:19 -0700, "Andy Peters"
<apeters.Nospam@nospam.noao.edu.nospam> wrote:

>>and find that only signals that are designated input/
>>output ports could be assigned timing constraints. All other signals I
>wrote
>>in my VHDL code has been placed in FPGA and renamed internally with LUT or
>>CLB numbers.
>
>
>Yup, welcome to the wacky world of synthesis.  see Kai's comments.  I'll
>echo his comment about a clock - is your design synchronous?  If so, you can
>place a period constraint on the clock pin and it will try to meet that
>constraint.  That's usually enough.  If not, you have to dig in to how
>constraints work.

as to the specific point of naming internal signals, this is generally
possible, if you're careful (and/or lucky). you'll probably need an
attribute set on your signal in the source; this seems to work for
Spectrum:

  attribute PRESERVE_SIGNAL of CE32_H : signal is true;

you'll need a different attribute for FPGA express - i don't know
which (or even if it exists). i also make sure that all required
signals are visible and attributed at the top level of the hierarchy,
so that i don't have to worry about specifying the hierarchy level in
the name.

you'll have to reference this signal in the UCF file. put a '*' after
it in case it has been duplicated by the synthesiser:

NET ce32_h* TNM = CE32;

check your reports to make sure that you've done what you intended to
do. if you're still getting a name mismatch, check the EDIF produced
by your synth, find the 'real' signal name (easy when you're used to
it), and use the real signal name in the UCF. however, be prepared to
go through this process again if a subsequent synthesis run causes the
name to change.

failing all this, there's actually a proper way to do this, but i
haven't tried it. simply put your timing constraints as attributes in
your VHDL source, and any name changes are then irrelevant. has anyone
had any success with this?

evan

Article: 19246
Subject: Re: Is there two-read one-write asynchronous SRAM in FPGA?
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Wed, 08 Dec 1999 16:52:35 GMT
Links: << >>  << T >>  << A >>
anonymous wrote in message <82lgam$gls$1@sunlight.pku.edu.cn>...
>Hi,
>I want to use a three-port(two reads and one write) asynchronous SRAM(or
>register file)
>in my ASIC design. As the first step, I hope to verify my logic using
>FPGA, but I'am not sure if some FPGA can provide this capability. If not,
>are there some methods to implement the same function, for example, using
>discrete SRAM device. Any information about multi-port SRAM in FPGA or ASIC
>would be very appreciated.

To my knowledge, there is no primitive device support for such a construct
in any commercial FPGA device.  In fact after musing aloud about such things
(3-ported and 4-ported SRAMs) a few years back I received a reply from a
commercial FPGA device architect praying that such things never come to
pass!

So you'll have to use 1-port or 2-port SRAMs.  For example, you can use:

* 1 1-port SRAM and do RRW accesses over 3 cycles

* 2 1-port SRAMs and do two RR access in one cycle and the W access in the
second cycle

* 1 2-port SRAM and do the one R access in one cycle and the RW access in
the second cycle,

* 1 2-port SRAM (like the Xilinx dual port select RAM) where you can do two
reads and one write per cycle assuming one of the read addresses is the
write address.

* 2 2-port SRAMs and do the two RR accessses and the W access in one cycle.

Note it may be possible to do read accesses in the first HALF cycle and the
write access in the second HALF cycle.  That's the way I build compact one
cycle 2R1W reg files from 2 1-port SRAMs.

See also these sources:

* http://www.deja.com/getdoc.xp?AN=491241651
* http://www.deja.com/getdoc.xp?AN=336757776&fmt=text (Altera vs Xilinx)
* http://www3.sympatico.ca/jsgray/homebrew.htm

Jan Gray



Article: 19247
Subject: constraints between clock domains: can't advance
From: Utku Ozcan <ozcan@mimoza.netas.com.tr>
Date: Wed, 08 Dec 1999 21:47:25 +0200
Links: << >>  << T >>  << A >>
Design Entry: Verilog
Synthesizer: Synplify v5.21
P&R: Design Manager M1.5 patched
Technology: XC4044XLA

We have two clock domains, 25 MHz and 6 MHz, and 25 MHz is derived
internally. Two separate FSM's in different clock domains communicate
to each other. Since implementation is quite fast, we directly perform
postroute simulations.

The problem is, that FSM's can't talk to each other in lab. FSM's are
alike, they have 1-bit states, at every execution the states are expected
to toggle, 0-1-0-1..., as we have seen at postroute simulations.

In board tests the FSM states don't toggle in 0-1-0-1 state sequences.
Sometimes it is 0-1-1-0... and clearly the chip malfunctions. It is quite
hard to cover in lab that this untoggle timepoint is somewhere around when
25 MHz and 6 MHz edges overlap.

To overcome this problem, we have inserted FF's between clock domains,
for a possibility of metastability etc. Signals between clock domains
are constrained with acceptable TIMESPEC commands. But no advance.

I have read several mails posted to newsgroup so far, the opinions
are centered to:

- incapability of resetting to complete system
- metastability condition right after reset deassertion

But I could not have found any obvious solution.

What do you recommend? Is it far good way to insert FF's between
the clock domains?

Utku

-- 
I feel better than James Brown.
Article: 19248
Subject: Re: Is there two-read one-write asynchronous SRAM in FPGA?
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Wed, 8 Dec 1999 14:57:51 -0500
Links: << >>  << T >>  << A >>
The simplest, least efficient, way to do this would be to duplicate all of
your data across two dual-port SRAM's. You'd hook up your write ports in
parallel between both, and attach your two read ports one to each. Depending
on how much memory you need, this may be the way to go. A more efficient,
but slightly more complex, way would be to run a single dual-port memory at
twice the required speed. With some time-sharing logic around the memory,
you could make it look like a three or four port device. Neither of these
options is terribly complicated because you only wanted one write port.

Seeing as this is comp.arch.fpga, I'll only comment on FPGA's. They have
limited amounts of memory, the exact amount being documented for the device.
Both Xilinx and Altera have devices with dual-port memory elements.

Cheers,
Jamie

anonymous <jianjie@263.net> wrote in message
news:82lgam$gls$1@sunlight.pku.edu.cn...
> Hi,
> I want to use a three-port(two reads and one write) asynchronous SRAM(or
> register file)
> in my ASIC design. As the first step, I hope to verify my logic using
> FPGA, but I'am not sure if some FPGA can provide this capability. If not,
> are there some methods to implement the same function, for example, using
> discrete SRAM device. Any information about multi-port SRAM in FPGA or
ASIC
> would be very appreciated.
>
> jianjie
>
>


Article: 19249
Subject: Re: constraints between clock domains: can't advance
From: Ray Andraka <randraka@ids.net>
Date: Wed, 08 Dec 1999 15:18:09 -0500
Links: << >>  << T >>  << A >>
It may not be metastability at all.  One machine may be cycling through the 0
1 0 before the other ever sees the 1.  It is a little unclear as to exactly
what you are doing, so my comments may or may not be on target.     The safe
way to go across async clock domain boundaries is to toggle a semaphore
flip-flop in the first domain (a change of level indicates an occurrence, not
a pulse), then in the second domain sense the change of level and generate the
pulse in that domain.  That will insulate you from problems where a pulse in a
faster domain gets missed by the slower one because it has come and gone
before the next rising edge.  It also lets you move the clock frequencies of
one domain without affecting the operation of the other to some degree.

Utku Ozcan wrote:

> Design Entry: Verilog
> Synthesizer: Synplify v5.21
> P&R: Design Manager M1.5 patched
> Technology: XC4044XLA
>
> We have two clock domains, 25 MHz and 6 MHz, and 25 MHz is derived
> internally. Two separate FSM's in different clock domains communicate
> to each other. Since implementation is quite fast, we directly perform
> postroute simulations.
>
> The problem is, that FSM's can't talk to each other in lab. FSM's are
> alike, they have 1-bit states, at every execution the states are expected
> to toggle, 0-1-0-1..., as we have seen at postroute simulations.
>
> In board tests the FSM states don't toggle in 0-1-0-1 state sequences.
> Sometimes it is 0-1-1-0... and clearly the chip malfunctions. It is quite
> hard to cover in lab that this untoggle timepoint is somewhere around when
> 25 MHz and 6 MHz edges overlap.
>
> To overcome this problem, we have inserted FF's between clock domains,
> for a possibility of metastability etc. Signals between clock domains
> are constrained with acceptable TIMESPEC commands. But no advance.
>
> I have read several mails posted to newsgroup so far, the opinions
> are centered to:
>
> - incapability of resetting to complete system
> - metastability condition right after reset deassertion
>
> But I could not have found any obvious solution.
>
> What do you recommend? Is it far good way to insert FF's between
> the clock domains?
>
> Utku
>
> --
> I feel better than James Brown.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search