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Messages from 20350

Article: 20350
Subject: Re: Count 1's algorithm...
From: a@z.com
Date: Mon, 07 Feb 2000 08:22:43 -0500
Links: << >>  << T >>  << A >>
Dragon wrote:

> 1. Count three 'ones' per CLB:
> With 2 sum bits you could count at most 3 ones. To count 16 ones you would need
> 5 CLBs and have one bit left over. Now you have five 2-bit numbers with one bit
> left over. If you add pairs of 2-bit numbers, you need 3 bits per sum. Since we
> have 3 pairs, we need 9 more CLBs. Now we have three 3-bit numbers. We can use
> 5 CLBs to add them together to get the five-bit result. This solution uses 19 CLBs
> with three levels of logic.
>
> 2. Use all 9 inputs per CLB:
> To count 9 ones we need a 4-bit result. In 4 CLBs we count the first 9 ones. In
> 3 CLBs we count the remaining 7. Now we have a 4-bit and a 3-bit number.
> Use 5 more CLBs to get the five-bit result. This solution uses 12 CLBs and
> two levels of logic.
>
> 3. Somewhere in the middle:
> With 2 sum bits you could count at most 3 ones. To count 16 ones you would need
> 5 CLBs and have one bit left over. Now you have five 2-bit numbers with one bit
> left over. Add three of the pairs of 2-bit numbers into a 4-bit sum. This would take
> 4 CLBs. Add the other two pairs and one left over bit into a 3-bit sum. This
> would take 3 CLBs. Use 5 more CLBs to get the five-bit result. This solution
> uses 17 CLBs and three levels of logic.
>
> Looks like solution 2 is the best way to go. If speed was not the issue, and you
> had access to a clock, I would go with Ray's suggestion of a shift reg and counter.
> Shift the bits and tap one stage to the clock enable of a 5-bit binary counter.
> That would need only 5 CLBs.
>
>         - Craig

Unfortunately solution 2 uses the false assumption that any 9-input function can be
mapped to one CLB. You cannot count 9 ones with just 4 CLBs.

Catalin

Article: 20351
Subject: Re: Xilinx "WebCD" gripes
From: rk <stellare@nospam.erols.com>
Date: Mon, 07 Feb 2000 08:33:12 -0500
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:

> rk <stellare@nospam.erols.com> wrote:
> : Hal Murray wrote:
>
> : For the previous post, I just noted that you can paste notes with Acrobat; obviously
> : not with a CD-ROM.  The data part of the CD-ROM is about 500 megabytes, so copying the
> : whole thing over to the hard disk is not too bad.  That does seem to work ok.
> : However, the directory and file names are not very descriptive so I couldn't be
> : selective in what I loaded and I would rather not load the whole thing.  My CD-ROM
> : reader isn't that fast so I like to have things on the hard disk, which is pretty
> : quick.
>
> I always wonder who produces those data book CDs. In most cases tons of
> senseless DLL are uploaded to your system ( some old TI data books were
> great at this) and files and directories have sensles names.
>
> The recent TI CD has for every PDF file a dirctory of the same name. Argh!
>
> Bye

I guess people who make $ making data book CD's. :-)  I do not like when you have to run
.exe's and load .dll's and modify this program and that (I believe this one links into the
browser).  I just want the computer to, er, compute and enough of this stuff and it won't
work and one will never find out why.

On the other hand, the Xilinx guys did give me a hardcopy databook and I find that I do use
that most of the time, then their www site, and finally the CD-ROM.

Have a nice day,

----------------------------------------------------------------------
rk                               The ability to carry out scientific
stellar engineering, ltd.        observations at a distance is
stellare@erols.com.NOSPAM        developing so rapidly that I don't
Hi-Rel Digital Systems Design    see any unique role for man in
                                 planetary exploration.
                                 -- Gordon MacDonald, National
                                 -- Academy of Sciences, 1968


Article: 20352
Subject: Re: ADC to DSP... FIFO?
From: "Paul Butler" <c_paul_butler@yahoo.com>
Date: Mon, 7 Feb 2000 08:52:17 -0600
Links: << >>  << T >>  << A >>

rk <stellare@nospam.erols.com> wrote in message
news:3896D039.4C2DF0B6@nospam.erols.com...
> Of course, we must mention that
> schematics are portable across humanoids.  Two humanoids reading the same
schematic will
> understand the design exactly the same.  Two humanoids reading the same
VHDL (or Verilog or
> C++ or whatever) code can not understand the design exactly the same way
since they are
> shielded from the design (except if the design is completely structural).
**
>

Unless my synthesizer is inserting or removing FFs from my design (FPGA
Express doesn't seem to), then the only thing synthesis seems to shield me
from is the implimentation of the combinatorial logic I specify.  If I draw
schematics of the same logic using the conventional primitives (and, or,
not), the mapper still has to convert that logic into look up tables (in the
cases of brand X and brand A), so I'm still shielded from the logic
implementation.  What's the difference?

As an example, my synthesizer tends to remove the redundant logic required
to overlap state decodes so that an output doesn't glitch.  The solution is
to register state machine outputs that can't glitch.  Doesn't the mapper do
the same thing to the logic in a schematic?

Paul Butler



Article: 20353
Subject: Why does Virtex has no EPROM support like XC4000
From: Kai Troester <troester@imms.de>
Date: Mon, 07 Feb 2000 15:55:30 +0100
Links: << >>  << T >>  << A >>
Maybe someone asked this question before. but i don't understand why the
designers of the Virtex family did not include the possibility to
download from an EPROM without an additional PLD. The XC4000 family had
this feature and I liked it very much. Does Xilinx has to much low
density pld and want to ship with every virtex one of these. But I think
a lot of Virtex users will take an Altera for this job. Or is there a
more lucid explanation ?

Kai
-- 
----- Dipl. Ing. Kai Troester -------------------------------------
IMMS - Institut fuer Mikroelektronik- und Mechatronik-Systeme gGmbH
Langewiesener Strasse 22, 98693 Ilmenau, Germany
Tel:    +49(3677)6783-42
Fax:    +49(3677)6783-38
mailto:kai.troester@imms.de
http://www.imms.de/~troester
-------------------------------------------------------------------
Article: 20354
Subject: Re: Xilinx "WebCD" gripes
From: Ray Andraka <randraka@ids.net>
Date: Mon, 07 Feb 2000 15:53:16 GMT
Links: << >>  << T >>  << A >>
Its a mix of html, pdf and ppt files, which would be fine except they are all named
wcd#####.pdf/html/ppt and are separated into folders called wcd#####.  Makes it kind
of hard to find anything without going through their program.

Hal Murray wrote:

> > HELLO XILINX, do you hear all this.  S**tcan the stuff you need to install and
> > give us plain old PDFs like you used to do.  The latest Applinx disk is not very
> > useful for much anything but a high tech frisbee.
>
> Is most of the info on the CD normal pdf files?  Does the new stuff
> do anything useful?  If so, it should be possible to have both modes.
>
> Run the installer if you want that mode.  Bypass it and browse
> directly if you don't want it "helping" you.
>
> --
> These are my opinions, not necessarily my employers.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20355
Subject: Re: Xilinx "WebCD" gripes
From: Ray Andraka <randraka@ids.net>
Date: Mon, 07 Feb 2000 15:53:17 GMT
Links: << >>  << T >>  << A >>
Its a mix of html, pdf and ppt files, which would be fine except they are all named
wcd#####.pdf/html/ppt and are separated into folders called wcd#####.  Makes it kind
of hard to find anything without going through their program.

Hal Murray wrote:

> > HELLO XILINX, do you hear all this.  S**tcan the stuff you need to install and
> > give us plain old PDFs like you used to do.  The latest Applinx disk is not very
> > useful for much anything but a high tech frisbee.
>
> Is most of the info on the CD normal pdf files?  Does the new stuff
> do anything useful?  If so, it should be possible to have both modes.
>
> Run the installer if you want that mode.  Bypass it and browse
> directly if you don't want it "helping" you.
>
> --
> These are my opinions, not necessarily my employers.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20356
Subject: How to get Synplicity to NOT use Global Clock for Virtex...
From: "Austin Franklin" <austin@dar88kroom.com>
Date: 7 Feb 2000 16:06:27 GMT
Links: << >>  << T >>  << A >>
I have a clock that I want to bring in on a regular I/O pin.  I have it
assigned to a non-BUFGP pin in the .ucf file...but prior to using that
file, Synplicity forces the use of a BUFGP...

I tried this:

  input		I_S_LF_SCK /* synthesis xc_padtype = "IBUF" */ ;

And that didn't stop it from using the BUFGP.  When I run the Xilinx tools,
it tells me I can't use the regular I/O pin with a BUFGP, and I need to get
Synplicity to NOT assign this input to a BUFGP.

Any suggestions?  The design is in Verilog, and I don't want to use the
'black box' instantiations if I can avoid it.


Article: 20357
Subject: Re: How to get Synplicity to NOT use Global Clock for Virtex...
From: "Austin Franklin" <austin@dar88kroom.com>
Date: 7 Feb 2000 16:13:33 GMT
Links: << >>  << T >>  << A >>
I found it:

/* synthesis syn_noclockbuf = 1 */

seems to work fine...


Austin Franklin <austin@dar88kroom.com> wrote in article
<01bf7185$382cc370$207079c0@drt1>...
> I have a clock that I want to bring in on a regular I/O pin.  I have it
> assigned to a non-BUFGP pin in the .ucf file...but prior to using that
> file, Synplicity forces the use of a BUFGP...
> 
> I tried this:
> 
>   input		I_S_LF_SCK /* synthesis xc_padtype = "IBUF" */ ;
> 
> And that didn't stop it from using the BUFGP.  When I run the Xilinx
tools,
> it tells me I can't use the regular I/O pin with a BUFGP, and I need to
get
> Synplicity to NOT assign this input to a BUFGP.
> 
> Any suggestions?  The design is in Verilog, and I don't want to use the
> 'black box' instantiations if I can avoid it.
> 
> 
> 
Article: 20358
Subject: Re: Conditional compilation in VHDL?
From: mench@mench.com
Date: 7 Feb 2000 11:32:49 -0500
Links: << >>  << T >>  << A >>
On Fri, 04 Feb 2000 19:42:13 GMT, in comp.lang.vhdl Mikhail Matusov
<matusov@ANNTIsquarepegSPPAMM.ca> wrote in article
<pYFm4.131$2a6.154350@news.magma.ca>:

> Mike Treseler <tres@tc.fluke.com> wrote in message
> news:389B1405.8529A3F8@tc.fluke.com...
>>
>> I define some boolean constants and jump around them.

> Can you tell me please how exactly you are jumping? I am kinda
> missing a syntax book at the moment so I am not sure what kind of
> "goto" statement I could use... Generate statement as it was pointed
> out in another post requires code to be syntactically correct and
> what is worse I believe it works only inside of processes. If it is
> not generate then what is it?

if ... generate works OUTSIDE of processes.

if ... then works INSIDE of processes.

Neither is a preprocessor construct, so all code, excluded or not, must
be at least statically semantically correct.

You can also use any number of preprocessors.  See the FAQ, located at
http://vhdl.org/comp.lang.vhdl, for more info.

Paul
-- 
Paul Menchini          | mench@mench.com |"Outside of a dog, a book is
Cadence Design Systems | www.orcad.com   | probably man's best friend, and
P.O. Box 71767         | 919-479-1670[v] | inside of a dog, it's too dark
Durham, NC  27722-1767 | 919-479-1671[f] | to read."	--Groucho Marx
Article: 20359
Subject: ASIC Opportunities
From: m.beard@vertex-solutions.co.uk
Date: Mon, 07 Feb 2000 16:47:28 GMT
Links: << >>  << T >>  << A >>
Apologies for any intrusion but I am looking for ASIC Designers to work
on the very latest in digital broadcast projects in the UK.
Please mail me for more info. You should be eligible to work in the UK.

See www.vertex-solutions.co.uk for other exciting opportunities


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20360
Subject: Floating license & Foundation Express
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Mon, 07 Feb 2000 18:01:27 +0100
Links: << >>  << T >>  << A >>
Hi
We are 2 engineers sharing 1 FPGA Express license. It should be all
right excepted that the project manager won't launch if it doesn't find
a valid license, so only 1 can work at a time.
I thought the floating license was only used with Synopsys, not the
whole program. Now that my design is synthesized, I can't improve the
p&r if the other one uses Foundation at the same time?


Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 20361
Subject: Re: Xilinx vs Altera
From: "John Janusson" <jjanusson@nospami-o.com>
Date: Mon, 07 Feb 2000 17:06:32 GMT
Links: << >>  << T >>  << A >>
I would recommend Xilinx Foundation because it includes Synopsys FPGA
Express, which I think most would agree is a better HDL synthesizer than
Altera's...  You also get a state machine entry program, which might make it
easier for beginners... Alas, neither come with a good VHDL simulator...  I
use ModelSim, so I can't comment on the simulator in Foundation...  I know
you can use the Aldec VHDL simulator right in the Foundation design flow,
but that's extra money.   I don't think you can put a VHDL simulator
seamlessly in the MAX-PLUS II design flow, but I'm not sure on this...

Altera's graphical waveform simulator is very easy to use for small designs.
MAX-PLUS II is quite mature and easy to use, but Xilinx has improved in this
regard in the last few years.  In my limited use of the schematic editors,
they seem to be a wash.   Foundation is a better platform for VHDL, though.

Of course, you should see what sort of deal you can cut with the vendors.
Cheap (or free) is good...

Good Luck,


JJ

Shawki Areibi wrote in message <3891C2B3.9FB4614E@uoguelph.ca>...
>We are introducing a new course on Digital Design at the School of
>Engineering
>at the University of Guelph. We would like to choose between the Altera
>MAXII-Plus and the Xilinx Foundation Series Software.
>Anyone with the experience of using the two systems? Which is better to
>use
>by the students (i.e simpler to use e.t.c)
>Thanks,
>Shawki Areibi
>
>--
>Shawki Areibi
>Assistant Professor
>School of Engineering
>University of Guelph
>Guelph, Ont, Canada N1G 2W1
>Tel: (519) 824-4120
>Fax: (519) 836-0227
>
>


Article: 20362
Subject: Re: Floating license & Foundation Express : Ooops
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Mon, 07 Feb 2000 18:24:50 +0100
Links: << >>  << T >>  << A >>
Nicolas Matringe wrote:
> 
> Hi
> We are 2 engineers sharing 1 FPGA Express license. It should be all
> right excepted that the project manager won't launch if it doesn't find
> a valid license, so only 1 can work at a time.
> I thought the floating license was only used with Synopsys, not the
> whole program. Now that my design is synthesized, I can't improve the
> p&r if the other one uses Foundation at the same time?

Looks like I had a problem and Synopsys had not released the license
after ending. Everything works fine now. Sorry.

Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 20363
Subject: Re: ADC to DSP... FIFO?
From: Mike Treseler <tres@tc.fluke.com>
Date: Mon, 07 Feb 2000 10:00:53 -0800
Links: << >>  << T >>  << A >>
Paul Butler wrote:

> Unless my synthesizer is inserting or removing FFs from my design (FPGA
> Express doesn't seem to), then the only thing synthesis seems to shield me
> from is the implimentation of the combinatorial logic I specify.  If I draw
> schematics of the same logic using the conventional primitives (and, or,
> not), the mapper still has to convert that logic into look up tables (in the
> cases of brand X and brand A), so I'm still shielded from the logic
> implementation.  What's the difference?

It is possible to make a schematic using only native logic
blocks. In this case the schematic will be very close 
to the primitive netlist. 

However, if the schematic designer uses higher level schematic elements
like shift registers or large muxes, your point is well taken.
The schematic is no longer directly related to the netlist.

A schematic of TTL functions is very easy to read for some humanoids.
Others find collections of algorithmic processes easier.

Mappers and synthesizers are getting smarter with each release.
Since you can get 1000 gates for less than $.40 in large devices,
I think designers should use whatever description lets them
work fastest.

> As an example, my synthesizer tends to remove the redundant logic required
> to overlap state decodes so that an output doesn't glitch.  The solution is
> to register state machine outputs that can't glitch.  Doesn't the mapper do
> the same thing to the logic in a schematic?

There may be arcane ways to shut off logic reduction.
But I agree with you, that synchronizing inputs 
and outputs is both easier and more reliable.

  -Mike Treseler
Article: 20364
Subject: Re: Virtex Fine Pitch BGA pcb layout
From: Greg Neff <gregneff@my-deja.com>
Date: Mon, 07 Feb 2000 18:54:55 GMT
Links: << >>  << T >>  << A >>
In article <J9Qj4.8623$uI1.146653@typhoon2.kc.rr.com>,
  "Matt Billenstein" <mbillens@one.net> wrote:
> We're actually getting into the layout now and I'm not so scared now
that
> I've found the "correct" dimensions and a suggested escape routing
note for
> the FG parts...  it turns out the solder balls on the FPGA are
substantially
> larger than the foot print that is suggested goes on the board...
thus, I
> get a ton of more room between pads to route stuff and place vias.
I'll
> forward the appnote to anyone who'd like to see; I don't think it can
be
> found on the Xilinx website.
>
> m
>
> Matt Billenstein
> http://w3.one.net/~mbillens/
> mbillens@one.net
>

I would love to see this appnote.  Please forward the appnote (or a
link to it) to me.  Thanks!

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20365
Subject: FLASH-based reconfigurability
From: "Paul Mondello" <paul.mondello@zydacron.com>
Date: Mon, 7 Feb 2000 16:41:33 -0500
Links: << >>  << T >>  << A >>
I have an application where I would like to be able to remotely re-program a
FLASH configuration PROM (XC18V00). The PROM and FPGA reside on an expansion
card inside a PC.

Basically I would like to be able to download a new FPGA configuration file
to the Host over the network, re-program the Flash PROM, and then
re-configure the FPGA with the new code. The FPGA will be connected to an
embedded processor which will handle the task of interfacing to the Host via
the PCI bus and passing the configuration bits to the FPGA, which will then
have the task of re-programming the Flash, I'm guessing through the JTAG
port. At that point the embedded processor will force the FPGA to
reconfigure.

Does anyone have any experience or ideas on how to do this? We basically
want a "simple" way to download feature changes and/or bug fixes to the FPGA
without having to remove the board from the PC.

Thanks in advance for any help you can provide.

-Paul

P.S. I have read a little about "Xilinx Online" and think that this method
is more complicated than what we need.



Article: 20366
Subject: Re: Conditional compilation in VHDL?
From: "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca>
Date: Mon, 07 Feb 2000 23:01:21 GMT
Links: << >>  << T >>  << A >>

<mench@mench.com> wrote in message news:87ms3h$nns$1@mench.mench.com...
> On Fri, 04 Feb 2000 19:42:13 GMT, in comp.lang.vhdl Mikhail Matusov

> if ... generate works OUTSIDE of processes.

I am probably  doing something dumb but I can't get this thing through the
syntax check. Here is the idea (not the actual code as I don't want to post
several pages) of what I am doing:

library IEEE;
use IEEE.std_logic_1164.all;

entity XXX is
    port (

    );
end XXX;

architecture xxx_rtl of XXX is

constant enableP2  : BOOLEAN := TRUE;

begin

P1: process (...)
begin
...
end process;

if enableP2=TRUE generate

P2: process(...)
begin
...
end process;

end generate;

end xxx_rtl;

Any suggestions why I am getting syntax error on if enableP2 line? I tried
constants, signals, variables of different types but it seems to be
something else. If I use simple "if" it passes. I am using latest rev of the
Xilinx Foundation tools.


Thanks,
Mikhail Matusov


Article: 20367
Subject: Re: Conditional compilation in VHDL?
From: Mike Treseler <tres@tc.fluke.com>
Date: Mon, 07 Feb 2000 15:24:47 -0800
Links: << >>  << T >>  << A >>
Mikhail Matusov wrote:

> if enableP2=TRUE generate
> 
> P2: process(...)
> begin
> ...
> end process;
> 
> end generate;
> 
> end xxx_rtl;
> 
> Any suggestions why I am getting syntax error on if enableP2 line? I tried
> constants, signals, variables of different types but it seems to be
> something else. If I use simple "if" it passes. I am using latest rev of the
> Xilinx Foundation tools.

Try 

if enableP2 generate

  -Mike Treseler
Article: 20368
Subject: Cool website... Engineering Salary Survey
From: menwright@hotmail.com (Mark Enwright)
Date: Mon, 07 Feb 2000 23:25:24 -0500
Links: << >>  << T >>  << A >>
 
Hey guys,
I recently found a website where I was able to determine my market value
based on my experience, industry, geography, and skills.  It is an easy way
to get information about salary and market trends.  My individual market
value was e-mailed back to me and I was better able to make decisions about
my career based on this valuable information.  I just thought I'd pass this
along since it is so important to be aware of your current market value.

Check it out.....http://www.gdsweb.com/survey.asp


Mark Enwright
Firmware Engineer
Real-Time Solutions
716.425.8009

-- 

 
Article: 20369
Subject: Re: ADC to DSP... FIFO?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Mon, 07 Feb 2000 23:42:30 -0500
Links: << >>  << T >>  << A >>
Paul Butler wrote:
> Unless my synthesizer is inserting or removing FFs from my design (FPGA
> Express doesn't seem to), then the only thing synthesis seems to shield me
> from is the implimentation of the combinatorial logic I specify.  If I draw
> schematics of the same logic using the conventional primitives (and, or,
> not), the mapper still has to convert that logic into look up tables (in the
> cases of brand X and brand A), so I'm still shielded from the logic
> implementation.  What's the difference?

First I would like to point out that FPGA Express is perfectly capable
of removing FFs. I tried to do a one hot FSM and found that I only got
15 FFs in a 16 state design. The IDLE state was being coded as no FFs
set. This was very disturbing to me since it meant that my FSM logic
would change depending on how I used the outputs! If I used the IDLE
output, it would remove one of the other FFs. This made it very hard to
simulate since I had to constantly redefine my vectors. 

The other really big problem I had was that the synthesizer was capable
of vastly enlarging my logic by nearly an order of magitude. Again in
the one hot FSM, I found it very difficult to find the exact coding
style that would prevent the synthesizer from decoding all 15 FSM
variables (FF outputs) as the inputs to all 15 variables. Kinda defeated
the purpose of one hot encoding. In general I always had to play with
the code to get a good implementation of any logic. The mapper never
blows up my logic in that way. 

 
> As an example, my synthesizer tends to remove the redundant logic required
> to overlap state decodes so that an output doesn't glitch.  The solution is
> to register state machine outputs that can't glitch.  Doesn't the mapper do
> the same thing to the logic in a schematic?

If this is all the synthesizer does, you are lucky. My project changed
synthesizers after I found that the one I started with was for all
purposes non-functional. That meant I had to adopt a new coding style to
get a good implementation. Then Xilinx changed synthesizers on me with
an upgrade. That meant I had to change coding styles again. Each time
required that I reverse engineer the logic produced and use trial and
error to get good results. 

I will go back to and HDL someday, but it won't be on any design where I
need to optimize for speed or size. It will have to be a project where I
need to meet a tight deadline with no constraints on chip size or
recurring costs. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 20370
Subject: Re: How to get Synplicity to NOT use Global Clock for Virtex...
From: Ken McElvain <ken@synplicity.com>
Date: 08 Feb 2000 00:01:26 EST
Links: << >>  << T >>  << A >>


Austin Franklin wrote:

> I have a clock that I want to bring in on a regular I/O pin.  I have it
> assigned to a non-BUFGP pin in the .ucf file...but prior to using that
> file, Synplicity forces the use of a BUFGP...
>
> I tried this:
>
>   input         I_S_LF_SCK /* synthesis xc_padtype = "IBUF" */ ;

Try:

input         I_S_LF_SCK /* synthesis syn_noclockbuf=1 */ ;


>
>
> And that didn't stop it from using the BUFGP.  When I run the Xilinx tools,
> it tells me I can't use the regular I/O pin with a BUFGP, and I need to get
> Synplicity to NOT assign this input to a BUFGP.
>
> Any suggestions?  The design is in Verilog, and I don't want to use the
> 'black box' instantiations if I can avoid it.

Article: 20371
Subject: Re: ADC to DSP... FIFO?
From: rk <stellare@nospam.erols.com>
Date: Tue, 08 Feb 2000 00:26:05 -0500
Links: << >>  << T >>  << A >>
Rickman wrote:

> Paul Butler wrote:
> > Unless my synthesizer is inserting or removing FFs from my design (FPGA
> > Express doesn't seem to), then the only thing synthesis seems to shield me
> > from is the implimentation of the combinatorial logic I specify.  If I draw
> > schematics of the same logic using the conventional primitives (and, or,
> > not), the mapper still has to convert that logic into look up tables (in the
> > cases of brand X and brand A), so I'm still shielded from the logic
> > implementation.  What's the difference?

Of course, it depends on the manufacturer that you're using.  There are other
brands.  When I use schematics, it is often at the hard macro level and I know
exactly what I am getting.  All I need to do is look at what I drew on the
schematic.  Some of the newer back end software has some optimizations in it.  If
I don't want a circuit element to disappear since it is not "logically needed," I
can attach a preserve attribute and it stays just the way I put it down.  For many
of the designs that I do with schematics, I would say that I am not shielded from
the logic implementation at all.

================

> First I would like to point out that FPGA Express is perfectly capable
> of removing FFs. I tried to do a one hot FSM and found that I only got
> 15 FFs in a 16 state design. The IDLE state was being coded as no FFs
> set. This was very disturbing to me since it meant that my FSM logic
> would change depending on how I used the outputs! If I used the IDLE
> output, it would remove one of the other FFs. This made it very hard to
> simulate since I had to constantly redefine my vectors.
>
> The other really big problem I had was that the synthesizer was capable
> of vastly enlarging my logic by nearly an order of magitude. Again in
> the one hot FSM, I found it very difficult to find the exact coding
> style that would prevent the synthesizer from decoding all 15 FSM
> variables (FF outputs) as the inputs to all 15 variables. Kinda defeated
> the purpose of one hot encoding. In general I always had to play with
> the code to get a good implementation of any logic. The mapper never
> blows up my logic in that way.

If you read an HDL file, as you point out, you don't know how the logic is
mapped.  Your experience with the "pretty much" one hot logic is similar to what
I've seen from several synthesizers.  Of course, by just looking at HDL code, how
can you tell if the state assignment is one-hot, binary, gray, or whatever unless
there are directives in it?  Frequently they are not there, you just get a piece
of HDL code to look at.

I've seen logic synthesizers do "logic replication" unless you get it shut off.
As I've seen someone else here post previously, the back end software can do so
also.

Another case that I've seen, when analyzing a failed design, is when a piece of
CAE code took a flip-flop and an inverter and converted it into two flip-flops,
one with a complemented output.  The two flip-flops wound up in an "inconsistent
state" and since the outputs were controlling some high current switches in a
motor, well, BOOM!  While originally mis-diagnosed as a failed FPGA - how can a
flip-flop output and it's inversion be the same value? - it turned out the
designer was not aware of how the CAE software helped him out.

Lastly, if it is important to the application, one must be able to ensure that
there are no lockup sets of states in the state machine.  For many of the
applications that I do, that is important.

Many times the output of the synthesizer is dependent on manufacturer, version,
input (as I saw, same as Rick, dependent on what output of the FSM that you use),
phase of the moon, etc.  Some applications it's a don't care.  For many hi-rel
systems, people do care.

Have a good evening,

rk


Article: 20372
Subject: Xilinx board
From: "Tanthanuch.SAWIT" <tsawit@electric.ee.psu.ac.th>
Date: Tue, 08 Feb 2000 16:25:08 +0700
Links: << >>  << T >>  << A >>
Dear all
    If we found these errors in XC4020E, how can I  do?
I have already install .BSDL file of XC4020E.


ERROR:basut - Boundary-scan chain test failed at bit position '1' on
instance 'mult_c(Device1)'.
 Check that the cable, system and device JTAG TAP connections are
correct,
 that the target system power supply is set to the correct level,
  that the system grounds are connected and that the parts are properly
decoupled.
ERROR:basut - Boundary scan chain has been improperly specified.  Please
check your configuration and re-enter the boundary-scan chain
information.
Boundary-scan chain validated unsuccessfully.
ERROR:basut - : The boundary-scan chain has not been declared correctly.

 Verify the syntax and correctness of the device BSDL files, correct the
files,
 reset the cable and retry this command.


Please suggest me.
Best Regard
Wannarat

Article: 20373
Subject: EDIF info
From: "Jose" <a_k_y@hotmail.com>
Date: Tue, 8 Feb 2000 10:53:05 +0100
Links: << >>  << T >>  << A >>
Hi, I would like to obtain more info about EDIF especification.
Thanks.

--
Jose (a_k_y@hotmail.com)


Article: 20374
Subject: Timing constraint on a DLL output
From: "Jean-Paul GOGLIO" <goglio@getris.alpes-net.fr>
Date: Tue, 8 Feb 2000 11:45:27 +0100
Links: << >>  << T >>  << A >>
Hi Everybody.

I want to design a FPGA (virtex E) with the following features:

I've got 2 data sources DataA and DataB, they are synchronous and they
toggle at 50 MHz.
I want to process them with the same component. Therefore, i use a DLL to
generate a 100 MHz Clock with the 50 MHz data Clock.

Now, i have to switch between DataA and DataB to generate the input data of
the component. Therefore, I use the output CLK90 (or CLK270) of the DLL.

DLL_Inst: CLKDLL port map(
    CLKIN  => Clk50MHz, -- Input Clk
    CLKFB  => ClkSimple, -- 50 MHz Clk
    RST    => Rst,
    CLK0   => CLK0,    -- 50 MHz Clk
    CLK90  => CLK90,
    CLK180 => CLK180,
    CLK270 => CLK270,
    CLK2X  => CLK2X,   -- 100 MHz Clk
    CLKDV  => CLKDV,
    Locked => Locked
    );

BufGSimple: BUFG port map (  -- 50 MHz Clk
 I => CLK0,
 O => CLKSimple
 );

BufGDouble: BUFG port map (  -- 100 MHz Clk
 I => CLK2X,
 O => CLKDouble
 );

GenClkSimpleR : process (ClkDouble, Rst)
begin  -- process GenClkSimpleR
    if Rst = '1' then
        ClkSimpleR <= '0';
    elsif ClkDouble'event and ClkDouble = '1' then
 ClkSimpleR <= CLK270;
    end if;
end process GenClkSimpleR;

SwitchData : process (ClkDouble, Rst)
begin  -- process SwitchData
    if Rst = '1' then
        DataCompIn <= (others => '0');
    elsif ClkDouble'event and ClkDouble = '1' then
 if ClkSimpleR = '1' then
  DataCompIn <= DataA;
 else
  DataCompIn <= DataB;
 end if;
    end if;
end process SwitchData

Component_Inst : Comp port map(
 Clk => ClkDouble,
 DataIn => DataCompIn ,
 DataOut => DataCompOut
 );


Now, my problem is I want to put a timing constraint on the net CLK270 and i
don't know how to do this.
This constraint can't neither be FF to FF nor Pad to FF.

Does anybody know how to specify it ? (I Use Foundation)

Second question : what about the skew between ClkSimple and ClkDouble
has anybody got any problem with this ?

J-P GOGLIO
GETRIS S.A.
13 Chemin des Prés
38240 Meylan
Tel : (33) 4 76 18 52 10
Fax : (33) 4 76 18 52 01
E-mail : goglio@getris.com






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