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Messages from 20900

Article: 20900
Subject: Re: Bit Serial Arithmetic De-mystified
From: sja@gte.net (Steven J. Ackerman)
Date: Sat, 26 Feb 2000 02:03:11 GMT
Links: << >>  << T >>  << A >>
On Thu, 24 Feb 2000 20:51:43 -0500, rk <stellare@nospam.erols.com>
wrote:

>Bob Cain wrote:
>
>> The first "home computer" that I know of was built by Don Hitt of IBM in
>> the early sixties out of a recirculating acoustic delay line with a
>> discrete component one bit ALU.  The architecture was ingeniously simple
>> and it was at least a Turing.  Programming it so that the data and
>> instruction you needed next was always close upstream was quite a
>> challenge though.
>
>More silly trivia ...
>
>The computer in the Saturn V launch vehicle was a serial machine - for example,
>a 26-bit add would take 82 us.
>
>Also, glass ultrasonic delay lines were used to improve reliability.  The main
>memory was duplex core.
>
>And, lastly, the computer was designed by IBM.
>
>Have a good evening,
>
>rk
>

Back in the mid-70s at the University of Florida, I worked as an
undergraduate on a project called CASSM - Context Addressed Segment
Sequential Memory.  Basically it was a fixed-head disc with multiple
bit serial processors - one per head - that could process a database
query against the entire disk's data in a single revolution. It used a
40-bit word and was implement with boards of TTL logic - the whole
shebang was interfaced to a Data General Nova minicomputer for I/O and
software development.

Anyway, I implemented many bit-serial adders/comparators/etc., and
used large shift registers to simulate the disk memory for development
and testing. As of last year, there was some discussion of
implementing this same bit-serial processing capability in DRAMs -
which have to be refreshed anyways - to process data in place, in the
memory device without moving it back and forth thru the main
processor.

--
Steven J. Ackerman, Consultant
ACS, Sarasota, FL
sja@gte.net
http://www.acscontrol.com
Article: 20901
Subject: Re: Design security
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 25 Feb 2000 21:41:13 -0500
Links: << >>  << T >>  << A >>
Andreas Heiner wrote:
> You're right, but the major problem is the copying of your design by
> "normal" criminals. We're using a copy protected small CPLD (e.g. 9572XL)
> and implement a back-coupled shift register and compares the behaviour of
> this CPLD inside the FPGA. Of course, if you want to reverse engeneer the
> design you can eleminate the design security. But this is a lot of work.
> Even if we can't protect our design 100% we should protect it as much as
> possible with possibly low cost. The external CPLD solution is such a
> solution.
> 
> Best regards,
> 
> Andreas Heiner

I believe that this is very similar to my own idea of using a unique
serial number chip from Dallas to provide security at the board level. A
circuit programmed inside the FPGA will read the serial number from the
Dallas chip. This is computed against a second number contained within
the FPGA. If a correct result is not obtained the FPGA will not operate.
The second number is loaded from software and is not a fixed part of the
FPGA. 

This is better than a software security check on the serial number in
that a software hack can not circumvent it. Another advantage is that
the serial number can be read out from the FPGA to uniquely identify the
board in a system. 

A weakness is that the serial number can be "hacked" by watching the IO
pin on startup and making another device to emulate the Dallas serial
number chip. Although this is not as hard as reverse engineering a CPLD,
the mechanical aspects would require a redesign of the circuit board. In
my application, I simply want to provide protection against someone
literally copying my design or buying boards and not software. This
happens overseas a lot from what I hear. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 20902
Subject: Re: Design security
From: imclaren@california.com
Date: Sat, 26 Feb 2000 09:57:30 GMT
Links: << >>  << T >>  << A >>
Rick,

I've used the Dallas DS2401 serial ID chips for just this "FPGA
validation" function myself.

The nice thing about them is that the smaller packages (surface mount,
not TO92) can be hidden under physically large components (such as an
electrolytic capacitor), which adds another layer of security. If the
bad guys can't see 'em, they might not suspect....

A serial code embedded as ROM in a CPLD can do the same thing, of
course. Pro: you get to use the CPLD for something else as well. Con: a
miscreant *knows* he has his work cut out for him (pls forgive male
specificity) as soon as he sees the CPLD.

Ian McLaren

>
> I believe that this is very similar to my own idea of using a unique
> serial number chip from Dallas to provide security at the board level.
A
> circuit programmed inside the FPGA will read the serial number from
the
> Dallas chip. This is computed against a second number contained within
> the FPGA. If a correct result is not obtained the FPGA will not
operate.
> The second number is loaded from software and is not a fixed part of
the
> FPGA.
>
> This is better than a software security check on the serial number in
> that a software hack can not circumvent it. Another advantage is that
> the serial number can be read out from the FPGA to uniquely identify
the
> board in a system.
>
> A weakness is that the serial number can be "hacked" by watching the
IO
> pin on startup and making another device to emulate the Dallas serial
> number chip. Although this is not as hard as reverse engineering a
CPLD,
> the mechanical aspects would require a redesign of the circuit board.
In
> my application, I simply want to provide protection against someone
> literally copying my design or buying boards and not software. This
> happens overseas a lot from what I hear.
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20903
Subject: Re: Foundation 2.1i device support?
From: imclaren@california.com
Date: Sat, 26 Feb 2000 10:25:01 GMT
Links: << >>  << T >>  << A >>
Hi Ewan,

This is *not* the definitive answer, but is at least from personal
experience. Others may answer at greater length and with greater
authority.

I have the Foundation Base 2.1i package DS-FND-BAS-PC (originally
version 1.4 in 1998, with a couple of upgrades). I am currently shipping
products, designed using the above, with XC95xx, Spartan, and Spartan XL
parts, so *YES THOSE WORK*!. I can create "what-if" designs using
Spartan II and Virtex (XCV50 only) parts, and get them to compile to
bitstream. I'm waiting for my Spartan II development board, however, to
try it in silicon....

My understanding is that the table labeled "Device Support" at
http://www.xilinx.com/products/found.htm
is accurate.

So, if you're looking for schematic-only support of the most
cost-effective parts (95xx, Spartan, Spartan II), the FND-BAS package
will probably work for you. I consider it one of the best $95 I've ever
spent.

Please note that Insight (www.insight-electronics --with whom I am in no
way affiliated) sells develoment boards for the Spartan XL and Spartan
II -- amongst others -- and the incremental cost to get Foundation Base
is about $70 ($195 vs $125 for board with no software). Their Spartan XL
board (XCS30XL)is in stock, and the Spartan II board (XC2S100-5)is
currently on a 6-8 week backlog (just don't take the one with my name on
it : ) ).

Please feel free to e-mail me with any more specific questions.

Ian McLaren
McLaren Research
Mountain View, CA 94043 USA
imclaren@california.com


In article <896gg2$l4f$1@sunfish.hi.com>,
  milne@hi.com wrote:
> The Xilinx Online Silicon Xpresso Cafe allows you to
> purchase Foundation 2.1i software in three packages:
>
>     DS-FND-BAS-PC         $95.00
>     DS-FND-BSX-PC         $495.00
>     DS-FND-EXP-PC         $2495.00
>
> These prices are presumably for 1-year renewable licensing.
>
> However, the product details pages and the product comparisons
> page contain different information about which devices are
> supported.  In particular, the product comparisons page shows
> that only XC4000 series parts are supported by any of these
> packages.  However, the product details pages claim that
> other device families are supported, such as XC3000, XC5200,
> Spartan, and Virtex XCV50.
>
> So, what devices are really supported by these packages?
> The DS-FND-BAS-PC package at $95.00 is very inexpensive, much
> like the Student Edition.  But the Student Edition device
> support was somewhat limited.
>
> I would be extremely pleased if the Base package contained
> support for all of the above mentioned device families.
>
> -Ewan
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20904
Subject: ISP in the Field
From: =?koi8-r?B?88HXwSD2ydfBzs/XyT8gKFNhdmEgWnhpdmFub3ZpY2gp?= <caba@eunet.yu>
Date: Sat, 26 Feb 2000 14:35:20 +0100
Links: << >>  << T >>  << A >>
Hi!

I need some advice.

We have to design telecom equipment that can be upgraded in the field.
That means microcontroler program and PL program.

In this moment we are using 68HC11 and Xilinx series 3 and 95.

Can we use SPI for programming PL over slave serial mode/JTAG port?
Is there any problem with the timing?

Thanks,
Sava

Article: 20905
Subject: Re: MRP systems
From: riclyons@ix.netcom.com (Rick Lyons)
Date: Sat, 26 Feb 2000 13:52:05 GMT
Links: << >>  << T >>  << A >>
On Tue, 22 Feb 2000 15:31:57 -0500, Rickman <spamgoeshere4@yahoo.com>
wrote:

>I have started a company to make several DSP boards and I am looking for
>a program to manage the parts procurement and tracking for manufacturing
>these boards. As it turns out, I am spending more time dealing with the
>management of the process than I am the engineering. A good MRP program
>would help me enormously. 
>
>It would also be good if it included or interfaced to an accounting
>package. I have considered using Quick Books for accounting simply
>because that is recommended by my accountant. 
>
>Anyone involved in the support of manufacturing that can offer some
>advice?
>
>Rick Collins
>

Hi Rick,
   How weird to see Quickbooks mentioned on 
comp.dsp!!   I use Quickbooks to manage the 
accounting for my bar.  I have a love-hate 
relationship with that damned software.
Anyway, just thought I'd recommend that you 
get some help from someone who's been using 
Quickbooks for a while (preferably someone 
using it in the way you intend to use it).

I say that because setting up the initial 
organization (structure) of your "Accounts" 
is so important.
Making changes to the overall organization of 
your accounting data is one royal pain in the 
butt after you've been using the software 
for six months.  All I'm saying is that 
careful thought when creating your "Company" 
in Quickbooks, at the start, will save you 
lots of heartache in the future.

If I had it to do over again, I would have 
initially organized my Quickbooks "Accounts" 
to correspond with the expense categories 
in Federal IRS Tax forms (for corporations).
This would have saved me *many* hours of pain 
at "tax time" each year.

Good Luck to you,
[-Rick-] 

Starting your own business is like getting in
the ring to fight three opponents - 
1) Your competitors, 2) the Federal Govt, and 
3) the State Govt.  You can keep an eye on your 
competitors, but not the Govts.  They'll sneak 
up and smack you from behind.

Article: 20906
Subject: IC Validation Engineers/Managers Wanted
From: margaretatwork@my-deja.com
Date: Sat, 26 Feb 2000 14:49:38 GMT
Links: << >>  << T >>  << A >>
Oxford & Associates in Portland, Oregon, is helping a local client
search for a product validation engineer to work 40+ hours a week
onsite (no telecommuting).  You must have experience in complex board
design, analog and digital design, FPGA design.  Very desirable:
experience with C and knowledge of ATM, Sonet, and frame relay.
Positions are available at the management and engineering levels.

Please respond with your resume.  It will be held in the strictect
confidence.  Principals only, please.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20907
Subject: Re: MRP systems
From: Ray Andraka <randraka@ids.net>
Date: Sat, 26 Feb 2000 15:19:06 GMT
Links: << >>  << T >>  << A >>
Intuit is the microsoft of accounting software.  The software is reasonably
priced, but then they soak you for even simple support and 'optional'
services that are essentially mandatory .  For example I just attempted to
upgrade to quickbooks pro for the time tracking.  When I tried to install it,
it couldn't find quickbooks on my system unless I had quickbooks open and
then it couldn't install.  Reinstalling quickbooks 6 not only didn't help the
problem, but also made so I couldn't access my existing data without getting
on-line to obtain an update.  Call customer support.  Well, after 10 minutes
of touch tone menus, that got me a 15 minute wait in line to the equivalent
of the front lobby desk.  The dweeb there wouldn't/couldn't  listen to what
the problem was, instead he told me he would put me in the tech support queue
(which is where I thought I called in the first place), but that the hold
time was about 56 minutes.  He then offered a "premier support option" for an
additional $169 which would move me to the front of the queue.  Don't tell me
money doesn't talk!  My guess is they just put you on hold until you are
ready to pony up the cash.  Anyway, I put it on the speaker phone and went
back to work.  Guess what, after 42 minutes the message changes to the "we're
sorry our offices are closed, please call back between the hours of... ".  I
didn't stay on long enough to hear the hours, but I suspect they are
something like 9am to 10am on even numbered thursdays and 4 to 5 pm on
fridays.
Oh, those mandatory 'optional' services?  The tax tables.  If you don't buy
the service,  you can't manually put stuff in a tax table, instead you have
to fill in all the numbers by hand everytime you cut a paycheck (this is done
on purpose to encourage you to pony up the cash for the service).   Now, I
get the postcards from the state telling me when tax tables change.  It would
take me less time to enter those by hand than it takes to dial up the
internet to download a new table.  For a small business with only one state
to worry about, why in the world should I have to subscribe to a 'service'

If I wasn't already locked into it by several years use, I'd dump quickbooks
in a heartbeat.

Rick Lyons wrote:

>
> Hi Rick,
>    How weird to see Quickbooks mentioned on
> comp.dsp!!   I use Quickbooks to manage the
> accounting for my bar.  I have a love-hate
> relationship with that damned software.
> Anyway, just thought I'd recommend that you
> get some help from someone who's been using
> Quickbooks for a while (preferably someone
> using it in the way you intend to use it).

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20908
Subject: Re: PCI 64 bit / 66 MHz
From: "peter dudley" <padudle@worldnet.att.net>
Date: Sat, 26 Feb 2000 17:08:08 GMT
Links: << >>  << T >>  << A >>
I saw a Silicon Graphics x86 workstation that had 64/66 PCI.

--
Pete Dudley

Arroyo Grande Systems

Markus Michel <mmichel@kontronmedical.ch> wrote in message
news:38B51BD7.80DBF07D@kontronmedical.ch...
> does anybody out there know where to get PC-motherboards which support
> PCI 64 bit / 66 MHz ???
> (or PCI 32 bit / 66 MHz, or PCI 64 bit / 33 MHz)
>
>


Article: 20909
Subject: Galois Coefficients g0,g1,...
From: "Pradeep Rao" <pradeeprao@planetmail.com>
Date: Sun, 27 Feb 2000 00:36:21 +0530
Links: << >>  << T >>  << A >>
Hi,
I'm working on a Reed-Solomon codec RS(255,239).
Does anyone know where I might find tables for the generator polynomial
coefficients for different values of (n,k).
I've tried deriving them from the pimitive polynomial but it gets too
cumbersome to do it on paper for such large values.
Thanks in anticipation,

Regards,
Pradeep Rao








Article: 20910
Subject: Re: MRP systems
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 26 Feb 2000 15:56:19 -0500
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> Intuit is the microsoft of accounting software.  The software is reasonably
> priced, but then they soak you for even simple support and 'optional'
> services that are essentially mandatory .  For example I just attempted to
...snip...
> If I wasn't already locked into it by several years use, I'd dump quickbooks
> in a heartbeat.
>
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka

Interesting comments. Quick Books was recommended by my accountant.
Likely not so much because he thinks it is a good package, but because
that is what they are using. Very much like why Microsoft is the defacto
standard for office applications. It doesn't have to be good. It is what
everybody else is using. 

I have found a couple of MRP related packages that might be both
affordable enough and useful enough to justify buying. The big problem
is just what you have run up against. The package was good enough for
your immediate needs, but later as your needs change, problems show up
in support, the price of add-ons or just plain limitations in what it
can do. Since this is an area that is new to me, I don't know what to
expect to need in the future and so I don't know what to look for. 

One package I have found is pc/MRP from the company of the same name. In
addition to addressing the MRP related functions like inventory control,
BOMs, purchasing, receiving... it has an accounting portion. So I might
not need a separate package like Quick Books. At $400 for a single
license, it isn't too much if I have to scrap it in a year or two. They
work with dBASE III+ dbf files, so the basic data can be read by many
data base applications. 

They also have a lot of options at $200 each; ECO, Sales Quote, Purchase
Request (as opposed to Purchase Order), serial number and others. So the
final price can easily be $1000 or more. 

They have a demo, but you have to buy it for $35! Of course that is not
much of a barrier since I would be spending much more than that for my
time to evaluate any package. 

Anyone know anything about the pc/MRP package?


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 20911
Subject: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
From: John <johnm0@hotmail.com>
Date: Sun, 27 Feb 2000 01:36:42 GMT
Links: << >>  << T >>  << A >>
Unfortunately, Xilinx's DLLs are not capable of clock recover from a
Manchester encoded signal. Running at 125M is no problem. Your clock
recovery would have to be done externally.

Anthony Ellis - LogicWorks wrote:
> 
> Seeing thiis whole thread is about PLL's etc. I have a simple question?
> 
> Given a Manchester encoded input at 125Mhz. Can one use a Zilinx PLL, DPLL
> or whatever to generate a phase sync'd clock at 125Mhz  to extract the data?
> 
> Thanks Anthony
> 
> Don Husby wrote in message <8746qh$spc$1@info3.fnal.gov>...
> >Ray Andraka <randraka@ids.net> wrote:
> >> I hadn't considered a VCO made as a ring oscillator.
> >
> >Take a look at the Lucent 3T parts.  Their clock synchronizer
> >can be used in either DLL or PLL mode.  It's implemented as a
> >multi-tap voltage-controlled delay line.
> >
> >
> >--
> >Don Husby <husby@fnal.gov>             http://www-ese.fnal.gov/people/husby
> >Fermi National Accelerator Lab                          Phone: 630-840-3668
> >Batavia, IL 60510                                         Fax: 630-840-5406
Article: 20912
Subject: Re: Design security
From: krw@attglobal.net (Keith R. Williams)
Date: 27 Feb 2000 03:08:19 GMT
Links: << >>  << T >>  << A >>
On Fri, 25 Feb 2000 18:00:07, Tom Burgess 
<tom.burgess@hia.nrc.ca> wrote:

> Those concerned about design security against determined crackers with well equipped labs
> will find little reassurance in the following survey paper: "Tamper Resistance - a Cautionary Note"
> http://www.cl.cam.ac.uk/users/rja14/tamper.html

Yikes!  I did work on the tamper resistance that SR White was 
talking about in:

  An early example, whose design rationale was published in 
detail, is 
  the ĉABYSS coprocessor developed by IBM. A variety of tamper 
resistant 
  packages were tested for ease of penetration and ease of 
manufacturing, 
  including stannic oxide lines on glass, piezo-electric sheets 
and a 
  number of wire winding techniques. The designers settled on a 
four layer
  wrapping of 40 gauge (80 ĉm diameter) nichrome wire surrounding
the 
  processor, battery, memory and sensor circuitry, and embedded 
in a 
  hard, opaque epoxy filled with silica to make it harder to 
machine 
  and more likely to crack under UV laser ablation [WC87] 
[Wei87]. 

However, I don't recall it being named uABYSS.  I was the key 
storage and physical security team leader on the IBM Integrated 
Cryprographic Facility (ICRF) for the IBM 3090 and ES9000 
systems.  There were many hardware checks involved in the 
environmental controls and tamper detection.  However, there was 
never any doubt that someone with infinite resources could break 
the system.  Hell, it would be cheaper to buy-off the trusted 
employees.

The latest incarnations of the product use asymetric keys for 
security, rather than tamper-hardening.  There are still trusted 
employees doing this work.  All crypto-systems require trust 
somewhere along the line. 

.. no I didn't put in any back doors (I was a trusted employee 
;-), even though the Fed used these things to transfer *huge* 
number of bit$.  A small percentage of the bit$ would make me 
very happy. ;-)

Anyway, this article only touched the things we protected 
against.  Ten years later this stuff would be so much simpler, 
but then again the attackers so much more sophisticated.

Now, back to trying to get my FPGA's working.  ;-)

----
  Keith


Article: 20913
Subject: Xilinx 1802/4 SPROMs....anyone get them to actually work?
From: "Austin Franklin" <austin@da33rkroom.com>
Date: 27 Feb 2000 03:18:06 GMT
Links: << >>  << T >>  << A >>
I've got a board with one XCV300 and one SPROM (VQ-44) in a JTAG chain. 
The Virtex is first in the chain.  I had an 1802 as the PROM, and it gave
me an error when I tried to program it (saying it was read protected, and
even erasing it wouldn't help), so Xilinx suggested replacing it with an
1804.  Now I can program the SPROM, but it won't verify, and doesn't appear
to work.

The Virtex loads just fine over JTAG, and works.  No problems there.  Has
anyone had similar problems with the 1804, and has anyone gotten one to
work?  Voltage and pinouts all checkout fine, the JTAG programmer
recognizes it just fine....

Thanks



Article: 20914
Subject: Re: Xilinx 1802/4 SPROMs....anyone get them to actually work?
From: "Austin Franklin" <austin@da33rkroom.com>
Date: 27 Feb 2000 04:38:38 GMT
Links: << >>  << T >>  << A >>
Minor update...according to the Xilinx web site, verify doesn't work. 
Great.  The only way to see if it was programmed is to look at the bit
stream (or let it program the FPGA and look for DONE)...but I currently get
all 1's out of the SPROM...as if it wasn't programmed at all.

Also, the JTAG programmer claims it programs the SPROM just fine, and that
I can erase it just fine, but it fails blank check....  I'm led to believe
it just isn't programming the 1804 at all...even though it says it did.


Austin Franklin <austin@da33rkroom.com> wrote in article
<01bf80d1$393e2f00$207079c0@drt1>...
> I've got a board with one XCV300 and one SPROM (VQ-44) in a JTAG chain. 
> The Virtex is first in the chain.  I had an 1802 as the PROM, and it gave
> me an error when I tried to program it (saying it was read protected, and
> even erasing it wouldn't help), so Xilinx suggested replacing it with an
> 1804.  Now I can program the SPROM, but it won't verify, and doesn't
appear
> to work.
> 
> The Virtex loads just fine over JTAG, and works.  No problems there.  Has
> anyone had similar problems with the 1804, and has anyone gotten one to
> work?  Voltage and pinouts all checkout fine, the JTAG programmer
> recognizes it just fine....
> 
> Thanks
> 
> 
> 
> 
Article: 20915
Subject: clocked or not clocked?
From: Jamil Khatib <khatib@ieee.org>
Date: Sun, 27 Feb 2000 14:23:09 +0200
Links: << >>  << T >>  << A >>
Hi,
Which is preferable to have a clocked memory core or un clocked one and
when can use each one

Thanks
Jamil Khatib
OpenIPCore Project  http://www.openip.org/oc

Article: 20916
Subject: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
From: =?koi8-r?B?88HXwSD2ydfBzs/XyT8gKFNhdmEgWnhpdmFub3ZpY2gp?= <caba@eunet.yu>
Date: Sun, 27 Feb 2000 15:39:58 +0100
Links: << >>  << T >>  << A >>
Use programmable PLLs like:
1) ICS502
2) ICS525
3) other variant programmable over wire (i2c, spi...)
4) Cy2291
5) Cy2292

PLLs like 4046, 7046 made us a very big problem.

Regards,
Sava

Dominique SZYMIK <szymik@nospam.univ-lille1.fr> wrote in message
news:38B260D3.C1A9D7BE@nospam.univ-lille1.fr...
>
>
> jim granville wrote:
>
> > nestor@ece.concordia.ca wrote:
> > >
> > > Thanks Peter, Ray and Hal for your input.
> > >
> > >   Since creating a completelly digital DPLL in an FPGA looks to be
> > > quite difficult, what about creating a hybrid PLL where only the
> > > voltage-controlled oscillator would be external (analog) and the rest
> > > (phase detector, loop filter and divide-by-N) would be designed in the
> > > FPGA?
> >
> > Yes, look at the data on 74HC4046/74VHC4046 ( Philips,TI,Mot,Fairchild
> > etc ).
> >
> > This shows alternatives for Phase/freq detectors, the simplest is a XOR
> > gate.
> > You could even trail their VCO circuit on a FPGA :-).
>
> DON'T DO THAT!
> Power supply noise will kill your attempts to get a good jitter.
> Instead use a LC vco (74HC04 gates will do) with a separate voltage
> regulator
> and even an additionnal RC decoupling (say 220uF, 100R) or a crystal vco
> (VCXO)
> if your reference frequency tolerances are tight.
>
> Forget the XOR gate, if the loop bandwidth is smaller than the vco control
> range it will
> NEVER lock alone.
> Instead use a phase / frequency comparator but not with a tristate output
> like on HC4046
> you got a good AN there:
> <http://www.latticesemi.com/lit/docs/designexamples/cpld/an8017.pdf>
> Beware of fpga's 'high' logic levels on outputs. For phase comparators
> outputs  you must
> pullup them or better, buffer them externally.
>
> With the preceding phase comp, you must use an  differential op amp loop
> filter, it will
> give you common mode mode supply noise rejection, and good control on loop
> bandwidth
> / damping.
>
> > If you the multiplied freq is fixed, and known, then a LC/Varicap Diode
> > VCO
> > can work well.
>
> It works also with variable mult. frequ.!!!
>
> At last you should at last give your reference frequency stability and
your
> precise
> requirements as to your multiplied frequency jitter. If you don't tell
what
> you need
> nobody will give you useful answers. Pll design is not straigtfoward if
you
> want performance.
>
> D.
>
>
>

Article: 20917
Subject: Re: Foundation 2.1i device support?
From: Peter <peterc@hmgcc.gov.uk>
Date: Mon, 28 Feb 2000 12:07:03 +0000
Links: << >>  << T >>  << A >>
Ewan D. Milne wrote:
> 
> The Xilinx Online Silicon Xpresso Cafe allows you to
> purchase Foundation 2.1i software in three packages:
> 
>     DS-FND-BAS-PC         $95.00
>     DS-FND-BSX-PC         $495.00
>     DS-FND-EXP-PC         $2495.00
> 
> These prices are presumably for 1-year renewable licensing.
> 
> However, the product details pages and the product comparisons
> page contain different information about which devices are
> supported.  In particular, the product comparisons page shows
> that only XC4000 series parts are supported by any of these
> packages.  However, the product details pages claim that
> other device families are supported, such as XC3000, XC5200,
> Spartan, and Virtex XCV50.
> 
> So, what devices are really supported by these packages?

All of the families that you list are I believe supported.
(I know for certain that XC3000, XC4000, Spartan and Virtex are).

Note that some of the earlier parts are no longer supported by the
latest software (e.g. 3000A/3100A are but non-A early devices are not).

An e-mail to Xilinx ought to be able to supply a full list.
-- 
Peter Crighton
Article: 20918
Subject: Xilinx Abel Problems
From: jrei7227@aol.com (JRei7227)
Date: 28 Feb 2000 15:46:04 GMT
Links: << >>  << T >>  << A >>
Hello, I am an electronics technician for a small company.  Currently
I'm trying to learn Xilinx for a project that I'm working on.  I'm
trying learn how to set up a state machine but the examples given by
Xilinx help don't seem to work.  When I try to simulate the following
code, All of my outputs are flat - lined.  In the report I get message
about dangling ports that  don't understand.  Please help.
Thanks,
Jeremy Nuckols


module jrmysim1
Title 'a simple learning program'


Declarations

//input pins
a PIN;
b PIN;
clk PIN;
enabl   PIN;
//output pins
c PIN istype 'reg';
d PIN istype 'reg';
e PIN istype 'reg';
f PIN istype 'reg';
sreg1 state_register;
s1 state;
s2 state;
s3 state;


Equations

 c = a & b;
 d = a # b;
 sreg1.clk = clk;

state_diagram sreg1

  state s1:

 e = a & b;
 f = 0;

 if enabl == 1 then s2;

  state s2:

 e = a # b;
 f = 1;

 if enabl == 1 then s3;

  state s3:

 e = a $ b;
 f = 0;

 if enabl == 1 then s1;

end







Article: 20919
Subject: PCI 64 bit / 66 MHz
From: Malachy Devlin <m.devlin@nallatech.com>
Date: Mon, 28 Feb 2000 17:17:54 -0000
Links: << >>  << T >>  << A >>
Hi,

We've got a Supermicro PIIIDME in our lab, which has 2 64bit 66Mhz PCI
slots in it.

regards

Malachy
http://www.nallatech.com

> -----Original Message-----
> From: Markus Michel [mailto:mmichel@kontronmedical.ch]
> Posted At: 24 February 2000 11:54
> Posted To: fpga
> Conversation: PCI 64 bit / 66 MHz
> Subject: PCI 64 bit / 66 MHz
> 
> 
> does anybody out there know where to get PC-motherboards which support
> PCI 64 bit / 66 MHz ???
> (or PCI 32 bit / 66 MHz, or PCI 64 bit / 33 MHz)
> 
> 

Article: 20920
Subject: Re: Xilinx Abel Problems
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Mon, 28 Feb 2000 10:07:19 -0800
Links: << >>  << T >>  << A >>

JRei7227 wrote: <snipped>
> 
> Equations
> 
>  c = a & b;
>  d = a # b;
>  sreg1.clk = clk;

You need a clock for your other regs:

[c,d,e,f].clk = clk;

regards, 
Tom Burgess
-- 
Digital Engineer
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3
Article: 20921
Subject: atmel fpga starter kit
From: nojunk@nojunk.com (myself)
Date: Mon, 28 Feb 2000 18:34:35 GMT
Links: << >>  << T >>  << A >>
hi i just ordered the atmel fpga starter kit and will receive it in a
few weeks.
Does anybody have any experiance with them? What did you think?
Article: 20922
Subject: PCI Core Problem
From: " Antonio Joaquim A Esteves" <esteves@di.uminho.pt>
Date: 28 Feb 2000 19:22:16 GMT
Links: << >>  << T >>  << A >>

Hello,

We designed a prototyping board with Xilinx FPGAs and a PCI 
interface implemented with the Xilinx LogiCORE 2.0.2 (slave
only) and a 4013XLT device.

The board has been used, but a problem remain unsolved:

"on faster PCs and/or when using optimized s/w to implement 
read/write operations that access the FPGAs, these operations 
seem not to succeed and in some situations the operating 
system (OS) hangs up".

What makes the OS to hang up when executing a sequence of 
"a writing operation (to send a FPGA configuration 
byte) followed by a read operation (to read FPGA status)" with
optimized code ? 
The interrupt signal seems not to be asserted ...

Since h/w logic adds long delays, we decided to deassert SREADY
signal for one state during read operations. Can this cause problems ?
 
Any ideas will be apreciated.
Regards.  

 -----------------------------------------------------
 Antonio J A Esteves 
 Departamento de Informatica - Universidade do Minho 
 Largo do Paco - 400-320 Braga Codex - Portugal

 Phone:  +351 253 604454  Fax: +351 253 604471 
 E-mail: esteves@di.uminho.pt
 Web:    http://www.di.uminho.pt/~esteves/
 -----------------------------------------------------


Article: 20923
Subject: Re: atmel fpga starter kit
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Mon, 28 Feb 2000 12:39:57 -0700
Links: << >>  << T >>  << A >>
myself wrote in message <38babfc9.20583432@news.magma.ca>...
>hi i just ordered the atmel fpga starter kit and will receive it in a
>few weeks.
>Does anybody have any experiance with them? What did you think?

why didn't you ask before you ordered the kit?

--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens



Article: 20924
Subject: Re: atmel fpga starter kit
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 28 Feb 2000 11:48:37 -0800
Links: << >>  << T >>  << A >>
I consider it impolite and bad netiquette to post without a name.
If you are ashamed of yourdelf, don't post !

Peter Alfke, speaking for himself.

myself wrote:

> hi i just ordered the atmel fpga starter kit and will receive it in a
> few weeks.
> Does anybody have any experiance with them? What did you think?



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